New high resolution and low distortion coherent sweep oscillators

In this paper, a new coherent digital sweep oscillator is proposed and its performance is evaluated. The proposed oscillator employs piecewise parabolic interpolation to decrease the look-up-table (LUT) size and system complexity while maintaining excellent spectral performance. The interpolation coefficients are predetermined in such a way that optimizes the spectral performance of the oscillator and are stored in the LUT. The interpolator generates the sample values of the sine wave using the optimized predetermined interpolation coefficients from the calculated phase. Hence, a few reference sample values and the optimized coefficients are stored in a small LUT. The complexity of the oscillator structure is decreased by eliminating one of the two multipliers needed to implement the interpolator. The proposed oscillator is simulated using optimized coefficients for different number of quarter sine wave segments. A comparison between the new oscillator and previously reported sweep oscillators indicates its superior performance and hardware efficiency. The ratio of the LUT size needed for the new oscillator is found to be 1:128 when compared with that of Pedersen oscillator with 12-bit address lines and 14-bit word length.     

Improved switching mode oscillators employing generalized switching lines

The present work proposes an unusual method for controlling the activation of the switches of switching mode oscillators. The proposed method is in fact a tool for developing switching mode oscillators that are controlled by full variable feedback. The methods developed in the present article rely on characterizing the switching procedure by intentionally moulding the related switching line (the switching line is the line in the state space, where the switches change polarity). The switching line in most of the switching mode oscillators is relatively simple. For example, in many cases the switch changes state in accordance with the output current sign. Hence, the line ‘output current’ is zero, is the switching line in this case. Relatively many advantages are attained by the present moulding of the switching line. For example, oscillators that oscillate even with very low‐quality factor (large load) are obtainable. The proposed method enables a simple way for controlling the output voltage and the frequency of the switching mode oscillator. Furthermore, current limiter property of the oscillator output can be obtained by the method, even in cases where the original oscillator is inherently a voltage source. The output impedance is also made controllable by the method. The successfully improved characteristics are demonstrated by investigating a particular structure, namely, a switching mode series resonant oscillator. Copyright © 2000 John Wiley & Sons, Ltd.     

Systematic realization of a class of hysteresis chaotic oscillators

A systematic method for realizing a class of hysteresis RC chaotic oscillators is described. The method is based on direct coupling of a general second‐order sinusoidal oscillator structure to a passive non‐monotone current‐controlled non‐linear resistor. Owing to this passive non‐linearity, the power consumption, supply voltage and bandwidth limitations imposed upon the chaotic oscillator are mainly those due to the active sinusoidal oscillator alone. Tunability of the chaotic oscillator can be achieved via a single control parameter and the evolution of the two‐dimensional sinusoidal oscillator dynamics into a three‐dimensional state‐space is clearly recognized. The flexibility of this method is demonstrated by two examples using PSpice simulations and experimental results. Numerical simulations of derived mathematical models are also shown. Copyright © 2000 John Wiley & Sons, Ltd.     

一种新颖的正弦正交编码器细分方法

提出了一种不用查询表的正弦正交编码器细分方法,利用控制系统临界稳定原理生成一个高频数字正弦载波与采样得到的正弦编码信号实时比较来获取相位信息;与传统查询表细分方法相比,节省了大量的存储空间,而且整个细分过程通过软件实现,不需要添加额外的硬件;同时阐述了影响细分分辨率的因素,推导出了防止电机高速运行时细分混叠的条件;最后...     

一种新颖的正弦正交编码器细分方法

提出了一种不用查询表的正弦正交编码器细分方法,利用控制系统临界稳定原理生成一个高频数字正弦载波与采样得到的正弦编码信号实时比较来获取相位信息;与传统查询表细分方法相比,节省了大量的存储空间,而且整个细分过程通过软件实现,不需要添加额外的硬件;同时阐述了影响细分分辨率的因素,推导出了防止电机高速运行时细分混叠的条件;最后,以一台7kW的电梯用永磁同步电机配套海德汉的ERN487-2048正弦增量式编码器为平台,验证了该细分方法用于转子初始位置识别及速度控制的可行性。     

用于旋转变压器的新型正弦波振荡源技术研究

精密伺服系统中需要高精度、大驱动能力的正弦波振荡源为大负载旋转变压器提供激磁信号,为了满足精密伺服系统对于高精度振荡源的设计需求,基于可编程振荡器AD2S99实现了一种新型的适用于旋转变压器的正弦波振荡源,主要介绍了硬件电路的工作原理,对电路进行了PSPICE仿真和实际编码系统测试。测试结果证明,该设计满足大负载旋转变压器的驱动要求,可用于代替价格昂贵、供货周期长的国外专用振荡源芯片;且成本低、电路结构简单、实用性强。     

Digital hardware implementation of a current controller for IMvariable-speed drives

This paper presents the design of an induction machine current controller that is entirely implemented in digital hardware. A hardware current controller allows high switching frequencies with only modest processing power, as well as simplified controller hardware and software. The paper briefly presents the concepts of the algorithm implemented, and then outlines the changes that are made to make the digital implementation even more efficient. It then discusses the architecture used for the hardware design. Experimental results are presented to demonstrate the algorithm's performance     

一种新的基于SVPWM策略的死区补偿方法

在基于SVPWM的电压源逆变器中死区时间的插入是必不可少的.这将导致电压和电流的畸变,也就是所谓的死区效应.对这一问题提出了许多不同的补偿方法.在传统的平均死区电压补偿方法基础上提出了一种新的改进方法,在运行速度很低时该方法比传统的方法有更小的电压和电流畸变,而且由软件实现,不需要增加额外的硬件.仿真试验结果证实了该方法的有效性.     

可扩展多输入多输出信道高效模拟器研制

针对现有信道模拟器通道规模受限、扩展性差等缺陷,设计实现了一种可扩展的多输入多输出(multiply-input multiply-output, MIMO)信道高效模拟器。 该模拟器采用改进的坐标旋转数字计算(coordinate rotation digital computer, CORDIC)算法,只 需较少硬件资源便可实现大规模多支路的随机信道衰落精确模拟。 基于 MIMO 信道离散化模型提出了一种可扩展的硬件模拟 架构,并结合现场可编程门阵列(field-programmable gate array, FPGA)的并行处理优势,进行硬件实现及实测验证。 针对 3GPP 标准扩展车载 A 信道模型(extended vehicular A model, EVA)静态场景和时变场景的实测结果表明,所研制的 MIMO 信道模拟 器输出时延功率谱和多普勒功率谱等统计特性均与理论值吻合,可用于无线通信设备的方案验证、算法优化和性能分析。     

Sinusoidal shaping of the ISF in LC oscillators

A new method to decrease the phase noise of the sinusoidal oscillators is proposed. The proposed method is based on using a dynamic transistor biasing in a typical oscillator topology. This method uses the oscillator impulse sensitivity function (ISF) shaping to reduce the sensitivity of the oscillator to the transistor noise and as a result reducing the oscillator phase noise. A 1.8 GHz, 1.8 V designed oscillator based on the proposed method shows a phase noise of ?130.3dBc/Hz at 1 MHz offset frequency, thereby showing about 6 dB phase noise decreasing in comparison with the typical constant bias topology. This result is obtained from the simulation based on 0.18u CMOS technology and on‐chip spiral inductor with a quality factor equal to 8. Copyright © 2007 John Wiley & Sons, Ltd.     

Sinusoidal oscillators with lower gain requirements at higher frequencies based on an explicit tanh(x) nonlinearity

Two novel sinusoidal oscillator structures with an explicit tanh(x) nonlinearity are proposed. The oscillators have the attractive feature: the higher the operating frequency, the lower the necessary gain required to start oscillations. A nonlinear model for the two oscillators is derived and verified numerically. Spice simulations using AMS BiCMOS 0.35µ model parameters and experimental results are shown. Copyright © 2009 John Wiley & Sons, Ltd.     

一种级数混合运算产生SPWM波新方法

提出了一种产生正弦脉宽调制波的新方法。介绍了采用级数混合运算产生数字化正弦波数据的基本原理,不需要专门的ROM存储器,利用传统查表法就能够得到所需要的SPWM信号。基于所提出的方法设计了一种通用型SPWM波形发生器,利用FPGA内部的RAM资源例化成所需要的虚拟ROM存储器,用来存储由级数混合运算得到的1/4周期数字化正弦波数据,然后利用中心对称和轴对称运算得到整周期的正弦波,与三角形载波进行比较后输出SPWM信号。实验结果表明,该SPWM发生器具有可靠性高,电路结构简单,使用灵活等特点。采用所提出的方法设计的SPWM光伏逆变器已投入应用,性能良好,工作稳定。     

A new hardware efficient coherent digital sweep oscillator with very low sweep rates and harmonic distortion

A new technique to efficiently increase the resolution of coherent digital sweep oscillators based on look-up-table (LUT) methods is proposed. The increase in resolution measured in terms of sweep rates is achieved while maintaining simple hardware implementation and very low levels of spurious harmonic distortion. The proposed technique increases the LUT length to a level at which the spurious harmonic distortion is negligible. The proposed technique is based on partitioning the address register into three sets and dividing the available LUT length into two smaller tables addressed according to the content of the address register sets. The proposed technique is simulated, and its performance is compared with that of the known sweep oscillators. The simulation results show that the proposed technique is superior to all previously reported sweep oscillators. Received: 9 October 2001/Accepted: 18 January 2002     

基于DSP的异步电机矢量控制系统研究

为提高异步电机控制性能,根据异步电机矢量控制原理,采用空间矢量脉宽调制技术,按照异步电机的定子产生跟踪圆形旋转磁场的方式控制逆变器开关动作,供给电机理想的正弦波电流,提高异步电机的稳、动态性能。结合电机控制专用高速数宇信号处理器TMS320LF2407A运算速度快、精度高、可以实时完成SVPWM控制算法的特点,建立了异步电机转子磁场定向下的矢量控制系统。实验结果表示,系统方案切实可行,工作性能良好。     

Design of a ZVS PWM DC–DC converter for high gain applications

In this paper, a pulse width modulation DC‐DC converter with high step‐up voltage gain is proposed. The proposed converter achieves high step‐up voltage gain with appropriate duty ratio, coupled inductor, and voltage multiplier technique. The energy stored in the leakage inductor of the coupled inductor can be recycled in the proposed converter. Moreover, because both main and auxiliary switches can be turned on with zero‐voltage switching, switching loss can be reduced by soft‐switching technique. So the overall conversion efficiency is improved significantly. The theoretical steady‐state analyses and the operating principles of the proposed converter are discussed in detail for both continuous conduction mode and discontinuous conduction mode. Finally, a laboratory prototype circuit of the proposed converter is implemented to verify the performance of the proposed converter. Copyright © 2015 John Wiley & Sons, Ltd.     

An efficient implementation of PRNGs based on the digital sawtooth map

In this paper, the sawtooth map digitally implemented is analysed to evaluate its suitability for pseudo‐random binary numbers generation. Period and statistical properties of the sequences generated by the digital map are evaluated versus arithmetic precision, approximation strategy and characteristic parameter of the map. In general, the digital implementation of the sawtooth map requires the use of a multiplier, which is quite expensive in terms of gate count. However, results show that values of design parameters that lead to adequate statistical features and to a relatively high period also allow for significantly reducing the complexity required in the implementation. To better evaluate performance of the digital sawtooth map as a pseudo‐random number generator, it is compared to a linear feedback shift register with the same number of flip‐flops, which is well known for its output sequences with a long period, appealing statistical quality, and for a reduced gate count. Performance comparison and implementation on a programmable logic device show that the digital sawtooth map is suitable for pseudo‐random number generation, also requiring a relatively small amount of hardware. Copyright © 2004 John Wiley & Sons, Ltd.     

New sinusoidal oscillator configurations using operational transresistance amplifier

The objective of this brief is to introduce four new structures of electronically tunable sinusoidal oscillators (SOs) designed using operational transresistance amplifier (OTRA). Each of the proposed SO consists of forward path derived from a generic structure along with one/two OTRA-based resistive gain stages or differentiator in its feedback path. All the proposed SOs enjoy independent tuning of the frequency of oscillation (FO) through resistors without affecting the condition of oscillation (CO). Further, all topologies are found to exhibit low f_o sensitivities at all frequencies with respect to circuit parameters, and the second topology is capable of achieving very low frequencies (VLFs) using less RC component spread and provides linear tuning too. The fourth circuit provides quadrature output. The proposed SOs have been successfully implemented and verified in 180-nm CMOS technology node using ADE (analog design environment) tool Cadence Virtuoso. Both prelayout and postlayout simulation results have been included. To assess the oscillator prefabrication performances, Monte Carlo and process-voltage-temperature (PVT) analyses have been performed. The total harmonic distortion (THD) is observed to be less than 3.5%.     

Piecewise-linear modeling of I-V characteristics with SPICE

This paper presents a technique for piecewise-linear modeling of arbitrary nonlinear I-V characteristics with SPICE. In particular, I-V characteristics (including those exhibiting negative resistance) that lend themselves to piecewise-linear approximation are easily modeled using six elemental building blocks; three for voltage-controlled I-V characteristics and three for current-controlled I-V characteristics. The elemental building blocks are implemented with resistor, diode, independent voltage source, and independent current source SPICE primitives. Two of the elemental building blocks use the ability of SPICE to accept negative values for the resistance and diode saturation current parameters. The technique is applied to model a unijunction transistor and a tunnel diode. Two negative resistance oscillator examples which use these models are included; a current-controlled negative resistance sinusoidal oscillator (unijunction transistor) and a voltage-controlled negative resistance relaxation oscillator (tunnel diode). These examples have been used to teach the fundamentals of negative resistance oscillators and nonlinear effects to sophomores and juniors     

Systolic digital filters with reduced latency—serial implementation

Schemes that implement finite impulse response (FIR) and infinite impulse response (IIR) digital filters when bit-serial or digit-serial arithmetic is used are proposed in this paper. The main objective is to obtain reduced latency (minimal latency at the word level) of the filter outputs while maintaining the word rate. Existing schemes (systolic or not) for filters are transferred down to the digit level and regular structures systolic at the bit or digit level are proposed. First a modified representation of a digital filter signal flow-graph appropriate for bit-serial or digit-serial arithmetic is presented. Next we show how the resulting flow-graph can be transformed to lead directly to a systolic implementation at the bit or word level. We aim towards minimizing the latency of the filter response. For this reason we work with bidirectional signal flow-graphs that lead to systolic arrays where data and partial results move in opposite directions, otherwise called two-way pipeline systolic arrays. The multipliers that are used in the implementation of the filters must have low latency themselves. For this reason they have the same two-way pipeline structure. In order to maintain the data word rate, the full-bit output of a multiplier must be rounded by a number of bits equal to the length of the data words. We propose a composite bit-serial multiplier that performs this rounding while preserving low latency and incorporate it in schemes for direct implementation of low-latency high-throughput systolic arrays for FIR and IIR digital filters. These schemes for bit-serial multipliers and filters are also extended to digit-serial arithmetic.     

Analysis and design of LC oscillators associated with frequency multipliers: a phase noise perspective

When a local oscillator signal generation system is based on an LC oscillator and a frequency multiplier, the question of determining the optimal multiplication factor is a key issue. In this paper, the problem is addressed in order to minimize the 1/f ² phase noise within a tuning range constraint. The analysis, with a practical graphical representation, reveals the oscillator phase noise dependence on the oscillating frequency in the transition from two different regimes, named the inductor‐limited quality factor and the capacitor‐limited quality factor. The results obtained enable the evaluation of the phase noise performance of systems based on a sub‐harmonic and super‐harmonic oscillators and how they compare with an oscillator in the fundamental mode. Crucial questions like the phase noise improvement that these systems can achieve are analytically answered. A design methodology is thus proposed and verified through measurements on a frequency source at 31 GHz, composed by a sub‐harmonic voltage‐controlled oscillator followed by an injection‐locked frequency tripler, dedicated to backhauling applications, designed on a BiCMOS process technology. The tuning range is 10%, and the phase noise at a 1‐MHz offset is −112 dBc/Hz. Copyright © 2017 John Wiley & Sons, Ltd.