A monolithic 200-V CMOS analog switch

A new high-voltage CMOS technology is described which can increase the operating voltage of these circuits to more than 200 V. This represents approximately an order of magnitude improvement over present-day commercially available CMOS devices. The technology is straightforward to implement and uses n-channel MOS transistors and high-voltage p-channel devices. As an example of the capability of the technology, a monolithic quad CMOS analog switch has been fabricated which can handle 200-V, 0.3-A analog signals, with a dynamic range in excess of 150 dB.     

A power IC technology with excellent cross-talk isolation

This paper reports a low-cost, excellent cross-talk isolation power integrated circuit (PIG) technology capable of integrating high-voltage LDMOS, high-voltage LIGBT, and low-voltage CMOS control circuit. The technology is implemented using a conventional twin-well CMOS process with no compromise on the CMOS devices, and the breakdown voltages of the LDMOS and LIGBT with drift length of 40 μm are over 400 V. Using this technology, operating current of the body diode of the LDMOS can be improved by over 16 times and operating current of the LIGBT can be improved by over five times before CMOS latch-up in the control circuit occurs     

A coplanar CMOS power switch

A 300 V power switch in a high-voltage CMOS technology compatible with a low-voltage MOS/bipolar technology is presented. This circuit can switch positive and negative 150 V pulses with rise and fall times of 100 ns for a 200 pF capacitive load. The switch has a low-voltage input control (/spl plusmn/15 V). Using earth-symmetrical non-overlapping high-voltage pulses as dynamic supply voltages, it is possible to reduce the power dissipation during the switching time considerably in comparison with the power dissipation of power switches, which use static (i.e., constant) supply voltages under the same conditions.     

High-voltage technology offers new solutions for interface integrated circuits

A BIMOS IC technology improving the design of interface circuits that require either high-voltage (up to 120 V) of current (up to a few amperes per output) has been developed. Both bipolar and MOS complementary components are processed together on the same chip for low- and high-voltage applications. Various BIMOS power interface circuits are now in production, e.g., a motor driver, a high-voltage plasma display driver, and a printer head driver. This paper describes the BIMOS technology and the characteristics of its components. As applications, two circuits are presented: the UEB 4732 (plasma display driver) with complementary MOS push-pull output stages (120 V), and the UAA 2081 (stepper motor driver) with power bipolar transistors (1 A per output). Both circuits have a logical part designed with low-voltage CMOS (5-12 V).     

基于0.5μm CMOS工艺的高压器件

近年来,驱动类、音响类、接口类电路产品系列是CMOS集成电路发展的一个重要方向,这些电路中特有的高低压兼容结构是其重要的特点.相应地高低压兼容CMOS工艺技术应用也越来越广泛.本文研究了与常规CMOS工艺兼容的高压器件的结构与特性,在结构设计和工艺上做了大量的分析和实验,利用n-well和n管场注作漂移区,在没有增加任何工艺步骤的情况下,成功地将高压nMOS,pMOS器件嵌入在商用3.3/5V 0.5μm n-well CMOS工艺中.测试结果表明,高压大电流的nMOS管BVdssn达到23～25V,P管击穿BVdssp>19V.     

High-voltage solutions in CMOS technology

This paper presents trends on CMOS high-voltage techniques for power integrated circuits (PICs). Several fully CMOS compatible drain engineering techniques will be presented. Experimental devices were fabricated in standard CMOS processes from three different lithography generations (2, 0.7 and 0.5 μm) without resorting to any extra processing steps. MOS devices layout specificity towards performance improvement, namely breakdown, parasitic effects and degradation, will be emphasized.A recently developed technique used to enlarge high-voltage devices safe-operating area and reduce leakage current will also be presented due to the very promising experimental results.Comparison with more sophisticated and expensive technologies still reveals CMOS as a highly accessible and versatile technology for future PICs.     

An analog/digital BCDMOS technology with dielectricisolation-devices and processes

A dielectrically isolated bipolar-CMOS-DMOS (BCDMOS) integrated-circuit technology that has been successfully developed for high-voltage applications (150-500 V) is reported. This technology integrates bipolar, CMOS, DMOS, p-n-p-n, JFET, and DGDMOS (dual-gate DMOS) devices on a single chip. The core BCDMOS process is chosen to be an optimized poly-gate n-channel DMOS process; additional levels and their relative sequences were chosen on the basis of their effects on the performance of the various kinds of devices in the chip and the trade-offs among those performances. The characteristics of the major devices in solid-state switches for telecommunication applications are demonstrated     

基于0.5 μm CMOS集成电路高低压兼容技术研究

将高压MOSFETs器件集成到低压CMOS数字和模拟电路中的应用越来越频繁。文章参考了Parpia提出结构,将高压NMOS、PMOS器件制作在商用3.3V/5V 0.5μmN-阱CMOS工艺中,没有增加任何工艺步骤,也没有较复杂BiCMOS工艺中用到的P-阱、P+、N+埋层,使用了PT注入。通过对设计结构的PCM测试,可以得到高压大电流的NMOS管BVdssn>23V～25V,P管击穿BVdssp>19V。同时,文章也提供了高压器件的设计思路和结果描述。     

High-voltage CMOS SIMOX technology and its application to a BSH-LSI

This paper describes high-voltage CMOS separation by implanted oxygen (SIMOX) technology and its application to a BSH-LSI that provides the basic functions of battery feed, supervision, and hybrid for subscriber line interface cuircuits. This technology is characterized by the existence of an electric-field-shielding (EFS) layer formed between the buried SiO2and the surface Si layer by oxygen implantation. The density of localized states at the Fermi level of the EFS layer has been estimated to be about 1 × 10¹⁹cm^-3. eV^-1using the Cohen-Fritzsche-Ovshinsky model. The EFS layer reduces substrate voltage dependence of the threshold voltage and increases the drain-to-source breakdown voltage for MOSFET's. Specifically, the drain-to-source breakdown voltage has been raised to 180 V. The BSH-LSI, which is composed of high-voltage CMOS of more than 60 V and low-voltage CMOS of 15 V, has been successfully fabricated containing resistors and capacitors. Compared with a conventional bipolar BSH-LSI, the chip size and the dissipation power of the LSI have been reduced to approximately one-third and one-half, respectively.     

Recent progress of submicron CMOS using 6H-SiC for smart powerapplications

Silicon carbide (SiC) CMOS circuits have been developed recently to provide monolithic control for SiC MOS power switching devices. Although SiC CMOS is not well suited for high-end microprocessor applications, it must provide the necessary response time performance required for safe operation in high-voltage power switching applications. Despite previous developments in SiC CMOS process technology; which have enabled digital circuit operation using a 5 V power supply, circuit switching speeds were in the microsecond range. An obvious way to improve circuit performance is to scale device lateral and vertical dimensions. This paper describes recent progress in the development of a submicron, single metal, p-well CMBS process technology using 6H-SiC. Conventional NMOS transistors are fabricated with 0.5-mm (drawn) channel lengths and exhibit acceptable short-channel effects. Conventional PMOS transistors exhibit punchthrough at 0.8-mm channel lengths and require considerable channel engineering efforts which are also presented. Several digital logic gates and a ring oscillator have been fabricated with nanosecond gate switching performance. Performance limiting factors like parasitic series resistance is also investigated     

A simplified low-voltage smart power technology

A novel self-isolated low-voltage smart power technology, based on a conventional polysilicon-gate VDMOS process, has been developed for applications where cost is a crucial factor. The low mask count (eight) and the optimization of the VDMOS power device are the main process characteristics. Besides, different devices (high-voltage PMOS, low-voltage CMOS, vertical and lateral n-p-n bipolar transistors, diodes, Zeners, and high-value isolated capacitors) are also fabricated, all MOS transistors being self-aligned to the gate     

Silicon-on-insulator power integrated circuits

A power integrated circuit process has been developed, based on silicon-on-insulator, which allows intelligent CMOS control circuitry to be placed alongside integrated high-voltage power devices. A breakdown voltage of 335 V has been obtained by using a silicon layer of 4 μm thickness together with a buried oxide layer of 3 μm thickness. The respective LDMOS specific on-resistance and LIGBT on-state voltage for this breakdown voltage were 148 mΩ cm² and 3.9 V, respectively.     

一种基于BCD工艺的高速低功耗电平位移电路

提出了一种基于0.25 μm BCD工艺、适用于高压降压型DC-DC转换器的新型电平位移电路.该电路使用了耐压60 V的高压DMOS器件(HVNMOS、HVPMOS)、耐压5V的低压CMOS器件(LVNMOS、LVPMOS),以及耐压5V的三极管器件(BJT).分析了降压型DC-DC转换器对电平位移电路的特殊要求;基于对两种常见电平位移电路的分析,提出了一种新型的电平位移电路.电路仿真结果显示,与之前的电路相比,新型电路结构具有响应快速、功耗低、输出电平精确、可靠性高等优点.     

Power integrated circuits—A brief overview

A brief overview of developments in power and high-voltage integrated circuits is presented. The technology can be classified into two types: 1) smart power devices that contain one or more common drain, vertical power transistors with control, and protective circuitry built on the same chip, and 2) high-voltage integrated circuits that combine lateral high-voltage with CMOS logic and analog bipolar circuits on the same chip. These technologies are being aimed at display drivers, telecommunications, motor drives, power supplies, and automotive electronics. A rapid growth in their application in the future can be expected.     

The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs

The holding voltage of the high-voltage devices in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristics will cause the LCD driver ICs to be susceptible to the latchup-like danger in the practical system applications, especially while these devices are used in the power-rail ESD clamp circuit. A new latchup-free design on the power-rail ESD clamp circuit with stacked-field-oxide structure is proposed and successfully verified in a 0.25-/spl mu/m 40-V CMOS process to achieve the desired ESD level. The total holding voltage of the stacked-field-oxide structure in snapback breakdown condition can be larger than the power supply voltage. Therefore, latchup or latchup-like issues can be avoided by stacked-field-oxide structures for the IC applications with power supply of 40 V.     

SOI power devices

This paper provides an introduction to silicon-on-insulator (SOI) technology and the operating principles of high-voltage SOI devices, reviews the performance of the available SOI switching devices in comparison with standard silicon devices, discusses the reasoning behind the use of SOI technology in power applications and covers the most advanced novel power SOI devices proposed to date. The impact of SOI technology on power integrated circuits (PICs) and the problems associated with the integration of high-voltage and low-voltage CMOS are also analysed     

TFSOI complementary BiCMOS technology for low power applications

A Thin-Film-Silicon-On-Insulator Complementary BiCMOS (TFSOI CBiCMOS) technology has been developed for low power applications. The technology is based on a manufacturable, near-fully-depleted 0.5 μm CMOS process with the lateral bipolar devices integrated as drop-in modules for CBiCMOS circuits. The near-fully-depleted CMOS device design minimizes sensitivity to silicon thickness variation while maintaining the benefits of SOI devices. The bipolar device structure emphasizes use of a silicided polysilicon base contact to reduce base resistance and minimize current crowding effects. A split-oxide spacer integration allows independent control of the bipolar base width and emitter contact spacing. Excellent low power performance is demonstrated through low current ECL and low voltage, low power CMOS circuits. A 70 ps ECL gate delay at a gate current of 20 μA is achieved. This represents a factor of 3 improvement over bulk trench-isolated double-polysilicon self-aligned bipolar circuits. Similarly, CMOS gate delay shows a factor of 2 improvement over bulk silicon at a power supply voltage of 3.3 V. Finally, a 460 μW 1 GHz prescaler circuit is demonstrated using this technology     

A monolithic low-power high-voltage driver for bistable LCDs

A complete low-power high-voltage driver for a 80×104 passive-matrix bistable LCD is integrated in a 0.7 μm CMOS smart-power technology. It features 100 V driving capability on all row and column outputs and comprises all necessary digitally programmable high-voltage generators and multiplexers to synthesize the required complex high-voltage waveforms from a 3 V battery. An original level-shifter design for the high-voltage multiplexers and a dedicated architecture for the programmable high-voltage generators yield an extremely low internal power consumption below 10 mW for the entire driver chip.     

一种极低功耗的CMOS带隙基准源

随着SoC在便携产品中应用的迅猛发展,低功耗技术变得越来越重要。本文采用了0.18um的标准CMOS工艺来,设计了一种无电阻、工作在亚阈值区的低功耗、小面积的CMOS电压基准源。这个带隙基准可以灵活运用于极低功耗的SoC系统中。这个电路的电源电流大约为150nA,可以在1.5V～3.3V之间的电源电压下工作,基准源的输出电压的线性度为44.4ppm/V。当电源电压为1.5V,室温下带隙基准电路的输出电压为1.1126V,100Hz频率下的电源抑制比为-66dB,当温度在-20℃与80℃之间变化时,输出电压的温度系数是55ppm/℃。整个带隙基准的芯片面积是0.011mm2。     

IGBT gate driver IC with full-bridge output stage using a modified standard CMOS process

This paper discusses the benefits of a full-bridge output stage on integrated IGBT gate drive circuits. This full-bridge topology allows obtaining positive and negative gate voltages using a single floating power supply. Short circuit protections have also been integrated, implementing an original soft shutdown process after an IGBT short circuit fault. The monolithic integration is based on an innovative high-voltage CMOS technology for power integrated circuits, using a standard low cost CMOS technology, requiring only one extra processing step. Lateral power N- and P-MOS transistors have been optimized using 2D simulators attending both specific on-resistance and breakdown voltage in order to optimize the full-bridge output stage. The IGBT driver has been experimentally tested, producing ±15 V gate-to-emitter voltage, and supplying the current peaks required by the 600 V IGBT switching processes. The driver characteristic response times are adapted to work at high switching frequency (>25 kHz) with high value of capacitive loads (3.7 nF).