Fabrication of thick, high-quality strained SiGe layer on ultra-thin silicon-on-insulator and modeling of film strain

Fabrication of a thick strained SiGe layer on bulk silicon is hampered by the lattice mismatch and difference in the thermal expansion coefficients between Si and SiGe, and a high Ge content leads to severe strain in the SiGe film. When the thickness of the SiGe film is above a critical value (90 nm for 18% Ge), drastic deterioration of the film properties as well as dislocations will result. In comparison, a silicon-on-insulator (SOI) substrate with a thin top Si layer can mitigate the problems and so a thick SiGe layer with high Ge concentration can conceivably be synthesized. In the work reported here, a 110 nm thick high-quality strained Si_0.82Ge_0.18 layer was fabricated on an ultra-thin SOI substrate with a 30 nm top silicon layer using ultra-high vacuum chemical vapor deposition (UHVCVD). The thickness of the SiGe layer is larger than the critical thickness on bulk Si. Cross-sectional transmission electron microscopy (XTEM) reveals that the SiGe layer is dislocation-free and the atoms at the SiGe/Si interface are well aligned, even though X-ray diffraction (XRD) data indicate that the SiGe film is highly strained. The strain factors determined from the XRD and Raman results agree well.     

Electron mobility behavior in extremely thin SOI MOSFET's

Extremely thin-film SOI MOSFET's with silicon film thickness down to 8 nm have been fabricated without inducing serious source/drain series resistance by employing a gate recessed structure. The influence of extremely thin silicon film on the electron mobility has been experimentally studied. The results show an abrupt mobility decrease in the device with less than 10 nm silicon film thickness. The measured mobility versus effective field below 10 nm silicon film thickness shows that a different scattering mechanism is involved in carrier conduction in 10 nm t_si region. The reasons for the mobility decrease have been examined from a device simulation and measurements     

Variation of the parameters and composition of thin films of porous silicon as a result of oxidation: Ellipsometric studies

The variation of the optical characteristics of thin films of oxidized porous silicon as a function of the preparation regime and subsequent heat treatment is investigated by ellipsometry. It is shown that the refractive index, optical thickness, and extinction coefficient of porous silicon films decrease monotonically, but the film thickness increases as the degree of oxidation of the silicon base layer increases. An analysis of the film thickness as a function of the degree of oxidation shows that it differs very little from the same dependence for the nonporous film. The composition of the films is determined from the measured refractive index at a wavelength λ=632.8 nm by means of curves calculated on the basis of the three-component Bruggeman model of the effective medium for layers with different initial porosities. Fiz. Tekh. Poluprovodn. 33, 1264–1270 (October 1999)     

薄膜厚埋层SOI材料的新制备技术

在结合低剂量注氧隔离(SIMOX)技术和键合技术的基础上,研究了制备薄膜(薄顶层硅膜)厚埋层SOI材料的新技术--注氧键合技术.采用该新技术成功制备出薄膜厚埋层SOI材料,顶层硅厚度130nm,埋氧层厚度lμm,顶层硅厚度均匀性±2%.并分别采用原子力显微镜(AFM)和剖面透射电镜(XTEM)对其表面形貌和结构进行了表征.研究结果表明,SIMOX材料顶层硅通过键合技术转移后仍能够保持其厚度均匀性,且埋氧层和顶层硅之间具有原子级陡峭的分界面,因此注氧键合技术将会是一项有广阔应用前景的SOI制备技术.     

钝化层对声表面波滤波器的影响

为了研究钝化层对声表面波(SAW)滤波器性能的影响,以二氧化硅(SiO2)薄膜为钝化层,对厚度为12～80 nm的SiO2膜钝化层工艺数据进行分析.结果表明,当SiO2膜钝化层覆膜厚度大于25 nm时其膜层质量均匀性好,致密度高.同时SiO2膜钝化层厚度对膜层间的粘性、传播损耗、自身的质量负载及谐振峰处的频率均有影响,...     

Thickness estimation of silicon-on-lnsulator by means of the fourier transform of bilinearly transformed infrared reflectance data

Knowledge of film thickness is essential for device design in silicon-on-insulator technology. A new thickness estimation technique, based on the calculation of the spatial frequencies of bilinearly transformed infrared reflectance data in a spectral window, is introduced. The assignment of dominant spectral peaks in the power spectral density curve to the optical thickness of the silicon, silicon dioxide and the combined layer, is also presented. Examples for silicon-on-silicon dioxide with the silicon layer ranging in thickness between 1000 nm and 50 nm, with fixed oxide thickness, are presented. Thickness values of both layers to better than a few percent accuracy, were obtained for silicon layers down to 100 nm and with reduced accuracy for layers as thin as 50 nm.     

Analysis of structural transformations and fluctuation effects in the nanosized nickel films in the vicinity of the melting point

The effect of heating temperature on the structure of the nickel films with an original thickness of 20 nm that are deposited on silicon-oxide substrate (the thickness of the thermally grown silicon oxide SiO₂ is about 1 ??m) is studied using the scanning probe microscopy. An increase in the temperature causes a decrease in the mean thickness of the Ni film from the original thickness h = 20 nm to 18 ± 2 nm at a temperature of 737 K and 15 ± 2 nm at a temperature of 752 K. The thickening of the film is interpreted with allowance for the heterogeneous melting. The voltage jumps across the film sample in the vicinity of the melting point under slow heating and constant current flow through the sample are interpreted. In particular, the primary fluctuations lead to a decrease in the nickel film thickness due to the formation of drops from the liquid layer on the film surface and, hence, significant positive fluctuations of the resistance (or voltage jumps across the sample). Irreversible variations in the properties of thin metal films upon heating below the melting point are interpreted.     

Effects of deposition temperature on the oxidation resistance andelectrical characteristics of silicon nitride

A study was made of the effects of deposition temperature on the oxidation resistance and electrical characteristics of silicon nitride. It was found that silicon nitride below a certain limit thickness has no oxidation resistance. This threshold falls as the deposition temperature is lowered. 3-nm-thick silicon nitride deposited at 600°C has sufficient oxidation resistance For wet oxidation at 850°C, while 5 nm film deposited at 750°C has no oxidation resistance. The electrical characteristics also improve as the deposition temperature is lowered. 6-nm-thick silicon nitride deposited at 600°C shows a TDDB lifetime that is about two orders longer than that of 6-nm-thick silicon nitride deposited at 700°C. It was also found that the silicon nitride transition layer which is deposited at the initial stage of deposition influences the oxidation resistance and electrical characteristics of thin silicon nitride. It was concluded that lowering the deposition temperature reduces the influence of the transition layer and improves the oxidation resistance and electrical characteristics of thin silicon nitride     

Threshold voltage dependence of LOCOS-isolated thin-film SOINMOSFET on buried oxide thickness

Effects of buried oxide thickness on short-channel effect of LOCOS-isolated thin-film SOI n-MOSFETs have been investigated. Devices fabricated on SOI substrate with thin (100 nm) buried oxide have smaller roll-off of threshold voltage than those fabricated on SOI substrate with thick (400 nm) buried oxide. This is caused by a different boron concentration at the silicon film that results from the difference of stress with the buried oxide thickness. In the case of thin buried oxide, higher volumetric expansion of the field oxide causes higher stress at the interface between the silicon film and the surrounding oxide, including field and buried oxide, which prevents boron atoms from diffusing beyond the interface     

Advanced technologies for optimized sub-quarter-micrometer SOI CMOSdevices

Two manufacturable technologies of fully-depleted (FD) thin-film silicon-on-insulator (SOI) MOSFET's for low-power applications are proposed in this paper. To maintain high current drive while aggressively thinning down the SOI film, silicide is to be formed on Ge-damaged silicon layers. Ge preamorphization facilitates silicide formation at low temperature (~450°C) and effectively controls the silicide depth without void formation. It also reduces the floating body effect. In addition, a reliable gate work-function engineering is introduced for good threshold voltage management. A p⁺SiGe/Si stack gate alleviates the threshold voltage instability of SOI due to film thickness nonuniformity and broadens the design window for channel doping. These advanced technologies, compatible with existing bulk CMOS technology, are integrated into SOI CMOS process. Excellent electrical device results are presented     

Enhancement in thermal stability of atomic layer deposited HfO2 films by using top Hf metal layer

A thin (∼ 0.5 nm) layer of Hf metal was deposited on an atomic layer deposited (ALD) HfO₂ film by the DC sputtering method. X-ray photoelectron spectroscopy and high-resolution transmission electron microscopy analyses showed that the Hf metal layer transformed into HfO₂ during the post-deposition annealing process. It appears that the HfO₂ layer formed by the oxidation of Hf metal provided the underlying ALD HfO₂ layer with the nucleation sites necessary to decrease the grain-boundary density of the crystallized HfO₂ film. The decrease in the grain-boundary density resulted in a reduction in the Hf-silicate formation and interfacial layer growth during post deposition annealing. This eventually resulted in a smaller increase in the capacitance equivalent thickness (CET) and high-k characteristics in the CET vs. leakage current density curve even after post deposition annealing at 1000 °C.     

Hot-carrier degradation behavior of thin-film SOI nMOSFET withisolation scheme and buried oxide thickness

Hot-carrier degradation behavior of thin-film SOI (silicon-on-insulator) nMOSFETs with various isolation techniques and buried oxide (BOX) thickness has been investigated focused on the stress behavior in the SOI structure. LOCOS (local oxidation of silicon) and STI (shallow trench isolation) processes are used as isolation techniques. Buried oxide thickness is 100 and 400 nm, respectively. From the isolation point of view, STI-processed SOI devices have better hot-carrier immunity than LOCOS-isolated SOI devices. In terms of BOX thickness, the thick BOX case has better hot-carrier degradation characteristics than the thin one. It is found that STI process and thick BOX cases induce smaller stress than LOCOS process and thin BOX cases, resulting in better hot-carrier immunity     

Elevated field insulator (ELFIN) process for device isolation of ultrathin SOI MOSFETs with top silicon film less than 20 nm

New device isolation process, called elevated field insulator (ELFIN) process, for ultrathin SOI devices with top silicon film less than 20 nm has been proposed and successfully demonstrated. In ELFIN process, gate oxidation and subsequent gate poly-Si deposition is followed by conventional STI process. ELFIN process has a field region elevated compared with active silicon region, leading to prevention of silicon edge from being wrapped around by gate poly-Si. It is found that thin-film SOI NMOSFETs with ELFIN process have better reverse narrow channel effect about 50% at W/sub G/=0.3 /spl mu/m than that with conventional shallow trench isolation (STI) process.     

A novel source/drain on void (SDOV) MOSFET implemented by local co-implantation of hydrogen and helium

In this paper a novel device named as SDOV MOSFET is proposed for the first time. This structure features localized void layers under the source and drain regions. The short channel effects of this device can be improved due to the SOI-like source/drain structure. In addition, without the dielectric layer under the channel region, this device can avoid some weaknesses of UTB SOI devices caused by the thin silicon film and the underlying buried oxide, such as mobility degradation, film thickness fluctuation and self-heating effect. Based on self-aligned hydrogen and helium co-implantation technology, the new device can be fabricated by a process compatible with the standard CMOS process. The SDOV MOSFETs with 50 nm gate length are experimentally demonstrated for verification.     

对异型硅岛实现的厚膜全耗尽SOIMOSFET的模拟研究

本文提出了用异型硅岛实现的厚膜全耗尽(FD)SOI MOSFET的新结构,并分析了其性能与结构参数的关系.通过在厚膜SOI MOSFET靠近背栅的界面形成一个相反掺杂的硅岛,从而使得厚膜SOI MOSFET变成全耗尽器件.二维模拟显示,通过对异型硅岛的宽度、厚度、掺杂浓度以及在沟道中位置的分析与设计,厚膜SOI MOSFET不仅实现了全耗尽,从而克服了其固有的Kink效应,而且驱动电流也大大增加,器件速度明显提高,同时短沟性能也得到改善.模拟结果证明:优化的异型硅岛应该位于硅膜的底部中央处,整个宽度约为沟道长度的五分之三,厚度大约等于硅膜厚度的一半,掺杂浓度只要高出硅膜的掺杂浓度即可.重要的是,异型硅岛的设计允许其厚度、宽度、掺杂浓度以及位置的较大波动.可以看出,异型硅岛实现的厚膜全耗尽 SOI MOSFET 为厚膜SOI器件提供了一个更广阔的设计空间.     

Defect transformation study in silicon-on-insulator structures by high-resolution X-Ray diffraction

Silicon-on-insulator (SOI) structures were fabricated by bonding using a new variant of Smart-Cut technology. As-bonded SOI structures are annealed at high temperature (1100°C) for removal of hydrogen, radiation defects and stresses at the bonding interface. The transformation of structural parameters in as-bonded and annealed SOI structures was investigated by high-resolution X-ray diffraction. The large strain observed for as-bonded SOI structures is relaxed during annealing at high temperature and final SOI wafer has strain-free top silicon layer due to defect annealing and viscous flow of SiO₂. FWHM value for SOI film is higher than that for typical silicon single crystal and is caused by mosaic-like structure only.     

A simple electrical method to determine the Si and oxidethicknesses in SOI materials

It is shown that the thickness of the silicon and oxide layers of a silicon-on-insulator (SOI) structure can be determined from high-frequency capacitance-voltage measurements. The test device consists of a Schottky diode in series with a Si-oxide-Si capacitor. The Si film and the substrate are n-type. The operation of this device is explained for n-type Si with the help of the energy-band diagrams. It is demonstrated that this simple test device can be implemented as a process monitor for silicon thickness control     

Crystallographic defects in thermally oxidized wafer bonded silicon on insulator (SOI) substrates

The crystalline quality of wafer bonded (WB) silicon on insulator (SOI) structures thermal treated in dry oxygen ambients has been investigated by means of transmission electron microscopy and defect etching. The main crystallographic defects present in the SOI layers are dislocations, amorphous precipitates, and oxidation induced stacking faults (OISF). The evolution of the OISFs with time and temperature has also been investigated. The main feature observed is that the OISF in WB SOI structures undergo a retrogrowth process at temperatures around T = 1195°C for times of t = 2h. This result is very similar to that recently reported for oxygen implanted SOI (SIMOX) but considerably different from that observed in bulk silicon. The experimental data fits nicely a model recently proposed for the retrogrowth of OISF in thin SOI layers. This model considers that the self-interstitial supersaturation is considerably reduced compared to bulk silicon due to the relative fast point defect recombination inside the top silicon layer.     

氧化对SOI基SiGe薄膜残余应变弛豫的影响

研究了氧化对外延在SOI衬底上的SiGe薄膜的残余应变弛豫过程的影响.通过对SiGe薄膜采用不同工艺的氧化,从而了解不同氧化条件对SOI基SiGe薄膜的应变弛豫过程的影响.氧化将会促使SiGe薄膜中的Ge原子扩散到SOI材料的顶层硅中.而SiGe薄膜的残余应变弛豫过程将会与Ge原子的扩散过程同时进行,通过对SiGe薄膜和SOI顶层硅中位错分布的分析发现:在氧化过程中,SiGe薄膜和SOI衬底之间存在一个应力传递的过程.     

Net negative charge in low-temperature SiO2 gate dielectric layers

SiO₂ gate dielectric layers (4–60 nm) were grown (0.6 nm/min) by plasma-enhanced chemical vapor deposition (PECVD) in strongly diluted silane plasmas at low substrate temperatures. In contrast to the well-accepted positive charge for thermally grown silicon dioxide, the net oxide charge was negative and a function of layer thickness. Our experiments suggested that the negative charge was created due to unavoidable oxidation of the silicon surface by plasma species, and the CVD component added a positive space charge to the deposited oxide. The net charge was negative under process conditions where plasma oxidation played a major role. Such conditions include low deposition rates and the growth of relatively thin layers.