Technology limitations for N+/P+ polycidegate CMOS due to lateral dopant diffusion in silicide/polysilicon layers

The device degradation of dual-polycide-gate N⁺/P⁺ CMOS polycide transistors due to the lateral diffusion of dopants in the silicides is studied using a coupled 2-D process and device simulator. Design rule spacings between the NMOS and the PMOS transistor are given for various NMOS:PMOS gate area ratios and thermal processing conditions. The simulations show that contrary to previous findings, micrometer and submicrometer spacings are possible for certain silicide technologies using low-temperature or short higher-temperature furnace steps. Simulations show that CoSi₂ and TiSi₂ appear to be better candidates for submicrometer dual-gate applications than WSi₂     

A multiple-terminal gate charging model

A gate charging model considering charging effect at all terminals of a MOSFET is reported in this letter. The model indicates two distinct charging mechanisms existing in P MOSFETs with a protecting device at their gates during plasma processing. The "normal-mode" charging mechanism exists when antenna size at the gate is higher than that at other terminals combined. In contrast, the "reverse-mode" charging mechanism exists in the case of antenna size at the gate lower than that at other terminals combined. The normal-mode mechanism will dominate the charging event when there is no protecting device at the transistor gate or the protecting device provides very low leakage current. On the other hand, the reverse-mode mechanism becomes dominant if the protecting device provides very high leakage current. The normal-mode charging mechanism is limited by the N-well junction leakage while in the reverse-mode mechanism, it is limited by the leakage of the protecting device. The model also suggests that larger N-well junction gives rise to higher charging damage in the normal-mode mechanism while it is opposite in the reverse-mode mechanism. These were confirmed by experimental data. The model points out that a zero charging damage can be achieved at certain combinations of the gate, source, drain and N-well antenna ratio. The knowledge of these transistor terminal antenna-ratio combinations will maximize the effective usage of the charging protection devices in circuit design. The reverse-mode charging mechanism suggests that the use of a high-leakage device at the transistor gate for charging protection may cause an opposite effect when the transistor terminal antenna ratios run into a condition that triggers this mechanism. This implies that PMOS transistors with gate intentionally pinned at ground or low potential in circuits may be prone to charging damage depending on the connectivity of their source, drain, and NW.     

Evidence of hole direct tunneling through ultrathin gate oxideusing P+ poly-SiGe gate

P⁺ poly-Si and poly-Si_0.75Ge_0.25-gated PMOS transistors with ultrathin gate oxides of 25 and 29 Å were used for this study. The difference in the gate work function was used to determine the mechanisms of gate tunneling current in such thin gate oxides, Under negative gate bias (inversion bias), it was found that the source/drain terminal serves as a source of holes for small V_g value, and as gate bias increases (more negative), it becomes a hole sink. These observations can be interpreted in terms of two competing mechanisms. For the first time, hole direct tunneling is reported, Hole direct tunneling is the dominant mechanism for -2 Vg<0 V. For Vg<-2 V, electron direct tunneling is dominant. Electron-hole pair generation by the tunneling electrons starts to dominate over hole direct tunneling only for V_g<-4 V     

Exploiting Gate Leakage in Deep-Submicrometer CMOS for Input Offset Adaptation

Gate leakage that occurs in deep-submicrometer CMOS might be a convenient new way of implementing highly resistive elements with minimal area consumption. We present an adaptive device that exploits gate leakage in the 90-nm STM CMOS process for offset cancellation at its input. This is achieved by a high-pass-filtering input stage with a very low cutoff due to a time constant of approximately 130 ms. In this filter, three 0.1times0.22 mum² gate-oxide structures are used to achieve the equivalent of a 6.5-GOmega resistance     

Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology

Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nanoscale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design concept and circuit implementations of ESD protection designs for mixed-voltage I/O interfaces with only low-voltage thin-oxide CMOS transistors. Especially, the ESD protection designs for mixed-voltage I/O interfaces with ESD bus and high-voltage-tolerant power-rail ESD clamp circuits are presented and discussed.     

Optimization of gate oxide N2O anneal for CMOSFET's atroom and cryogenic temperatures

This paper presents a study of the impact of gate-oxide N₂ O anneal on CMOSFET's characteristics, device reliability and inverter speed at 300 K and 85 K. Two oxide thicknesses (60 and 110 Å) and five N₂O anneal conditions (900~950°C, 5~40 min) plus nonnitrided process and channel lengths from 0.2 to 2 μm were studied to establish the correlation between the nitrogen concentration at Si/SiO₂ interface and the relative merits of the resultant devices. We concluded that one simple post-oxidation N₂O anneal step can increase CMOSFET's lifetime by 4~10 times, effectively suppress boron penetration from the P⁺ poly-Si gate of P-MOSFET's without sacrificing CMOS inverter speed. We also found that the benefits in terms of the improved interface hardness and charge trapping characteristic still exist at cryogenic temperature. All these improvements are found to be closely correlated to the nitrogen concentration incorporated at the Si/SiO₂ interface. The optimal N₂O anneal occurs somewhere at around 2% of nitrogen incorporation at Si/SiO₂ interface which can be realized by annealing 60~110 Å oxides at 950°C for 5 min or 900°C for 20 min     

Process limitation and device design tradeoffs of self-aligned TiSi2 junction formation in submicrometer CMOS devices

Submicrometer CMOS transistors require shallow junctions to minimize punchthrough and short-channel effects. Salicide technology is a very attractive metallization scheme to solve many CMOS scaling problems. However, to achieve a shallow junction with a salicide structure requires careful optimization for device design tradeoffs. Several proposed techniques to form shallow titanium silicide junctions are critically examined. Boron, BF₂, arsenic, and phosphorus dopants were used to study the process parameters for low-leakage TiSi ₂ p⁺/n and n⁺/p junctions in submicrometer CMOS applications. It is concluded that the dopant drive-out (DDO) from the TiSi₂ layer to form a shallow junction scheme is not an efficient method for titanium salicide structure; poor device performance and unacceptably leaky junctions are obtained by this scheme. The conventional post junction salicide (PJS) scheme can produce shallow n⁺/p and p⁺/n junctions with junction depths of 0.12 to 0.20 μm below the TiSi₂. Deep submicrometer CMOS devices with channel length of 0.40 to 0.45 μm can be fabricated with such junctions     

Analysis of thin gate oxide degradation during fabrication ofadvanced CMOS ULSI circuits

The electrical characteristics uniquely associated with the thin gate oxide degradation of the advanced CMOS technology in manufacturing were determined for the first time. They were different from Fowler-Nordheim (F-N) stress, and therefore, cannot be simulated by the F-N stress. The p⁺ thin gate oxides were found to be inherently more susceptible to gate oxide degradation than the n⁺ gate oxides. The p⁺ oxide degradation is caused by a combination of the process-induced defect and plasma charging. The nature of the defect and its formation were identified by electrical and physical analysis. The defect formation was modeled. The p-channel gate oxide degradation will be worse with gate oxide scaling, and may limit the device scaling     

Plasma-charging damage in ultra-thin gate oxide

The impact of plasma-charging damage on ultra-thin gate oxide is discussed. The argument for plasma-charging damage becoming less important is examined. Without considering the area and failure rate scaling effect, one mode of charging damage does become less important while other modes continue to be a serious problem. After scaling is properly accounted for, all charging damage remains a serious problem. The problem is more serious for thinner gate oxides because its life time becomes a limiting factor in device scaling. No one has yet made proper measurement for charging damage in the ultra-thin gate oxide regime. Stress-induced leakage current with properly designed tester may be used for ultra-thin gate-oxide damage measurement if one has the required sensitivity in the measurement. However, one must take care to use stress to reveal the latent defects that are hidden by annealing.     

SiGe-channel heterojunction p-MOSFET's

The advances in the growth of pseudomorphic silicon-germanium epitaxial layers combined with the strong need for high-speed complementary circuits have led to increased interest in silicon-based heterojunction field-effect transistors. Metal-oxide-semiconductor field-effect transistors (MOSFET's) with SiGe channels are guided by different design rules than state-of-the-art silicon MOSFET's. The selection of the transistor gate material, the optimization of the silicon-germanium channel profile, the method of threshold voltage adjustment, and the silicon-cap and gate-oxide thickness sensitivities are the critical design parameters for the p-channel SiGe MOSFET. Two-dimensional numerical modeling demonstrates that n⁺ polysilicon-gate SiGe p-MOSFET's have acceptable short-channel behavior at 0.20 μm channel lengths and are preferable to p⁺ polysilicon-gate p-MOSFET's for 2.5 V operation. Experimental results of n⁺-gate modulation-doped SiGe p-MOSFET's illustrate the importance of the optimization of the SiGe-channel profile. When a graded SiGe channel is used, hole mobilities as high as 220 cm² /V.s at 300 K and 980 cm²/V.s at 82 K are obtained     

Fully symmetric cooled CMOS on (110) plane

A cooled CMOS device using dual-polysilicon gates, (110) Si substrates, lightly doped drains with doping concentrations of 10¹⁴ cm^-2, and no channel implant is described. It is found that the peak mobility of a p⁺ polysilicon gate pMOS transistor on a (110) plane is 1.6 times larger than that on a (100) plane at 77 K. This pMOS transistor si very promising for use at 77 K because of its steeper subthreshold slope and higher hole mobility. The design has realized fully symmetrical cooled CMOS devices with 0.8-μm gates in which saturation currents and transductances of both n and pMOS transistors have been almost equalized. This fully symmetric cooled CMOS increases the ring oscillator speed by a factor of 1.2 and allows flexible CMOS circuit design that allows effective use of NOR gates     

An optimized bidirectional lightning surge protection semiconductordevice

This paper addresses the analysis of a bidirectional lightning surge protection power semiconductor device called the bidirectional breakover diode (BBD). The BBD has a high-speed response, high current capability, and low conduction and switching losses. The influence of the layout on the trigger and holding current values has been studied by means of two-dimensional (2-D) electrical simulations. The length of the peripheral N⁺ diffusion together with the location of the edge contact between the metallization and the P⁺/N⁺ diffusions are crucial in optimizing the trigger mechanism and the trigger and holding current values. The turn on of the inner cells has also been analyzed by numerical simulations, showing the effect of the central parasitic P⁺NP⁺ bipolar transistor at the initial phase of the turn on process. Experimental results have been obtained from fabricated 180-V BBD devices with holding current values in the range of 150-250 mA. The BBD surge protection capability has been corroborated by impulsive tests using a 10/1000 μs, 50 A, 1000 V, current pulse. In addition, transient losses have been monitored in order to improve the surge protection capability of the device. Finally, the static and dynamic BBD thermal behaviour has also been analyzed     

The origin of channel currents associated with P+regions in silicon

The mechanism by which very large channel currents can result in P⁺N junctions or in PNP transistors having annular P⁺diffused channel-stop regions was studied in detail using experimental structures whose oxides were intentionally contaminated with sodium ions. It is shown that the onset of channel current flow corresponds quantitatively to the formation of an inversion layer over the P⁺region. Possible mechanisms by which carriers can be supplied to the inversion layer, thereby resulting in a channel current, are considered. It is demonstrated that the mechanism involves the breakdown of the field-induced junction formed between the inversion layer and the underlying P⁺region. The breakdown characteristics of this field-induced junction are considered experimentally in detail. It is shown that breakdown can proceed through either a tunneling or an avalanche mechanism depending on the surface concentration of the P⁺region, and that the breakdown characteristics of field-induced junctions are much like those of narrow alloyed silicon junctions studied earlier by Chynoweth et al.     

Leakage Biased pMOS Sleep Switch Dynamic Circuits

In this brief, a low-overhead circuit technique is proposed to simultaneously reduce subthreshold and gate-oxide leakage currents in domino logic circuits. pMOS sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. A sleep transistor added to the dynamic node strongly turns off all of the high threshold voltage transistors. Similarly, a sleep switch added to the output inverter exploits the initially high subthreshold and gate-oxide leakage currents for placing a circuit into an ultimately low leakage state. The proposed circuit technique lowers the total leakage power by 56.1% to 97.6% as compared to standard dual threshold voltage domino logic circuits. Similarly, a 4.6% to 50.6% reduction in total leakage power is observed as compared to a previously published sleep switch scheme in a 45-nm CMOS technology     

On the SiO2-based gate-dielectric scaling limit forlow-standby power applications in the context of a 0.13 μm CMOS logictechnology

This paper describes a leading-edge 0.13 μm low-leakage CMOS logic technology. To achieve competitive off-state leakage current (I _off) and gate delay (T_d) performance at operating voltages (V_cc) of 1.5 V and 1.2 V, devices with 0.11 μm nominal gate length (L_g-nom) and various gate-oxide thicknesses (T_ox) were fabricated and studied. The results show that low power and memory applications are limited to oxides not thinner than 21.4 Å in order to keep acceptable off-state power consumption at V_cc=1.2 V. Specifically, two different device designs are introduced here. One design named LP (T_ox=26 Å) is targeted for V_cc=1.5 V with worst case I_off <10 pA/μm and nominal gate delay 24 ps/gate. Another design, named LP1 (T_ox=22 Å) is targeted for V_cc =1.2 V with worst case I_off<20 pA/μm and nominal gate delay 27 ps/gate. This work demonstrates n/pMOSFETs with excellent 520/210 and 390/160 μA/μm nominal drive currents at V_cc for LP and LP1, respectively. Process capability for low-power applications is demonstrated using a CMOS 6T-SRAM with 2.43 μm² cell size. In addition, intrinsic gate-oxide TDDB tests of LP1 (T _ox=22 Å) demonstrate that gate oxide reliability far exceeding 10 years is achieved for both n/pMOSFETs at T=125°C and V _cc=1.5 V     

Development of an integrated high speed silicon PIN photodiodesensor

A silicon integrated PIN photodiode sensor, combined with a bipolar IC on same substrate (that is, a PIN photo integrated circuit sensor: PIN-PICS), was developed by employing a high resistive P^-- epitaxial layer on a P⁺ substrate for creating a high speed and high optical responsivity PIN photodiode. We fabricated this device based on two special techniques: (1) the PIN photodiode is formed on a P^--/P⁺ substrate structure and isolated from bipolar components by the combination of a P^--well and a trench isolation, and (2) bipolar components are formed by the doubly diffused buried layer of the P^--well and the N⁺ collector wall. All of these components, such as npn and pnp transistors, were arranged within the lightly doped P^--well regions. From several kinds of trial samples, the following results were obtained. The PIN photodiode with 0.145 mm² active area indicated 680 MHz for cutoff frequency at 10 V bias with 830 mn radiation. In the case of 20 V bias, this value exceeded 1.5 GHz. This PIN-PICS was applied to a 10 Mbit/s burst mode compatible optical monolithic receiver and a transimpedance amplifier, and it has shown the expected results     

High-quality stacked CMOS inverter

A stacked CMOS technology with enhanced device performance and small geometries is discussed. Surface-channel mobilities were measured to be 700 cm²/V-s for bulk n-channel devices and 165 cm² /V-s for the top PMOS transistors. Excellent subthreshold slope of 100 mV/decade and leakage currents below 150-fA/μm channel width were measured for both device types. The low-impurity crystalline silicon film on top of the bulk devices was produced by local epitaxial overgrowth, an important alternative to recrystallized silicon films for three-dimensional CMOS circuits. The structure is planarized and requires only size masks with reduced processing time     

Disposable polysilicon LDD spacer technology

An advanced 0.5-μm CMOS disposable lightly doped drain (LDD) spacer technology has been developed. This 0.5-μm CMOS technology features surface-channel LDD NMOS and PMOS devices, n⁺/p⁺ poly gates, 125-A-thick gate oxide, and Ti-salicided source/drain/gate regions. Using only two masking steps, the NMOS and PMOS LDD spacers are defined separately to provide deep arsenic n⁺ regions for lower salicided junction leakage, while simultaneously providing shallow phosphorus n^- and boron p^- regions for improved device short-channel effects. Additionally, the process allows independent adjustment of the LDD and salicide spacers to optimize the LDD design while avoiding salicide bridging of source/drain to gate regions. The results indicate extrapolated DC hot-carrier lifetimes in excess of 10 years for a 0.3-μm electrical channel-length NMOS device operated at a power-supply voltage of 3.3 V     

Plasma-parameter dependence of thin-oxide damage from wafercharging during electron-cyclotron-resonance plasma processing

In this work, the effects of plasma-parameter variations on the charging damage of polysilicon-gate MOS capacitor test structures exposed to O₂ electron-cyclotron-resonance (ECR) plasmas are investigated. The results show that charging damage is generated when large potential differences exist across the gate-oxide layers of the MOS capacitor test structures and that these potential differences can only occur in the presence of plasma nonuniformities. These results demonstrate the critical need for plasma uniformity during processing, in particular as device dimensions shrink and gate-oxide thicknesses decrease. The plasma parameters were varied by adjusting the neutral gas pressure and by independently biasing a circular grid and a ring electrode located above the wafer. The damage induced in the test wafers during the plasma exposure was characterized with ramp-voltage breakdown measurements. Radial profiles of the floating potential measured with a Langmuir probe were found to vary nonuniformly when the grid electrode was positively biased due to preferential depletion of electrons relative to ions beneath the grid electrode. An equivalent-circuit model of the test wafer and the wafer-stage electrode predicts that the silicon substrate acquires a potential equal to the average of the wafer surface potential. Comparisons of the calculated profiles of the potential difference across the gate-oxide layers of the test structures and whole-wafer maps of the breakdown-voltage measurements show that the majority of the damage occurs where the oxide potential difference is largest and that the damage only occurs in the presence of plasma nonuniformities     

A variable-work-function polycrystalline-Si1-xGex gate material for submicrometer CMOS technologies

P⁺ poly-Si_1-xGe_x is a promising candidate for the gate material in submicrometer CMOS technologies due to its improved resistivity and its work function (which can be modified to achieve more-scalable NMOS and PMOS devices). The work function of P ⁺ poly-Si_1-xGe_x decreases with increasing Ge content, by more than 0.3 V from 0 to 60%. Because of its ease of formation and compatibility with VLSI fabrication techniques, assimilating poly-Si_1-xGe_x into an existing CMOS process should be relatively simple