InGaAsP–InP Avalanche Photodiodes for Single Photon Detection

In this paper, we describe the design, characterization, and modeling of InGaAsP/InP avalanche diodes designed for single photon detection at wavelengths of 1.55 and 1.06 mum. Through experimental and theoretical work, we investigate critical performance parameters of these single photon avalanche diodes (SPADs), including dark count rate (DCR), photon detection efficiency (PDE), and afterpulsing. The models developed for the simulation of device performance provide good agreement with experimental results for all parameters studied. For 1.55-mum SPADs, we report the relationship between DCR and PDE for gated mode operation under a variety of operating conditions. We also describe in detail the dependence of afterpulsing effects on numerous operating conditions, and in particular, we demonstrate and explain a universal functional form that describes the dependence of DCR on hold-off time at any temperature. For 1.06-mum SPADs, we present the experimentally determined relationship between DCR and detection efficiency for free-running operation, as well as simulations complementing the experimental data.     

NiSi Polysilicon Fuse Reliability in 65-nm Logic CMOS Technology

The programming characteristics and reliability of NiSi polysilicon fuse fabricated using 65-nm logic complimentary metal-oxide-semiconductor technology were studied. Under optimal programming conditions, high postprogram resistance can be achieved. These well-programmed fuses showed good data retention under unbiased temperature stress test. In order to avoid read disturb of unprogrammed fuses, the read current has to be kept below the threshold for silicide electromigration.     

Impact of MOSFET Gate-Oxide Reliability on CMOS Operational Amplifier in a 130-nm Low-Voltage Process

The effect of the MOSFET gate-oxide reliability on operational amplifier is investigated with the two-stage and folded-cascode structures in a 130-nm low-voltage CMOS process. The test operation conditions include unity-gain buffer (close-loop) and comparator (open-loop) configurations under the dc stress, ac stress with dc offset, and large-signal transition stress. After overstress, the small-signal parameters, such as small-signal gain, unity-gain frequency, and phase margin, are measured to verify the impact of gate-oxide reliability on circuit performances of the operational amplifier. The gate-oxide reliability in the operational amplifier can be improved by the stacked configuration under small-signal input and output application. The impact of soft and hard gate-oxide breakdowns on operational amplifiers with two-stage and folded-cascode structures has been analyzed and discussed. The hard breakdown has more serious impact on the operational amplifier.     

Ultra Storage-Efficient Time Digitizer for Pseudorandom Single Photon Counter Implemented on a Field-Programmable Gate Array

Pseudorandom single photon counting is a novel time-resolved optical measurement method, which is advantageous over convention techniques in terms of data-acquisition speed and system cost. As a critical component of the pseudorandom single photon counter, the photon arriving time digitizer should be storage efficient for a high photon counting rate, while maintaining good time accuracy. We report an ultra storage-efficient time digitizer for a pseudorandom single photon counter in this paper, which is based on the asynchronous serial communication and can store the arriving time of every photon in 1-b memory space. In addition, a novel comb-wave modulator is proposed to achieve the dc balance required for asynchronous serial communication. Our prototype implemented on field-programmable gate arrays provides a time resolution of 400 ps. It can register up to 4.2-Giga photon arriving time tags with 1024 $times$ 32-b memory space.      

Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology

Negative bias temperature instability (NBTI) and channel hot carrier (CHC) are the leading reliability concerns for nanoscale transistors. The de facto modeling method to analyze CHC is based on substrate current I_sub, which becomes increasingly problematic with technology scaling as various leakage components dominate I_sub. In this paper, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions for both NBTI and CHC effects. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65-nm technology. By benchmarking the prediction of circuit performance degradation with the measured ring oscillator data and simulations of an amplifier, we demonstrate that the proposed method very well predicts the degradation. For 65-nm technology, NBTI is the dominant reliability concern, and the impact of CHC on circuit performance is relatively small.     

A Retinal Prosthesis Technology Based on CMOS Microelectronics and Microwire Glass Electrodes

A very large format neural stimulator device, to be used in future retinal prosthesis experiments, has been designed, fabricated, and tested. The device was designed to be positioned against a human retina for short periods in an operating room environment. Demonstrating a very large format, parallel interface between a 2-D microelectronic stimulator array and neural tissue would be an important step in proving the feasibility of high resolution retinal prosthesis for the blind. The architecture of the test device combines several novel components, including microwire glass, a microelectronic multiplexer, and a microcable connector. The array format is 80 times 40 array pixels with approximately 20 microwire electrodes per pixel. The custom assembly techniques involve indium bump bonding, ribbon bonding, and encapsulation. The design, fabrication, and testing of the device has resolved several important issues regarding the feasibility of high-resolution retinal prosthesis, namely, that the combination of conventional CMOS electronics and microwire glass provides a viable approach for a high resolution retinal prosthesis device. Temperature change from power dissipation within the device and maximum electrical output current levels suggest that the device is acceptable for acute human tests     

Interface trap generation and hole trapping under NBTI and PBTI in advanced CMOS technology with a 2-nm gate oxide

This paper gives an insight into the degradation mechanisms during negative and positive bias temperature instabilities in advanced CMOS technology with a 2-nm gate oxide. We focus on generated interface traps and oxide traps to distinguish their dependencies and effects on usual transistor parameters. negative bias temperature instability (NBTI) and positive bias temperature instability in both NMOS and PMOS have been compared and a possible explanation for all configurations has been suggested. Recovery and temperature effect under NBTI were also investigated showing different behaviors of the two components.     

单片计算机系统抗干扰技术

介绍单片计算机应用系统常见的干扰作用机制和后果 ,并针对这些干扰在软件和硬件方面采用的措施以及CPU抗干扰技术。     

企业门户单点登录技术的研究

通过对系统的设计方式、数据结构及安全机制分析,设计和研究统一的系统管理平台,实现单点登录技术的跨层级应用。针对频繁、多种形式进行身份验证的系统安全问题,以数据应用集成管理的理论方法,在概念、理论、方法、设计思路及安全管理等方面进行综合研究,把多个相似环境中共同存在的多个子系统以虚链路方式集成为一个系统,以实现跨系统数据查询、分析和统计。基于系统管理平台,实现多系统业务应用及安全机制的联合与管理。     

AC-DC LED驱动电源消除电解电容技术综述

电解电容是影响AC-DC LED驱动电源寿命的主要元件,因此,消除电解电容技术成为LED驱动电源研究的关键点。近几年国内外学者从控制策略或者拓扑结构等方面相继提出了一些消除电解电容的方法。本文基于控制策略、优化拓扑结构两方面详述AC-DC LED驱动电源消除电解电容技术的研究现状,总结出AC-DC LED驱动电源消除电解电容方法的基本思想,并阐述了现有方法的技术原理和应用特点。最后,根据各种消除电解电容技术的综合性能给出了其应用意见及研究方向。     

Fabrication and Characterization of a Surface-Acoustic-Wave Biosensor in CMOS Technology for Cancer Biomarker Detection

Design, fabrication, and characterization of a novel surface acoustic wave (SAW) biosensor in complementary metal–oxide semiconductor (CMOS) technology are introduced. The biosensor employs a streptavidin/biotin-based five-layer immunoassay for detecting a prominent breast cancer biomarker, mammoglobin (hMAM). There is a growing demand to develop a sensitive and specific assay to detect biomarkers in serum that could be used in the early detection of breast cancer, determining prognosis and monitoring therapy. CMOS-SAW devices present a viable alternative to the existing biosensor technologies by providing higher sensitivity levels and better performance at low costs. Two architectures (circular and rectangular) were developed and respective tests were presented for performance comparison. The sensitivities of the devices were analyzed primarily based on center frequency shifts. A frequency sensitivity of 8.704 pg/Hz and a mass sensitivity of 2810.25 m$^{2} /$kg were obtained. Selectivity tests were carried out against bovine serum albumin. Experimental results indicate that it is possible to attach cancer biomarkers to functionalized CMOS-SAW sensor surfaces and selectively detect hMAM antigens with improved sensitivities, lowered costs, and increased repeatability of fabrication.      

实行两部制上网电价的探讨

介绍两部制电价的概念、两部制电价的结算举例和如何在上网电价中实行两部制电价。论证将发电的固定成本和可变成本以容量和电量的方式分开计算,可以进一步完善电价体系,从而调动发电、电网调度等各方面的积极性。     

基于二极管钳位五电平技术的LCL型感应电能传输系统谐波分析

感应电能传输(IPT)系统通常采用单相全桥逆变器作为交流电源,受功率半导体器件容量和成本限制,输出功率受限。为实现IPT系统的大功率输出,将二极管钳位五电平逆变技术应用到IPT系统中,并详细分析二极管钳位五电平逆变技术在IPT系统中的工作原理。利用逆变器输出电压的傅里叶级数表达式及电路拓扑,建立基于谐波与移相角、脉宽的关系表达式,得到五电平逆变器的最优工作点。与全桥逆变拓扑相比,所提控制策略能消除逆变器输出电压的3次、5次谐波,降低电压谐波总畸变率,同时增加IPT系统的输出功率。最后,构建一个五电平IPT的实验系统,实验结果验证了该方法的正确性与有效性。     

Active High Power Conversion Efficiency Rectifier With Built-In Dual-Mode Back Telemetry in Standard CMOS Technology

In this paper, we present an active rectifier with high power conversion efficiency (PCE) implemented in a 0.5-$mu{hbox {m}}$ 5 V standard CMOS technology with two modes of built-in back telemetry; short- and open-circuit. As a rectifier, it ensures a ${rm PCE}>80%$, taking advantage of active synchronous rectification technique in the frequency range of 0.125–1 MHz. The built-in complementary back telemetry feature can be utilized in implantable microelectronic devices (IMD), wireless sensors, and radio frequency identification (RFID) applications to reduce the silicon area, increase the data rate, and improve the reading range and robustness in load shift keying (LSK).      

单管并联技术在大功率电动汽车充电机中的应用

为满足电动汽车对充电机大电流输出、高功率密度及高性价比的要求,本文应用静态均流、动态均流对IGBT（Insulated Gate Bipolar Transistor）并联技术进行理论分析。结合移相全桥技术,设计了一款3只IGBT并联使用的大电流输出智能充电机。实验及实际应用情况表明,该设计运行可靠、各项指标满足要求,且成本较低,具有很强的市场竞争力。     

单回路直流系统绝缘电阻检测装置技术研究

现代生活日新月异,人们一刻也离不开电,必然会有用电安全问题。在电器设备中,存在着许多单回路电器系统,包括了配电设备、电动汽车系统、直流电机等,这些设备的绝缘电阻达到了兆欧级别。一般的检测方法包括了兆欧表测量,无源接地方法,辅助电源法,低频信号注入法以及电压注入法等,在电压注入法的基础上,提出一种变换分压电阻的方法,能够扩大绝缘电阻测量范围,并能较准确的测出绝缘电阻值。     

基于带电检测技术对一起35 kV单芯电缆护层接地缺陷的发现与分析

红外热像分析发现35 k V单芯电缆外护层温度异常,结合护层电流检测,确诊了电缆因护层接地错误而存在的缺陷。经过理论计算,确定了电缆护层应采取的正确接地方式,现场将电缆护层两端接地系统改为单端接地系统后,消除了缺陷。案例通过带电检测发现问题从而实现问题的有效解决,表明带电检测技术可以提高检修的针对性,实现设备的精准检修。     

变电站电能量采集终端单口双规约采集技术的应用

介绍了变电站电能量采集终端基本原理,以及DL/T 645-2007和DI/T 645-1997 2种通讯规约之间的异同,重点论述变电站电能量采集终端使用单一通讯通道实现2种不同通讯规约电能表数据采集的方法.这一方法的成功应用,极大地减少了现场工作量,解决了变电站电能表新旧规约过渡期间电能量采集面临的问题,实现了电能信息的全采集.     

一种单相并网逆变器电流相位的补偿方法

针对单相并网逆变器中,传统电流PI控制算法下的并网电流与电网电压存在相位差,尤其是在电流较小时相位差比较严重,导致逆变器输出功率因数较低的问题,提出了一种减小并网电流与电网电压相位差的控制方法.通过理论分析计算,得到不同的控制参数和电流给定情况下,并网电流与指令电流之间相位差的数学表达式,然后在指令电流中进行相应的相位...     

1 200 V/75 A IGBT与FRD芯片在功率模块中的性能优化

介绍绝缘栅双极型晶体管(insulated-gate bipolar transistors,IGBT)与快恢复二极管(fast recovery diode,FRD)匹配技术的特点和优势、应用前景及发展趋势。为更好地研究IGBT和FRD芯片在功率模块内的使用状况,结合国网智能电网研究院自主开发的1 200 V/75 A的IGBT和FRD芯片,得到相关的特性参数。将它们封装成功率模块,提出优化IGBT与FRD在功率模块中性能匹配优化的几种方法。