A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time

A portable clock generator, which solves the duty ratio and jitter problems of the input clock, has been developed. In the proposed clock generator, the complementary delay line generates a series of multiphase clocks. The 0-to-1 transition detector finds the 2 pi phase delayed position among the multiphase clocks produced by the complementary delay line, and then, the select signal generator chooses the proper path to generate the delayed output clock. As a result, the proposed open-loop and full-digital architecture achieves a fast lock time of two clock cycles. Also, it is a simple, robust and portable IP and consumes only 17 mW at an input clock frequency of 1.6 GHz. In addition, a complementary delay line is implemented to achieve high phase resolution over a wide frequency range. The proposed clock generator is implemented in a 0.18-mum CMOS process and, occupies an active area of 170 mum times 120 mum. Also, it operates at various input frequencies ranging from 800 MHz to 1.6 GHz.     

An All-Digital Fast-Locking Programmable DLL-Based Clock Generator

An all-digital fast-locking programmable DLL-based clock generator is presented. By resetting the output clock every two input clock periods, the initial minimal delay constraint in the conventional architecture is eliminated. Compared with the previous work, the short locking time is also achieved. The proposed circuit has been fabricated in 0.35-$mu$ m CMOS process and occupies the active area of 0.216 ${hbox {mm}}^{2}$. The clock multiplication ratio is programmed from 2 to 15. The frequency ranges of the input and output clocks are 4 $sim$ 200 MHz and 60 $sim$ 450 MHz, respectively. It dissipates less than 17 mW at all operating frequencies from a 3.3-V supply.      

A Fully Integrated Spread-Spectrum Clock Generator by Using Direct VCO Modulation

A compact architecture for a fully-integrated spread-spectrum clock generator (SSCG) using voltage-controlled oscillator direct modulation is presented in this paper. A dual-path loop filter in the phase-locked loop is employed to reduce the size of the capacitance in the filter with the aid of an extra charge pump and a unity gain amplifier. At the same time, a third-charge pump which generates triangular waves is used to perform the function of a spread-spectrum. The proposed circuit has been fabricated using a 0.35-$mu{hbox {m}}$ CMOS single-poly quadruple-metal process. The clock rate from 50 to 480 MHz with a center spread range of between 0.5% and 2% are verified and are close to the theoretical analyses. The size of the chip area is $0.82times 0.8 {hbox {mm}}^{2}$ (including the loop filter) and the power consumption was 27.5 mW at 400 MHz.      

一款用于扩频模式的时钟振荡器

针对扩频模式下开关频率在中心频率附近随机变化的要求,设计了一款时钟振荡器,可以通过模式选择信号选择工作在固定频率模式(FFM)或扩频模式(SSM)。基于0.6μmBCD工艺,Spectre仿真结果显示,选择固定频率模式时,产生频率为680kHz的方波;选择扩频模式时,通过对电路偏置信号的控制,使产生的方波频率在中心频率(680kHz)附近随机变化±5%。     

适用于HDTV的低抖动时钟电路

采用高速鉴频鉴相器、抗抖动电荷泵和差分对称负载延迟单元优化结构,综合分析环形振荡器各类噪声模型,设计了一种适用于HDTV的低抖动时钟电路。芯片采用SMIC 0.35μm标准CMOS工艺,3.3 V电源电压。在一定测试环境下,输出30 MHz时钟信号抖动σ仅为10.4 ps,能很好地满足电路设计要求。     

1．5GHz卫星无线电接收机

1 卫星无线电数字声音广播 系统概况 卫星无线电(Satellite Radio)是由美国全球宇空公司(World Space)开发的,利用定位在非洲、亚洲、美洲赤道上空的 3颗静止卫星,以 1.5GHz L波段覆盖全球的一种数字声音广播系统。它的突出特点是卫星电波照射区域广阔,又无C、K波段卫星接收天线的庞大设施,接收系统如同一般收音机似的简单,却能收听到数字的高音质声音广播,如今已受到国外广播界的关注。     

A Low-Jitter Spread Spectrum Clock Generator Using FDMP

A 1.5 GHz spread spectrum clock generator (SSCG) is realized by a fractional N frequency synthesizer with a third-order delta-sigma modulator and a fractional dual-modulus prescaler (FDMP). This FDMP utilizes a fractional division ratio to have a small phase step to improve the jitter performance. This SSCG has been fabricated in a 0.18 um CMOS process, and it consumes 34.2 mW from a supply of 1.8 V. The measured rms jitter is 5.55 ps and the measured electromagnetic interference reduction amount is 14.77 dB. The measured phase noise is $-97.18$ dBc/Hz at 1 MHz offset.      

1.2V低功耗时钟发生器设计

基于整数分频锁相环结构实现的时钟发生器,该时钟发生器采用低功耗、低抖动技术,在SMIC 65 nm CMOS工艺上实现。电路使用1.2 V单一电源电压,并在片上集成了环路滤波器。其中,振荡器为电流控制、全差分结构的五级环形振荡器。该信号发生器可以产生的时钟频率范围为12.5～800MHz,工作在800 MHz时所需的功耗为1.54 mW,输出时钟的周期抖动为:pk-pk=75 ps,rms=8.6 ps;Cycle-to-Cycle抖动为:pk-pk=132 ps,rms=14.1 ps。电路的面积为84μm2。     

一种基于注入锁定环形振荡器的时钟产生电路

提出了一种基于谐波注入锁定数控环形振荡器的时钟产生电路。采用注入锁定技术,极大地抑制了环形振荡器的相位噪声。在频率调谐环路关断的情况下,数控式振荡器可以正常工作,与需要一直工作的锁相环相比,大大节省了功耗。分析了电路的参考杂散性能。在65 nm CMOS工艺下进行流片测试,芯片的面积约为0.2 mm²。测试结果表明,设计的时钟产生电路工作在600 MHz时,1 MHz频偏处的相位噪声为-132 dBc/Hz,在1 V的电源电压下仅消耗了5 mA的电流。     

A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 μm CMOS Technology

A 2.5 GHz, 30 mW, 0.03 mm², all-digital delay-locked loop (ADDLL) in 0.13 mum CMOS technology is presented. The tri-state digital phase detector suppresses the dithering phenomenon and reduces the output peak-to-peak jitter for a counter-controlled digital DLL. The lattice delay unit has both a small delay step and a fixed intrinsic delay of two nand gates. A modified successive approximation register-controller reduces the locking time and allows the DLL to track the process, voltage, temperature, and load variations. This ADDLL locks in 24 cycles and has a closed-loop characteristic. The measured peak-to-peak jitter is 14 ps at 2.5 GHz.     

A $Delta{-}Sigma$ PLL-Based Spread-Spectrum Clock Generator With a Ditherless Fractional Topology

A triangular-modulated spread-spectrum clock generator using a$Delta{-}Sigma$-modulated fractional-$N$ phase-locked loop (PLL) is presented. The PLL employs a multiphase divider to implement the modulated fractional counter with increased $Delta{-}Sigma$ operation speed. In addition, the phase mismatching error in the phase-interpolated PLL with multiphase clocks can be randomized, and finer frequency resolution is achievable. With a frequency modulation of 33 kHz, the measured peak power reduction is more than 11.4 dB under a deviation of $pm$0.37%. Without spread-spectrum clocking, the PLL generates 2.4-GHz output with 18.82-ps peak-to-peak jitter. After spread-spectrum operation, the measured up-spread and down-spread jitter can achieve 52.59 and 56.79 ps, respectively. The chip occupies $950times850 {rm mu}{rm m}^{2}$ in 0.18-${rm mu}{rm m}$ CMOS process and consumes 36 mW.      

A 1.25–5 GHz Clock Generator With High-Bandwidth Supply-Rejection Using a Regulated-Replica Regulator in 45-nm CMOS

A clock generator for high-speed chip-to-chip link receivers was implemented in a 45-nm CMOS SOI technology. A low sensitivity to supply voltage noise was achieved by means of a low-dropout voltage regulator using a replica feedback in the regulation loop, where the replica resistance is regulated by a second loop. We show that by adjusting the replica load the necessary matching of the $gm/gds$ ratio of the current sources can be achieved. A power supply rejection of $>,$22 dB was measured up to 1 GHz for a circuit operating from a 1 V supply with 80$~$ pF decoupling capacitance and a load current of 18.5 mA. The maximum supply sensitivity of the clock generation circuit (DLL plus phase rotators) was 4.5 ps/100 mV supply noise over the entire noise frequency range at clock frequencies from 1.25–5 GHz. The phase rotator achieves a wide range of operating frequencies by providing programmable rise/fall times in its selection stage. In addition, low voltage operation of the circuit was demonstrated at supply voltages down to 0.7$~$V and a clock frequency of 1.6 GHz.      

时钟信号发生器及其应用

介绍时钟信号发生器(MAX3670)的性能、工作原理、内部结构、引脚功能及应用设计过程，并给出典型应用电路。     

A Low-Power Digital DLL-Based Clock Generator in Open-Loop Mode

This paper presents a low-power digital DLL-based clock generator. Once the DLL is locked, it operates in open-loop mode to reduce deterministic clock jitter and the power dissipation caused by DLL dithering. To keep track of any potential phase error introduced by environmental variations, a compensation mechanism is employed. In addition, a robust DLL-based frequency multiplication technique is proposed. The DLL-based clock generator is designed and fabricated in a 90 nm CMOS process in two different versions. Utilizing the proposed technique, the output jitter caused by DLL dithering is reduced significantly. Furthermore, the measured total power savings in the open-loop mode in comparison with the conventional closed-loop operation is about 14%.      

一种采用常跨导偏置技术的高速多相时钟发生器

介绍了一种基于电荷泵型锁相环的高速多相时钟发生器。采用常跨导偏置技术，使锁相环的频率响应对工艺、电源电压和温度的变化不敏感；在压控振荡器中采用镜像偏置，使该时钟发生器无需外部精确的偏置电压或电流。电路采用UMC 0．18m N阱CMOS工艺实现。仿真结果显示，在SSS、TTT和FFF三种条件下，环路带宽变化仅为12％，相位裕量只变化0.1。     

一种适用于相变存储器的低噪声时钟发生器

基于相变存储器的特性,设计了一种具有低功耗、低噪声的时钟发生器.该时钟由压控振荡器产生,并通过时钟控制电路转换为相变存储器存储操作所需的reset、set信号.由于纳米尺寸下的相变存储器件受噪声影响严重,该电路降低了外围驱动对相变存储单元的低频噪声干扰,能够改进相变存储器性能.电路采用40 nm CMOS工艺设计,电源电压为1.8V,功耗为1.26 mW,RMS抖动为0.83 ps,p-p抖动为5.14 ps,芯片面积为80 μm×90 μm.     

一种从E1信号中提取时钟的全数字锁相环

提出了一种从 E1信号中提取时钟的全数字锁相环。采用半脉宽移动技术设计数控振荡器 (DCO) ,使输出时钟占空比的误差小于 4%。经实验证实 ,在输入信号的频率范围为 2 .0 4 8MHz± 90 ppm且抖动满足 ITU- T G.82 3的情况下 ,该电路完全可以用于从 E1信号中提取时钟。采用数字锁相环对系统集成大有好处。     

一种用于流水线ADC的可调节多相时钟产生电路

设计了一种应用于10位80 MS/s流水线A/D转换器的可调节多相时钟产生电路.该电路采用一种电流镜结构,通过调节可变电阻的阻值来实现对单位延迟时间的精确控制.芯片采用IBM 0.13μm CMOS工艺实现,电源电压为2.5 V.在各种条件下仿真所得的最大延迟时间偏差为4%,时钟电路功耗为0.68 mW.仿真结果表明,该时钟产生电路适用于高速流水线A/D转换器.     

一种用于电子标签的低功耗高精度时钟电路设计

设计了一种适合射频电子标签的高精度时钟产生电路,在分析影响输出频率稳定性各因素的基础上,针对标签电路低功耗宽工作环境的要求,提出一种全CMOS结构带隙基准做偏置的电流受限型环形振荡器.全MOS自偏置PTAT迁移率和阈值电压互补偿带隙基准源的设计,使时钟电路受电源电压和温度的影响极小.全电路采用TSMC 0.18 μm CMOS工艺实现.HSpice仿真结果表明:电源电压为1.2～2 V,温度从-10～ 70 ℃变化时,带隙基准温度系数和电源电压抑制比分别为12 ppm/℃和59 dB,时钟稳定度在±2.5%以内,电路平均功耗仅为4 μw.