Digital compensation of DAC mismatches in multibit delta-sigma ADCs

A digital compensation technique to overcome the effects of the digital-to-analogue converter (DAC)'s mismatches in multibit delta- sigma modulators is described. The technique is purely digital, does not require the injection of a pilot signal and is compatible with binary-weighted element DACs. Simulation results confirm the validity of the compensation technique for a four-bit, fifth-order lowpass modulator with an oversampling ratio of 12 and 1% mismatch in the DAC elements. The compensated modulator exhibits a peak signal- to-noise-and-distortion ratio of 74.5 dB; that is within 0.5 dB of the ideal system without mismatch.     

A multibit delta-sigma audio DAC with 120-dB dynamic range

A 24-bit 192-kHz sample-rate digital-to-analog converter (DAC) achieves 120-dB A-weighted dynamic range in the 20-kHz band, and consumes 310 mW with a 5-V power supply. A third-order five-bit ΔΣ architecture optimized for high-end consumer audio has been developed and used. A switched-capacitor (SC) DAC combined with infinite-impulse response (IIR) and finite-impulse response (FIR) filters is employed to increase immunity to clock jitter, and reduce analog power. Partial-range dynamic element matching (DEM) enhances mismatch shaping with reduced circuit overhead. The 7.8-mm² chip fabricated in 0.5-μ m CMOS integrates a stereo DAC and all functions required for DVD-audio playback     

Tree structure for mismatch noise-shaping multibit DAC

A tree structure for the efficient implementation of segment selection in a multibit oversampled DAC is presented. The structure offers high-order noise-shaping of mismatch errors without the use of vector quantisation and so can be implemented in low silicon area     

A 3-V, 2%-mW multibit current-mode ΣΔ DAC with 100 dBdynamic range

The area ratio of analog to digital for mixed-mode chip has been inversely proportional to the process design rule for a given dynamic range objective, in contradiction to the LSI trend. This paper presents a design approach to realize a high degree of size reduction with process design rules for analog circuitry and a signal processing architecture for digital circuitry. A five-level current-mode ΣΔ digital-to-analog converter (DAC) system reveals full scale total harmonic: distortion plus noise (THD+N) of -90 dB and dynamic-range of 100 dB at 3 V (low power of 22 mW). Analog-area down-scaling can be accomplished by this architecture to be 1.09 mm², using 0.6-μm double-poly double-metal (DPDM) CMOS. For the digital filter, a pipeline instruction sequence with multiplierless architecture also gives small area of 1.98 mm²     

Ratiometric current-mode rational DAC

By exploring the principle of current division, a ratiometric current-steering rational implementation of a rational digital-to-analogue converter (DAC) is proposed. In this implementation, current scaling is achieved through ratios and, as a result, achieve greater independence from actual physical parameters and their associated non-idealities, resulting in the potential for achieving higher accuracy.     

Multiplexed noise shaping structures for delta-sigma modulators

A new structure for realising a multiplexed noise-shaping A/D convertor is proposed. It improves the performance of first- or second-order Delta Sigma modulators by employing additional feedback paths for suppressing the quantiser error. The structure, its theoretical analysis, and simulations confirming the improved resolution are presented.<>     

A 1-GHz, multibit, continuous-time, delta-sigma ADC for Gigabit Ethernet

In this work the design of a continuous-time ΔΣ modulator for Gigabit Ethernet applications is presented. The input bandwidth and oversampling ratio are, respectively, 62.5 MHz and 8, resulting in a clock frequency of 1 GHz. It was designed and implemented in a standard 90 nm CMOS technology. The active area of the modulator measures . It consists of a loop filter based on RC-opamp integrators and a 3-bit quantizer which includes a data weighted averaging scrambler. A digital tuning scheme to deal with process variations has also been included. System level simulations including several non-ideal effects have been carried out in order to determine in detail the performance of the converter. Experimental results show a resolution of 7.1 effective bits, and a power consumption of 10.8 mW from a nominal power supply of 1 V.     

Fourth-order two-stage delta-sigma modulator using both 1 bit and multibit quantisers

A fourth-order delta-sigma modulator is proposed as a cascade of two second-order stages. In the first stage, a 1 bit quantiser is employed, and in the second stage, a multibit quantiser is employed. The new modulator is tolerant of the multibit D/A conversion error and thus can deliver a very high signal-to-noise ratio in the baseband. Another significant advantage of using the new modulator is the reduced requirement on the following digital filter as associated with multibit modulators.<>     

Comparison of mismatch error shaping in multibit oversampledconverters

A number of mismatch error-shaping schemes for oversampled DACs are compared. Simulation results are presented to show that such a comparison should take account of the distribution of the mismatch errors, since the pattern of errors present affects different algorithms in different ways. A scheme for improving the error tolerance of one mismatch shaping architecture is presented     

一个具有平滑转换特性的电流型DAC单元电路

数模转换器（digital-analogue converter, DAC）在当前电子系统中发挥着重要作用,电流型DAC因其优良的特性而得到广泛应用。单元电路在开关瞬间的非理想转换特性对电流型DAC的性能有直接影响。文中对导致电流型DAC单元电路非理想转换特性的各类寄生效应进行了分析,并提出了一种结构简单的单元电路以改善非理想的输出特性。仿真结果显示其能有效抑制各类寄生效应,实现了输出的平滑转换。通过在一个抖频电路中的应用,该单元电路的可行性得以验证。     

A 100-dB gain-corrected delta-sigma audio DAC with headphone driver

An oversampled digital-to-analog converter (DAC) with a 100-dB A-weighted dynamic range is presented. It uses a switched-capacitor (SC) array to transfer the sampled charges directly into the headphone driver. The overall DAC gain is precisely controlled by a novel reference stage. A new dynamic element matching algorithm, based on split-set data-weighted averaging (SDWA), is used to improve the dynamic range and to reduce the nonlinearity caused by mismatches in the multibit DAC.     

A stereo multibit ΣΔ DAC with asynchronous master-clockinterface

A two-channel multibit ΣΔ audio digital-to-analog converter (DAC) with on-chip digital phase-locked loop and sample-rate converter is described. The circuit requires no over-sampled synchronous clocks to operate and rejects input sample clock jitter above 16 Hz at 6 dB/octave. A second-order modulator with a multibit quantizer, switched-capacitor (SC) DAC, and single-ended second-order SC filter provides a measured out-of-band noise of -63 dBr with less than 0.1° phase nonlinearity. Measured S/(THD+N) of the DAC channel including a 0-63 dB, 1 dB/step attenuator is greater than 90 dB unweighted. The circuit is implemented in 0.6-μm DPDM CMOS, dissipating 220 mW at 5 V. Die size is 3 mm×4 mm     

Switching Schemes for Reducing Capacitor Mismatch Sensitivity of Quasi-Passive Cyclic DAC

An alternately complementary switching is proposed to reduce the quasi-passive cyclic DAC error caused by capacitor mismatch, and a hybrid switching is adopted to further enhance its accuracy. With 1.1% moderate capacitor mismatch, the achievable effective number of bits is as high as 15. It is shown that a three-fold improvement in accuracy can be fulfilled by the proposed hybrid switching. Since the DAC owns better immunity to process variations, smaller capacitors can be utilized to diminish both chip cost and power consumption.      

A low-power 98-dB multibit audio DAC in a standard 3.3-V 0.35-μmCMOS technology

An oversampled digital-to-analog converter (DAC) is presented. The performance of this device has been achieved with a careful tradeoff with power consumption. A digital ΣΔ modulator has been optimized for the 96-dB target. In the switched-capacitor reconstruction filter (SCF), the input structure is embedded in the feedback loop in order to reduce the output noise. The order of the SCF is three, larger than in competitive solutions, allowing to achieve a lower out-of-band noise. Finally, the differential-to-single-ended converter does not strongly limit the overall DAC channel performance. The device has been realized in a standard 3.3-V CMOS technology. With a 28-mW-per-channel power consumption the dynamic range is 98 dB, while the SNDR peak is 86 dB     

Review and advances in delta-sigma DAC error estimation based on additive noise modelling

High-resolution and very high resolution data conversion is dominated by the use of delta-sigma modulating converters. Oversampling and noise-shaping is employed to enable a coarsely quantized conversion with high effective resolution. The time-domain output waveform from a delta-sigma modulator is often impossible to predict analytically, therefore modulator design is largely based on high level digital simulations and rule-of-thumb estimation. However, the output waveform also largely determines the distortion caused by analog error sources in the converter. Therefore optimization of the modulator with regards to digital quantization noise might not yield an optimal design when analog errors are included. This paper extends common estimation methods to include analog error sources, with the objective of enabling more global rule-of-thumb optimization.     

A 85-dB dynamic range multibit delta-sigma ADC for ADSL-CO applications in 0.18-/spl mu/m CMOS

A high-resolution multibit sigma-delta analog-to-digital converter (ADC) implemented in a 0.18-/spl mu/m CMOS technology is introduced. The circuit is targeted for an asymmetrical digital subscriber line (ADSL) central-office (CO) application . An area- and power-efficient realization of a second-order single-loop 3-bit modulator with an oversampling ratio of 96 is presented. The /spl Sigma//spl Delta/ modulator features an 85-dB dynamic range over a 300-kHz signal bandwidth. The measured power consumption of the ADC core is only 15 mW. An innovative biasing circuitry is introduced for the switched-capacitor integrators.     

Brownian-Bridge-Based Statistical Analysis of the DAC INL Caused by Current Mismatch

This brief analytically investigates the digital-analog converter (DAC) integrated nonlinearity (INL) with respect to the accuracy of the DAC unit elements. The main novelty of the presented approach is in the application of the Brownian Bridge (BB) process to precisely describe the INL. This method analyzes the thermometer and binary DAC architectures and is the first to prove that their statistical INL properties are different. The INL of the thermometer DAC is represented as a one-dimensional BB process. For the binary case, the INL is represented as combinations of random variables, the increments of which coincide with a BB process. For both architectures, this brief derives formulas for the INL main statistical properties, e.g., probability density function, mean, deviation, and chip yield. These properties are compared with previous analytical attempts and conclusions are drawn. The results of this brief fill a gap in the general understanding of the most quoted DAC specification- the INL. In particular, for a high-volume chip production, the derived formulas will help engineers to choose the DAC architecture and the allowed mismatch of the DAC unit elements     

Self-calibration techniques for a second-order multibit sigma-deltamodulator

Design techniques for self-calibration of the digital-to-analog converter DAC in a multibit sigma-delta modulator are described. When used in conjunction with dynamic element matching, self-calibration provides linearity performance suitable for digital audio applications. The dynamic element matching circuitry provides the mechanism of determining device mismatch for self-calibration. Practical circuit details and an effective calibration method are discussed. Test results from a l-μm CMOS test chip are presented. In this test system, a second-order loop with a 3-b quantizer achieves an 89-dB dynamic range and -91-dB harmonic distortion after calibration. In addition, a new method of detecting the presence of tones is described, using the entropy of the spectrum of the decimation filter output     

A low oversampling ratio 14-b 500-kHz ΔΣ ADC with aself-calibrated multibit DAC

Delta-sigma (ΔΣ) analog-to-digital converters (ADC's) rely on oversampling to achieve high-resolution. By applying multibit quantization to overcome stability limitations, a circuit topology with greatly reduced oversampling requirements is developed. A 14-bit 500-kHz ΔΣ ADC is described that uses an oversampling ratio of only 16. A fourth-order embedded modulator, four-bit quantizer, and self-calibrated digital-to-analog converter (DAC) are used to achieve this performance. Although the high-order embedded architecture was previously thought to be unstable, it is shown that with proper design, a robust system can be obtained. Circuit design and implementation in a 1.2-μm CMOS process are presented. Experimental results give a dynamic range of 84 dB with a sampling rate of 8 MHz and oversampling ratio of 16. This is the lowest oversampling ratio for this resolution and bandwidth achieved to date     

A 14-bit current-mode ΣΔ DAC based upon rotated dataweighted averaging

A new dynamic element matching (DEM) algorithm, referred to as rotated data weighted averaging (RDWA), is implemented in a third-order ΣΔ digital-to-analog converter (DAC) with 64× oversampling and a conversion bandwidth of 25 kHz. The systematic and random errors are considered in the design of the 14-bit converter. The ΣΔ DAC is fabricated in a 2-μm CMOS process and includes the on-chip reconstruction filter. The prototype was designed to test the performance of the DAC without DEM, with data weighted averaging (DWA), and with RDWA. The results show that the new RDWA algorithm is capable of achieving first-order noise shaping while eliminating the signal-dependent harmonic distortion present in DWA