Multistage amplifier topologies with nested Gm-Ccompensation

This paper presents a multistage amplifier for low-voltage applications (<2 V). The amplifier consists of simple (noncascode) low gain stages and is stabilized using a nested transconductance-capacitance compensation (NGCC) scheme. The resulting topology is similar to the well known nested Miller compensation (NMC) multistage amplifier, except that the proposed topology contains extra G _m feedforward stages which are used to enhance the amplifier performance. The NGCC simplifies the transfer function of the proposed multistage amplifier which, in turn, simplifies its stability conditions. A comparison between the NGCC and NMC shows that the NGCC has wider bandwidth and is easier to stabilize. A four-stage NGCC amplifier has been fabricated using a 2-μm CMOS process and is tested using a ±1.0 V power supply. A dc gain of 100 dB has been measured. A gain bandwidth product of 1 MHz with 58° of phase margin and power of 1.4 mW can be achieved. The op amp occupies an active area of 0.22 mm². Step response shows that the op amp is stable     

A 64K/spl times/1 bit dynamic ED-MOS RAM

A 64K/spl times/1 bit dynamic RAM based on an innovative short channel ED-MOS process technology and an improved ED-MOS sense amplifier circuit has been realized. The RAM has been designed by using 2-3 /spl mu/m design rules and employing ED-MOS peripheral circuits capable of low supply voltage operation. As a result, dynamic memory operation has been demonstrated with an access time less than 140 ns and a cycle time of 350 ns, using a single 5 V power supply.     

0.9 V rail-to-rail constant gm CMOS amplifier input stage

Presented is a 0.9 V rail-to-rail constant g_m CMOS amplifier input stage consisting of complementary differential pairs and a g_m control circuit. The g_m control circuit eliminates the g_m dead zone, which occurs in the conventional rail-to-rail amplifier with ultra-low supply voltages. The proposed amplifier input stage has a constant g_m that varies by ±2.3% for rail-to-rail input common-mode levels. To verify the proposed amplifier design, an experimental prototype operational amplifier is also implemented using 0.35 mm standard CMOS technology.     

A cyclic A/D converter that does not require ratio-matchedcomponents

The circuit configuration of a cyclic analog-to-digital (A/D) converter using switched-capacitor techniques is described. The analog portion of the circuit consists of two operational amplifiers, four capacitors, and ten switches regardless of the number of bits per sample converted, and completes an n-bit conversion in 3n clock cycles. The conversion characteristics are inherently insensitive both to capacitor ratio and to amplifier offset voltage. The circuit, therefore, can be realized in a small die area. The effects of finite amplifier gain and switch charge injection on the conversion accuracy are discussed. A prototype chip has been fabricated in a 2-μm CMOS technology operating on a single 5-V supply. When it is operated as an 8-bit converter at a sampling rate of 8 kHz, the maximum conversion error is 0.2 LSB (least-significant bit) for differential nonlinearity and 0.5 LSB for integral nonlinearity. The die area measures 0.79 mm²     

1.25 Gb/s低功耗CMOS光接收机限幅放大器

设计并实现了用于光纤用户网和千兆以太网光接收机的限幅放大器。电路采用有源电感负载来拓展带宽、稳定直流工作点 ,通过直接耦合技术来提高增益、降低功耗。测试结果表明 ,在从 5 m Vp- p到 5 0 0 m Vp- p,即40 d B的输入动态范围内 ,在 5 0 Ω负载上的单端输出电压摆幅稳定在 2 80 m Vp- p。在 5 V电源电压下 ,功耗仅为1 30 m W。电路可稳定工作在 1 5 5 Mb/s、62 2 Mb/s、1 .2 5 Gb/s三个速率上。     

20 mW 1.25 Gbit/s CMOS transimpedance amplifier with 30 dB dynamic range

A 1.25 Gbit/s transimpedance amplifier using a novel photodiode capacitance cancellation technique has been demonstrated in 0.35 mum CMOS technology. The transimpedance amplifier achieved a transimpedance gain of 17.1 kOmega as well as a wide dynamic range from +1 to -29 dBm while consuming only 20 mW from a 3 V supply     

A 5-10 GHz octave-band AlGaAs/GaAs HBT-Schottky diodedown-converter MMIC

The authors describe an AlGaAs/GaAs heterojunction bipolar transistor (HBT) X-band down-converter monolithic microwave integrated circuit (MMIC) which integrates a double double-balanced Schottky mixer and five stages of HBT amplification to achieve greater than 30 dB conversion gain over an RF bandwidth from 5 to 10 GHz. In addition, an output IP3 as high as +15 dBm has been achieved. The Schottky diodes are constructed from the existing N^$collector and N⁺ subcollector layers of the HBT molecular beam epitaxy (MBE) device structure. A novel HBT amplifier topology employing active feedback which provides wide bandwidth in a compact area is used for the RF, LO, and IF amplifier stages. The complete down-converter MMIC is realized in a 3.6×3.4 mm² area, is self-biased through a 6 V supply, and consumes 530 mW. This MMIC represents the highest complexity X-band down-converter MMIC demonstrated using GaAs HBT-Schottky diode technology     

A 10-b 50 MS/s 500-mW A/D converter using a differential-voltagesubconverter

A BiCMOS A/D converter using a “differential voltage subconverter,” which directly converts a voltage difference of complementary analog inputs to a digital code, is described. Fully differential architecture has advantages in immunity of common-mode error and in reduction of supply voltage. This differential-voltage subconverter realizes the fully differential A/D conversion without using interpolation technique. This subconverter is free from CR delay caused in the ladder resistors. Circuit techniques for high-accuracy conversion with single 5-V power supply, such as compensation technique for VBE modulation in emitter degeneration amplifier, are also described. A 10-b A/D converter is fabricated in a 0.8-μm BiCMOS process with f_T of 9 GHz. It successfully operates at 50 MS/s with 500-mW power consumption and with 5-V single supply     

Design and analysis of a high efficiency linear power amplifier

A high efficiency linear power amplifier is introduced based on the idea of Switch-Linear Hybrid (SLH) power conversion. The SLH power amplifier developed from the conventional class B power amplifier, while the class B configuration power unit in the SLH power amplifier is fed by a dynamic switching power supply, not the usual constant DC power supply. Thus, the efficiency of the class B configuration power unit in SLH power amplifier can be greatly improved. By combining linear power amplifier with switching power supply, the SLH power amplifier has synthetic performance of high fidelity, high efficiency and excellent dynamic characteristics. In this article, analysis of SLH power amplifier is performed, especially focusing on its linear power unit which is the core of SLH power amplifier. Design considerations are also presented parallel with the analysis. Both the theoretical analysis and experimental results verify the validity of SLH power amplifier.     

A low-voltage micropower JFET/bipolar operational amplifier

A single cell supply (operable down to 1.2 V) micropower operational amplifier using compatible low pinchoff voltage JFET's (V/SUB p/=0.4 V) in conjunction with standard bipolar technology has been developed. The subvolt pinchoff JFET's have proved useful in the common-mode feedback-assisted biasing of a simple p-n-p input stage to permit single supply operation, the design of a low-voltage high-performance current mirror and a differential to single-ended converter. The amplifier exhibits excellent ac performance (unity gain slew rate=0.25 V//spl mu/s, unity gain bandwidth=850 kHz) with low power dissipation (245 /spl mu/W).     

6-k/spl Omega/ 43-Gb/s differential transimpedance-limiting amplifier with auto-zero feedback and high dynamic range

A high-gain, 43-Gb/s InP HBT transimpedance-limiting amplifier (TIALA) with 100-/spl mu/A/sub pp/ sensitivity and 6 mA/sub pp/ input overload current is presented. The circuit also operates as a limiting amplifier with 40-dB differential gain, better than 15-dB input return loss, and a record-breaking sensitivity of 8 mV/sub pp/ at 43 Gb/s. It features a differential TIA stage with inductive noise suppression in the feedback network and consumes less than 450mW from a single 3.3-V supply. The TIALA has 6-k/spl Omega/ (76dB/spl Omega/) differential transimpedance gain and 35-GHz bandwidth and comprises the transimpedance and limiting gain functions, an auto-zero dc feedback circuit, signal level monitor, and slicing level adjust functions. Other important features include 45-dB isolation and 800-mV/sub pp/ differential output.     

5 V, DC-12 GHz InP/InGaAs HBT amplifier

An InP/InGaAs HBT cascode amplifier operating from a single 5 V power supply is described. The circuit has a DC gain of 17.2 dB and a -3 dB frequency point of 12.3 GHz. This results in a gain-bandwidth product in excess of 90 GHz. The frequency response of the amplifier remains constant if the power supply voltage is as low as 4 V.<>     

A 5 Gb/s CMOS adaptive equalizer for serial link

A 5 Gb/s adaptive equalizer with a new adaptation scheme is presented here by using 0.13μm CMOS process.The circuit consists of the combination of equalizer amplifier,limiter amplifier and adaptation loop.The adaptive algorithm exploits both the low frequency gain loop and the equalizer loop to minimize the inter-symbol interference (ISI) for a variety of cable characteristics.In addition,an offset cancellation loop is used to alleviate the offset influence of the signal path.The adaptive equalizer core occupies an area of 0.3567 mm2 and consumes a power consumption of 81.7 mW with 1.8 V power supply.Experiment results demonstrate that the equalizer could compensate for a designed cable loss with 0.23 UI peak-to-peak jitter.     

Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-/spl mu/m digital CMOS technology

This paper presents the design of an optical receiver analog front-end circuit capable of operating at 2.5 Gbit/s. Fabricated in a low-cost 0.35-/spl mu/m digital CMOS process, this integrated circuit integrates both transimpedance amplifier and post limiting amplifier on a single chip. In order to facilitate high-speed operations in a low-cost CMOS technology, the receiver front-end has been designed utilizing several enhanced bandwidth techniques, including inductive peaking and current injection. Moreover, a power optimization methodology for a multistage wide band amplifier has been proposed. The measured input-referred noise of the optical receiver is about 0.8 /spl mu/A/sub rms/. The input sensitivity of the receiver front-end is 16 /spl mu/A for 2.5-Gbps operation with bit-error rate less than 10/sup -12/, and the output swing is about 250 mV (single-ended). The front-end circuit drains a total current of 33 mA from a 3-V supply. Chip size is 1650 /spl mu/m/spl times/1500 /spl mu/m.     

Indirect current feedback instrumentation amplifier with acommon-mode input range that includes the negative roll

An instrumentation amplifier which can handle common-mode voltages that extend 200 mV below the negative supply is presented. The extended range is combined with a common-mode rejection of 92 dB and an accuracy of 0.1%, without the need for on-chip trimming. This has been achieved by the use of two p-n-p V-to-f converters in an indirect current feedback configuration. The output voltage can reach the negative supply. The offset voltage is 0.3 mV, and the noise voltage is 30 nV/√Hz. The circuit operates at supply voltages down to 2.5 V, and the quiescent current is 240 μA. The instrumentation amplifier has been integrated in a semicustom bipolar process     

High-gain SiGe transimpedance amplifier array for a 12/spl times/10 Gb/s parallel optical-fiber link

A transimpedance amplifier array for 12 parallel optical-fiber channels each operating at 10 Gb/s is presented, which is used in the receiver of short-distance links. It stands out for the following features: high gain (transimpedance 25 k/spl Omega/ in the limiting mode), high input sensitivity and wide input dynamic range (input current swing from 20 to 240 /spl mu/A/sub p-p/), constant output voltage swing (differential 0.5 V/sub p-p/ at 50 /spl Omega/ load), and low power consumption (1.4 W) at a single supply voltage (5 V). Each channel has its own offset-current control circuit. To the best of the authors' knowledge, the total throughput of 12/spl times/10 Gb/s=120 Gb/s is the highest value reported for a single-chip amplifier array. The target specifications have been achieved with the first technological run without needing any redesign. This fact demonstrates that the inherent severe crosstalk problems of such high-gain amplifier arrays can reliably be solved by applying adequate decoupling measures and simulation tools.     

A 10 bit 20 MS/s 3 V supply CMOS A/D converter

A 10 bit CMOS A/D converter with 3 V power supply has been developed for being integrated into system VLSI's. In this A/D converter, redundant binary encoders named “twin encoders” enhance tolerance to substrate noise, together with employing differential amplifiers in comparators. The bias circuit using a replica of the amplifier is developed for biasing differential comparators with 3 V power supply. Subranging architecture along with a multilevel tree decoding structure improves dynamic performance of the ADC at 3 V power supply. The A/D converter is fabricated in double-polysilicon, double-metal, 0.8 μm CMOS technology. The experimental results show that the ADC operates at 20 MS/s and the twin encoders suppress the influence of substrate noise effectively. This ADC has a single power supply of 3 V, and dissipates 135 mW at 20 MS/s operation     

Large-swing CMOS buffer amplifier

A circuit configuration for a CMOS buffer amplifier is described. The circuit, which is an enhancement of a previously reported buffer amplifier, features a large output voltage swing and a well-controlled quiescent current. A buffer amplifier of this type has been implemented in a 1.5-μm CMOS technology. The prototype occupies an area of 275 mil². It works with a 5-V supply and can drive more than 4.2 V (peak to peak) in to 300 Ω with a total harmonic distortion of less than 0.025%     

A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration

A 512-Mb DDR-II SDRAM has achieved 700-Mb/s/pin operation at 1.8-V supply voltage with 0.12-/spl mu/m DRAM process. The low supply voltage presents challenges in high data rate and signal integrity. Circuit techniques such as hierarchical I/O lines, local sense amplifier, and fully shielded data lines without area penalty have provided improved data access time and, thus, high data rate can be achieved. Off-chip driver with calibrated strength and on-die termination are utilized to give sufficient signal integrity for over 533-Mb/s/pin operation.     

Transconductance with capacitances feedback compensation for multistage amplifiers

A new performance-boosting frequency compensation technique is presented, named Transconductance with Capacitances Feedback Compensation (TCFC). A transconductance stage and two capacitors introduce negative feedback to a three-stage amplifier, which significantly improves the performance such as gain-bandwidth product, slew rate, stability and sensitivity. An optimized TCFC amplifier has been implemented, and fabricated in a 0.35-/spl mu/m CMOS process. The TCFC amplifier driving a 150-pF load capacitor achieved 2.9-MHz gain-bandwidth product dissipating only 45-/spl mu/W power with a 1.5 V supply, which shows a significant improvement in MHz/spl middot/pF/mA performance.