A new multitime programmable non-volatile memory cell using high voltage NMOS

A new multitime programmable (MTP) non-volatile memory (NVM) cell using high voltage NMOS is proposed. A PMOS transistor is used for programming, erasing, and reading, and a high voltage NMOS is used for selecting the memory cell. The memory cell has fewer number of transistors and terminals compared with the typical conventional memory cell. This reduces the area consumption and simplifies the implementation of memory's external circuit. In addition, the subthreshold swing (SS) of the memory cell is improved for larger coupling ratio. Experimental investigation on transfer characteristics, endurance, retention, and threshold voltage V_TH shift and leakage current of the high voltage NMOS of the memory cell are presented. The experimental endurance behaviour of the proposed memory cell is superior to the conventional memory cell.     

Adaptive instantaneous pitch detector with microcomputer error correction

A microcomputer is interfaced with an analogue circuit to detect the pitch of voiced speech over a 50 to 500 Hz range in real time.     

The effect of alpha-particle-induced soft errors on memory systems with error correction

Using Poisson statistics, a model for the survival probability of integrated memory circuits having both hard and soft error bit failure mechanisms is developed. Calculations are made over a range of soft error generation rates and erasure intervals for both single and double error correction. It is shown that even if the soft errors are erased effectively instantaneously, there is still an impact on the probability of system survival which is a function of soft error generation rate, and that in the case of instantaneous erasure of soft errors, a system with N bit error correction will have a probability of survival at least as good as the same system with N-1 bit error correction, no matter how high the soft error generation rate.     

A dual-port eight-transistor static memory cell with improved noise immunity

The results of simulation and measured parameters of a dual-selective static random access memory cell with two address inputs implemented in 180-nm CMOS technology are presented. Dependences of the static noise margin (SNM), write margin (WRM), noise margin at separate control nodes, and digit current on the potential of the trigger common bus are investigated. An increase in the SNM by 26% (up to 222 mV) and in the WRM by 6% (up to 1017 mV) as compared to the known circuit is obtained.     

Design of a programmable length FIFO memory and its controller

This paper describes the CMOS design of a first-in, first-out (FIFO) memory. The design is based on 2μ. meter CMOS technology and can operate with a 20 MHz clock. The length of the FIFO is programmable, resulting in minimum data ripple through time, for applications not requiring the full length.     

A high-density dual-port memory cell operation and arrayarchitecture for ULSI DRAMs

A high-density dual-port DRAM architecture is proposed. It realizes a two-transistor/one-capacitor (2Tr-1C) dual-port memory cell array with immunity against the array noise caused by the dual-port operation. This architecture, called a truly dual-port (TDP) DRAM, adopts the previously proposed divided/shared bit-line (DSB) sensing scheme in a dual-port 2Tr-1C DRAM array. A 2Tr-1C dual-port memory cell array with folded bit-line sensing operation, which does not increase the number of bit lines of the 1Tr-1C folded bit-line memory array, is realized, thus reducing the memory cell size. This architecture offers a solution to the fundamental limitations in the 2Tr-1C dual-port memory cell, and it is easily applicable to dual-port memory cores in ASIC environments. An analysis of the memory array noise in various dual-port architectures shows a significant improvement with this architecture. Applications to the complete pipelining operation of a DRAM array and a refresh-free DRAM core are also discussed     

A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining

This work describes a 500-MHz compiled eDRAM macro offered in a 90-nm logic-based process. The macro architecture is optimized for high bandwidth while enabling compilation in bank and data-word dimensions. A direct write scheme simultaneously improves random bank cycle time and row access time without signal loss. The benefits of ground sensing, reference cells, and bitline twisting was reviewed. A variable stage pipeline extends the macro bandwidth while offering flexibility in clock frequencies. The redundancy system is modified to support direct write and piping. Finally, BIST was enhanced to utilize electrically blown fuses, enabling one-touch test and repair. Hardware results was presented.     

ASMD with duty cycle correction scheme for high-speed DRAM

An analogue synchronous mirror delay with duty cycle-correction scheme (ASMDCC), to improve the data transmission performance between DRAM and system, is proposed. The ASMDCC achieves duty cycle correction and clock synchronisation at once within two clock cycles, by using a half value current source. The simulation results show the duty cycle of the internal clock is stabilised with less than ±100 ps deviation from 50% for the wide duty cycle range     

Application features of the error correction coding in sub-100-nm memory microcircuits for cosmic systems

The studies performed in the process of designing error correction coding elements in sub-100-nm memory and microprocessor microcircuits confirm that the most efficiency of increasing upset tolerances of commercial RHBD memory microcircuits can be ensured by combining modern circuit solutions for memory elements and algorithmic data encoding and protection methods. Among the circuit methods, the following methods are urgent: the application of DICE memory cells for checking (reference) data files; the introduction of additional columns and multiplexers, intended to replace any column with an additional one, if a multiple incurable upset arises in this column; the implementation of data interleaving with a degree of no more than 8 s to minimize adjacent upsets in the code word. Algorithmic encoding approaches of (SEC-DED-DAEC) classes (single-error correction, double-error-detection, and double-adjacent-error-correction) are efficient for ensuring the upset tolerance of sub-100-nm very-largescale integration (VLSI) circuits under the external action of single nuclear particles. The encoding algorithm based on these recommendations demonstrated up to 27% better efficiency of correction of nonadjacent double errors at a slightly slower speed of operation and occupied on-chip area, as compared with Datta and Choi codes, thus allowing one to implement different implementation versions of upset tolerant VLSI circuits, depending on the solved problem.     

A 2000-MOPS embedded RISC processor with a Rambus DRAM controller

We have developed a 0.25-μm, 200-MHz embedded RISC processor for multimedia applications. This processor has a dual-issue superscalar datapath that consists of a 32-bit integer unit and a 64-bit single-instruction multiple-data (SIMD) function unit that together have a total of five multiply-adders. An on-chip concurrent Rambus DRAM (C-RDRAM) controller uses interleaved transactions to increase the memory bandwidth of the Rambus channel to 533 Mb/s. The controller also reduces latency by using the transaction interleaving and instruction prefetching. A 64-bit, 200-MHz internal bus transfers data among the CPU core, the C-RDRAM, and the peripherals. These high-data-rate channels improve CPU performance because they eliminate a bottleneck in the data supply. The datapath part of this chip was designed using a functional macrocell library that included placement information for leaf cells and resulted in the SIMD function unit of this chip's having 68000 transistors per square millimeter     

An eight-channel 8 bit microprocessor compatible NMOS D/A converter with programmable scaling

A single-chip multiple-channel D/A converter is described. The NMOS chip contains a combination of digital and analog functions. Eight output channels with 8 bit accuracy are provided and each channel has programmable end points. The values for the data and the end points are stored in an internal RAM. Sample and-hold functions are completely on-chip. Only one multiplexed opamp is required for the analog functions. The entire control logic is incorporated in an easily testable PLA. The active chip area is 8 mm/SUP 2/. There are three power supplies (15,5,-5) with a total power dissipation of 120 mW. Updating of the eight channels occurs at a 16 kHz rate (5 MHz clock). The circuit aims at applications in microprocessor driven control systems in the industrial and consumer products field.     

Error correction and error detection techniques for wireless ATM systems

Error correction and error detection techniques are often used in wireless transmission systems. The Asynchronous Transfer Mode (ATM) employs Header Error Control (HEC). Since ATM specifications have been developed for high‐quality optical fiber transmission systems, HEC has single‐bit error correction and multiple‐bit error detection capabilities. When HEC detects multiple‐bit error, the cell is discarded. However, wireless ATM requires a more powerful Forward Error Correction (FEC) scheme to improve the Bit Error Rate (BER) performance resulting in a reduction in the transmission power and antenna size. This concatenation of wireless FEC and HEC of the ATM may effect cell loss performance. This paper proposes error correction and error detection techniques suitable for wireless ATM and analyzes the performance of the proposed schemes. This revised version was published online in June 2006 with corrections to the Cover Date.     

A 400-MHz random-cycle dual-port interleaved DRAM (D/sup 2/RAM) with standard CMOS Process

This paper describes a standard CMOS process based on embedded DRAM macro with dual-port interleaved DRAM architecture (D/sup 2/RAM), which is suitable for the leading edge CMOS LSIs with both high-speed and large-scale memories on a chip. This macro exploits three key technologies: fully sense-signal-loss compensating technology based on the whole detailed noise element breakdowns, the novel striped trench capacitor (STC) cell, and the write-before-sensing (WBS) circuit by decoded write-bus. A 400-MHz random cycle access has been verified for D/sup 2/RAM fabricated by a 0.15-/spl mu/m standard CMOS process.     

一种基于浮栅NMOS晶体管的可编程神经网络芯片的设计和应用

本文设计了一种浮栅NMOS晶体管神经网络,其结构简单、占用芯片面积小、连接强度可连续调整,同时,还具有分布神经元结构特点,可级联成大网络.用3μm浮栅NMOS工艺制造出的8×8全互连神经网络芯片,它有128个可编程浮栅NMOS晶体管,相当于8个神经元构成的全互连网络.以阿拉伯数字识别和二值图象处理为例,研究结果表明,该网络具有实用前景,且有很大灵活性,同时由于结构简单和适合集成电路工艺特点而便于制造。     

A byte organized NMOS/CCD memory with dynamic refresh logic

A 9216 bit NMOS/CCD memory organized as 1024 words by 9 bits is described. It employs a buried channel two phase charge-coupled device (CCD) storage cell combined with n-channel silicon gate Isoplanar (TM) MOS technology for logic functions and TTL compatible interfacing. Techniques of charge detection by using internally generated reference voltages are detailed. A low noise CCD input writing scheme and a dynamic sense-refresh cell are descried. Input-output logic is given that permits operating modes of read, write, read-modify-write, and recirculate. Operation at the specification limits of 100 kHz and 2 MHz is shown.     

A byte organized NMOS/CCD memory with dynamic refresh logic

A 9216 bit NMOS/CCD memory organized as 1024 words by 9 bits is described. It employs a buried channel two phase charge-coupled device (CCD) storage cell combined with n-channel silicon gate Isoplanar (TM) MOS technology for logic functions and TTL compatible interfacing. Techniques of charge detection by using internally generated reference voltages are detailed. A low noise CCD input writing scheme and a dynamic sense-refresh cell are described. Input-output logic is given that permits operating modes of read, write, read-modify-write, and recirculate. Operation at the specification limits of 100 kHz and 2 MHz is shown.     

连续YAG固体激光器电源的计算机闭环控制

本文探讨一种用单片机构成的激光电源闭环控制系统.该系统以单片机8031作为控制核心,兼有调节器和触发器功能,可使激光器工作电流自动调节,实现闭环.     

PCoSA: A product error correction code for use in memory devices targeting space applications

The radiation sensitivity of integrated memory cells increases dramatically as the supply voltage decreases. Although there are some Error Correcting Code (ECC) studies to prevent faults on memories used in space applications, there is no consensus on choosing the best ECC product-type with two-dimensional Hamming to mitigate data faults in memory. This work introduces the Product Code for Space Applications (PCoSA), an ECC product based on Hamming and parity in both rows and columns for use in memory with space-application reliability requirements. The potentialities of PCoSA were evaluated by injecting (i) thirty-six error patterns already available in the literature and (ii) all possible combinations of up to seven bitflips. PCoSA has corrected all cases of the thirty-six error patterns, and it has a correction rate of 100% for any three bitflips, 82.67% for four bitflips, and 69.7% for five bitflips.     

A programmable integrated digital controller for switching converters with dual-band switching and complex pole-zero compensation

The design of a 0.6-/spl mu/m CMOS programmable integrated digital PID controller for a buck converter is presented. Several novel features are implemented. These include: 1) a dual-band switching scheme for sampling the output voltage for better output resolution; 2) a dual-band switching PWM generator with a modified tapped delay line for area efficiency; 3) a VCO driving a counter to serve as an ADC; 4) a programmable PID compensator employing variable integration times for enhancing accuracy and stability; and 5) complex pole-zero cancellation in extending the bandwidth of the control loop. The converter is designed for variable output applications, and the fast digital loop achieves a tracking time of 50 /spl mu/s for a 1-V step change of the reference voltage. The converter switches at 1 MHz and attains a maximum efficiency of 90% when delivering a load of 125 mW.     

An SRAM cell with nonvolatile memory for programmable logicapplications

A memory cell has been developed and fabricated that during normal operation acts as an SRAM cell. The state of the cell can be “saved,” and at power up, the cell can be put back into that state