A built-in test pattern generator

Built-in testing is currently of more concern due to the difficulties in testing a VLSI byusing an external tester.In addition,Built-In Testing is also necessary for on-line testing and afault-tolerant computing system.Using a Linear Feedback Shift Register(LFSR)as a built-intest pattern generator(BITPG)is a realistic and simple approach.An LFSR with maximumlength can generate pseudo-random test patterns or all non-null vectors for exhaustive testing.This paper presents an LFSR design with non-maximum length to serve as a BITPG to generatea given test set T,which efficiently saves testing time.A search-verification process fordesigning this kind of LFSR is employed and implemented by the program SVBITPG.Thispaper presents the diagram of tire program and gives stone examples to illustrate the design ofthe BITPG.     

Throughput models of CSMA network with stations uniformly distributed along the bus

The distribution of station locations in a CSMA network can have significant effect onnetwork throughput. In this paper, we develop an analytic model for unslotted, non-persistentCSMA bus network where the stations are uniformly distributed along the bus. We derive aclosod form expression for throughput approximation, and discuss the fairness of CSMAprotocol using the bus topology. Analytic and simulation results are presented and compared.     

A Substitution Based Model for the Implementation of PROLOG——The Design and Implementation of LPROLOG

Since PROLOG has been chosen as the Fifth Generation Computer's Kernal Language,it ispresently one of the hottest topics among computer scientists all over the world.Recently,theimplementation technique and the application of PROLOG have been developed rapidly.In thispaper,a new implementation scheme for PROLOG is proposed.The scheme is based on thesubstitution of instantiated veriable values.It has many advantages,such as a higher runningspeed,less main memory requirement,and easier to be implemented.The scheme has beenimplemented by the authors on IBM4341.     

Compiling OR-parallelism into AND-parallelism

This paper suggests a general method for compiling OR-parallelism into AND-parallelism. An interpreter for an AND/OR-parallel language written in the AND-parallel subset of the language induces a source-to-source transformation from the full language into the AND-parallel subset. This transformation can be identified and implemented as a special purpose compiler or applied using a general purpose partial evaluator. The method is demonstrated to compile a variant of Concurrent Prolog into an AND-parallel subset of the language called Flat Concurrent Prolog (FCP). It is also shown applicable to the compilation of OR-parallel Prolog to FCP. The transformation identified is simple and efficient. The performance of the method is discussed in the context of programming examples. These compare well with conventionally compiled Prolog programs.     

The occur-check problem in Prolog

We present a method for preprocessing Prolog programs so that their operational semantics will be given by the first-order predicate calculus. Most Prolog implementations do not use a full unification algorithm, for efficiency reasons. The result is that it is possible to create terms having loops in them, whose semantics is not adequately described by first-order logic. Our method finds places where such loops may be created, and adds tests to detect them. This should not appreciably slow down the execution of most Prolog programs.     

A note on Moore's interval test for zeros of nonlinear systems

We study relations between Moore's interval test and Miranda's theorem. As an application we combine the (real) Newton iteration with a computational test for Miranda's hypothesis by Moore and Kioustelidis to find an approximate solution to the systemf(x)=0 with specified error bounds.     

Silicon neuron: digital hardware implementation of the quartic model

This paper presents an FPGA implementation of the quartic neuron model. This approach uses digital computation to emulate individual neuron behavior. We implemented the neuron model using fixed-point arithmetic operation. The neuron model’s computations are performed in arithmetic pipelines. It was designed in VHDL language and simulated prior to mapping in the FPGA. We show that the proposed FPGA implementation of the quartic neuron model can emulate the electrophysiological activities in various types of cortical neurons and is capable of producing a variety of different behaviors, with diversity similar to that of neuronal cells. The neuron family of this digital neuron can be modified by appropriately adjusting the neuron model’s parameters.     

A comprehensive study on RF MEMS switch

This paper emphasis on state-of-the-art of the earlier until the current trend and demand, principles, design considerations, key performance and fabrication technology of RF MEMS switch devices developed over the past few years. RF MEMS switch performance and features such as actuation voltage, insertion loss, isolation and ease with cost of fabrication and applications are compared and discussed.     

Short-term prediction of traffic flow using a binary neural network

This paper introduces a binary neural network-based prediction algorithm incorporating both spatial and temporal characteristics into the prediction process. The algorithm is used to predict short-term traffic flow by combining information from multiple traffic sensors (spatial lag) and time series prediction (temporal lag). It extends previously developed Advanced Uncertain Reasoning Architecture (AURA) k-nearest neighbour (k-NN) techniques. Our task was to produce a fast and accurate traffic flow predictor. The AURA k-NN predictor is comparable to other machine learning techniques with respect to recall accuracy but is able to train and predict rapidly. We incorporated consistency evaluations to determine whether the AURA k-NN has an ideal algorithmic configuration or an ideal data configuration or whether the settings needed to be varied for each data set. The results agree with previous research in that settings must be bespoke for each data set. This configuration process requires rapid and scalable learning to allow the predictor to be set-up for new data. The fast processing abilities of the AURA k-NN ensure this combinatorial optimisation will be computationally feasible for real-world applications. We intend to use the predictor to proactively manage traffic by predicting traffic volumes to anticipate traffic network problems.     

Prolog-ELF incorporating fuzzy logic

Prolog-ELF incorporating fuzzy logic and several useful functions into Prolog has been implemented as a basic language for building knowledge systems with uncertainty or fuzziness. Prolog-ELF inherits all the desirable basic features of Prolog. In addition to assertions with truth-values between 1.0 and 0.5 (0 for exceptional cases), fuzzy sets can be very easily manipulated. An application of fuzzy logical database is illustrated.     

A Prolog technology theorem prover

An extension of Prolog, based on the model elimination theorem-proving procedure, would permit production of a logically complete Prolog technology theorem prover capable of performing inference operations at a rate approaching that of Prolog itself.     

Bounded-wait merge in Shapiro’s Concurrent Prolog

InA Subset of Concurrent Prolog and Its Interpreter (1983), E. Y. Shapiro introduces the language Concurrent Prolog. In his presentation, the problem of guaranteeing bounded-waiting during a merge operation is used as a programming example. Solutions are proposed for binary and n-ary merges. The solutions are, however, completely dependent on specific operational characteristics of a Concurrent Prolog machine or interpreter. This paper presents an alternate approach in which the property of bounded-waiting is incorporated into the semantics of the programs, demonstrable given only the computational model of the language. The solution strategy is to utilize the familiar systems programming techniques of block-on-input and busy-wait. This approach requires that the language be augmented with a metalogical predicate analogous to thevar(_) predicate of Sequential Prolog. The resultant programs are interesting and illustrative examples of Concurrent Prolog as a programming language.     

Design and simulation of a sequential Prolog machine

Prolog-X is an implemented portable interactive sequential Prolog system in which clauses are incrementally compiled for a virtual machine called the ZIP Machine. At present, the ZIP Machine is emulated by software, but it has been designed to permit easy implementation in microcode or hardware. Prolog-X running on the software-based emulator provides performance comparable with existing Prolog interpreters. To demonstrate its efficiency, compatibility, and comprehensiveness of implementation, Prolog-X has been used to compile and run several large applications programs. Several novel techniques are used in the implementation, particularly in the areas of the representation of therecordx database, the selection of clauses, and the compilation of arithmetic expressions.