Rectifier for minimum line-current harmonics and maximum powerfactor

Rectifier line current harmonics interfere with proper power system operation, reduce rectifier power factor, and limit the power available from a given service. The rectifier's output filter inductance determines the rectifier line current waveform, the line current harmonics, and the power factor. Classical rectifier analysis usually assumes a near-infinite output filter inductance, which introduces significant error in the estimation of line current harmonics and power factor. A quantitative analysis of single and three-phase rectifier line current harmonics and power factor as a function of the output filter inductance is presented. For the single phase rectifier, one value of finite output filter inductance produces maximum power factor and a different value of finite output filter inductance produces minimum line current harmonics. For the three phase rectifier, a near-infinite output filter inductance produces minimum line current harmonics and maximum power factor, and the smallest inductance that approximates a near-infinite inductance is determined     

Design of CMOS tapered buffer for minimum power-delay product

The tapered buffer is analyzed from the viewpoint of power dissipation. Both uniform and nonuniform tapered buffers are considered. It is found that there is an optimum value of tapering factor for a minimum power-delay product. In case of uniform tapering, we can obtain an analytical solution of the optimum tapering factor for a minimum power-delay product, which is about 1.5~2 times larger than that for a minimum propagation delay. It is also found that there exists a nonuniform tapering factor which gives a global optimum condition for a minimum power-delay product, which, however, results in a larger short-circuit current. Compared with a uniform buffer, a nonuniform tapered buffer shows about 8% improvement in dynamic switching energy, and 3~5% improvement in total switching energy. We confirm this by simulating tapered buffers with SPICE     

数字化不间断电源对输入电网的谐波抑制

为了克服电网干扰对用电设备的破坏,目前广泛采用UPS为敏感用电设备供电。如何消除形形色色的干扰对用电设备造成的影响,为用电设备提供高可靠性、高质量的纯净电源,是各UPS厂商面对的问题。文章介绍了数字在线不间断电源中提高输入功率因数的方法,通过实时控制输入电流的波形,该UPS的功率因数近似为1,总的谐波分量大大减少。     

基于微波整流的半导体开关无线控制

针对有源电子标签及传感器节点低功耗唤醒模块的需求,设计了一种基于微波整流的半导体开关无线控制方法。通过微波整流之后的直流输出电压来控制半导体开关的状态,进而控制唤醒电路的直流电源通断,利用半导体开关关断状态下漏电流极低的特点,确保设备在休眠期达到极低功耗,从而延长标签及节点电源的工作时间。文中的微波整流设计主要以实现最大化直流输出电压为目标,整流天线部分采用双单元的整流阵列设计。仿真与测试结果表明,每一路天线接收到-18 dBm的射频功率时,直流输出电压可达到典型的CMOS开关控制所需的最低电平(1 V)。     

Minimum Fuel Consumption Strategy for PEM Fuel Cells

This paper proposes a proton exchange membrane fuel cell control strategy to produce the power requested by an electrical load, minimizing the fuel consumption and also providing a regulated dc bus voltage to the load. The power system consists of a hybrid fuel cell/capacitor topology, and the control objective is to follow the minimum fuel consumption points for a given load power profile. This is done by controlling the air pump voltage and regulating the fuel cell current through a dc/dc switching converter. Moreover, the design and control parameters of the output dc bus are discussed, and the calculations are adjusted to a Ballard 1.2-kW Nexa power module. Finally, the control results, fuel consumption, and fuel cell protection against oxygen starvation phenomenon are analyzed and experimentally validated, contrasting its performance with the Nexa power module internal control system.      

Picture-Based Address Power Saving Method for High Resolution Plasma Display Panel (PDP)

A picture-based high-speed address recovery technique for AC (adaptive control) plasma display panels (PDPs) is proposed. By removing the ground (GND) switching operation, the recovery speed can be increased and the switching loss due to the GND switch is reduced. The proposed method can perform load-adaptive operations by controlling the voltage level of the energy recovery capacitor, which prevents the increase of inefficient power consumption caused by circuit loss during the recovery operation. Thus, the technique shows the minimum address power consumption according to various displayed images, which is different from previous methods operating in fixed mode regardless of images. Test results with a 50-in HD single-scan PDP (resolution=1366 times 768) show that a recovery time of less than 350 ns is successfully accomplished and about 54% of the maximum power consumption can be reduced, by tracing the minimum power consumption curves.     

An Innovative Power-Gating Technique for Leakage and Ground Bounce Control in System-on-a-Chip (SOC)

Leakage has become one of the most dominant factors of power consumption and signal integrity of nanometer-scale integrated circuits. Recently, power-gating structures have proven to be effective in controlling leakage. In this paper an alternative dual-V _th reduced power-gating structure is proposed for better reduction of leakage currents, especially for low-power and high-performance portable devices. The proposed technique maintains an intermediate power-saving state as well as the conventional power cut-off state. The experimental results have demonstrated that the proposed technique can significantly reduce leakage current and associated power consumptions during the HOLD and CUT-OFF modes. In addition, an analysis of ground bounce due to power-mode transition in power-gating structures is presented. It is demonstrated that the proposed technique provides a way to control ground bounce during power-mode transition. Due to the presence of the intermediate state, its stepwise turning on feature will provide higher reduction of the magnitudes of peak current and voltage glitches in the power distribution network as well as the minimum time required to stabilize power and ground as compared to other similar techniques.     

Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes

This paper describes newly developed delay and power monitoring schemes for minimizing power consumption by means of the dynamic control of supply voltage V/sub DD/ and threshold voltage V/sub TH/ in active and standby modes. In the active mode, on the basis of delay monitoring results, either VDD control or VTH control is selected to avoid any oscillation problem between them. In V/sub DD/ control, on the basis of delay monitoring results, VDD is adjusted so as to be maintained at the minimum value at which the chip is able to operate for a given clock frequency. In V/sub TH/ control, on the basis of power monitoring results, VTH is adjusted so as to maintain a certain switching current I/sub SW//leakage current I/sub LEAK/ ratio known to indicate minimum power consumption. In the standby mode, the precision of power monitoring (which detects optimum body bias by comparing subthreshold current I/sub SUBTH/ to substrate current I/sub SUB/) is improved by taking into consideration both the effects of lowering V/sub DD/ and the effects of the presence of gate-oxide leakage current. Experimental results with a 90-nm CMOS device indicate that use of the proposed power monitoring results in the successful minimizing of power consumption. It does so by making it possible to: 1) maintain the I/sub SW//ILEAK ratio in the active mode and 2) detect optimum body bias conditions (I/sub SUBTH/=ISUB) within an error of less than 20% with respect to actual minimum leakage current values in the standby mode.     

An energy transmission system for an artificial heart using leakageinductance compensation of transcutaneous transformer

A power supply system using a transcutaneous transformer to power an artificial heart through intact skin has been designed and built. In order to realize both high-voltage gain and minimum circulating current, compensation of leakage inductances on both sides of a transcutaneous transformer is proposed. A frequency region which realizes the robustness against coupling coefficient and load variation is identified. In this region, the power converter has inherent advantages such as zero-voltage switching (ZVS) or zero-current switching (ZCS) of the switches, high-voltage gain, minimum circulating current and high efficiency     

基于UC3842的车用开关电源设计

基于UC3842高性能电流模式PWM芯片,提出一种供电动车无刷直流电机控制模块使用的开关电源设计方案。该设计由电动车的蓄电池供电,采用单端反激式结构,实现48V直流供电,12V的直流输出,具有瞬态响应快、稳定性好、输出电压精度高等优点,能够很好地满足电动车直流电机控制模块的供电需求。     

Thin-film persistent current switch

We have developed a fast, low power heat switch for switching a niobium thin film between the normal and superconducting state. The sputtered niobium film (400 nm thick, 100 /spl mu/m wide) has a critical current density of 5/spl times/10/sup 10/ Am/sup -2/. Switching is produced by joule heating a small section of the niobium film with a titanium thin-film resistor. With the heat switch in vacuum, the minimum heater power needed to switch to the normal state was 4.5/spl times/10/sup -5/ W. A simple three-dimensional thermal model shows that the minimum power is primarily determined by the thermal conductivity of the substrate. We have achieved response times less than 10/sup -6/ s.     

Joint power control and intracell scheduling of DS-CDMA nonrealtime data

The performance of DS-CDMA systems depends on the success in managing interference arising from both intercell and intracell transmissions. Interference management in terms of power control for real time data services like voice has been widely studied and shown to be a crucial component for the functionality of such systems. In this work we consider the problem of supporting downlink nonreal time data services, where in addition to power control, there is also the possibility of controlling the interference by means of transmission scheduling. One such decentralized schedule is to use time division so that users transmit in a one-by-one fashion within each cell. We show that this has merits in terms of saving energy and increasing system capacity. We combine this form of intracell scheduling with a suggested distributed power control algorithm for the intercell interference management. We address its rate of convergence and show that the algorithm converges to a power allocation that supports the nonreal time data users, using the minimum required power while meeting requirements on average data rate. Numerical results indicate a big potential of increased capacity and that a significant amount of energy can be saved with the proposed transmission scheme     

Modeling and Simulation of Wind Energy Systems with Matrix and Multilevel Power Converters

This paper is concerned with modeling and simulation in Matlab/Simulink of wind energy systems with different topologies for the power converters: matrix converter and multilevel converter. We use pulse modulation by space vector modulation associated with sliding mode for controlling the converters, and we introduce power factor control at the output of the converters. Finally, we present the electric behavior for the power and the current at the input and at the output of the converters.     

A 3.3-V ISDN U-interface line driver with a new I/sub Q/-control circuit

In this work, we propose a new quiescent current (I/sub Q/) control circuit applicable to line drivers for digital subscriber line (DSL) applications. The line driver consists of preamplifier, error amplifiers, output transistors, and I/sub Q/ control circuits. A new method is proposed for controlling I/sub Q/ values in order to obtain high linearity performance. It also helps to determine the minimum off-current value of the class-AB output stage to reduce crossover distortion. The line driver is implemented for ISDN U-interface applications. It is fabricated in a 0.35-/spl mu/m CMOS technology for a single power supply voltage of 3.3 V, and a total harmonic distortion of less than -64 dB is achieved.     

Design considerations for high-frequency crystal oscillatorsdigitally trimmable to sub-ppm accuracy

The current consumption of crystal oscillators is usually determined by the steady-state amplitude requirement, rather than the minimum transconductance for oscillation to exist, In a bipolar implementation transconductance is proportional to current, so that current consumption scales with frequency and load capacitance in the same way as transconductance. In a complementary metal-oxide-semiconductor (CMOS) implementation, current scales as the square of transconductance. It is therefore important to distinguish current from transconductance in power estimation for high frequency oscillators. Analytical expressions relating current to steady-state amplitude are used in this paper to estimate the minimum power required for a crystal oscillator at a given frequency. A 78 MHz crystal oscillator is described, which forms part of a regulated system in a pager where the oscillation frequency is controlled digitally to sub-ppm accuracy. The oscillator can be pulled from ±65 ppm to the required frequency with 0.2 ppm accuracy, with a maximum current consumption of 197 μA. The circuit has been fabricated in a 1-μm CMOS technology. The measured phase noise is -113 dBc/Hz at 300 Hz offset     

串联偏置迭堆式毫米波功率放大器的设计

设计了一种串联迭堆式偏置供电的毫米波功率放大器,其漏极供电电压高达+24V。该功率放大器共包含4个单芯片功率放大模块,每个模块承受+6V左右漏极电压。功率合成网络采用一分四的E面波导功分器,模块与功分网络间相互绝缘连接。该功率放大器最终实现的性能指标是:在直流偏置点(+24V,4.2A)条件下,功率放大器在频段26～30GHz内其连续波饱和输出功率大于42.1dBm,功率附加效率大于11.0%。提出了一种毫米波发射机功率输出部分新的构架形式,在模块级别对功率放大器串联馈电进行了首次尝试。     

EFDA泵浦源半导体激光器驱动电源的设计

设计了一种EFDA泵浦源半导体激光器的驱动电源,采用由PC机和单片机构成的上下位机的控制结构,具有恒定功率和恒定电流两种控制模式.该驱动电源具有激光器保护电路,电流精度和光功率控制精度分别为0.15％和0.2％.     

基于UC3854A/B的高功率因数变换器

文中分析了有源功率因数校正的基本原理，并采用平均电流控制芯片UC3854A/B设计出3.8Kw的高功率因数变换器。它基于电流跟踪技术、通过控制电感电流使其按正弦半波规律变化来提高网侧功率因数。结果表明，该设计电路功率因数高、输入电流失真度低，可明显的改善电网运行质量。     

Optimizing the Current Distribution in a Buried Linear Antenna

A solution is obtained to the problem of finding the current distribution in a buried linear antenna which minimizes the dissipated power while maintaining the required radiated field. An example shows that such distribution saves about 30 percent on power dissipation compared to an antenna of the same total length having simple bared-end grounding terminations. A practical method using current transformers is proposed for controlling the current distribution. A grounding system using this method has the property that it does not short out adjacent active antenna cables when it is in standby mode.     

A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT Variations on Nanoscale VLSI Systems

This paper proposes a novel design method to minimize the leakage power during standby mode using a novel adaptive supply voltage and body-bias voltage generating technique for nanoscale VLSI systems. The process, voltage, and temperature (PVT) variations are monitored and controlled independently by their own dedicated systems. The minimum level of $V_{rm DD}$ and the optimum body-bias voltage are generated for different temperature and process conditions adaptively using a lookup table method based on the PVT monitoring and controlling systems. The power supply variations is accurately compensated adaptively through the monitoring circuits based on the propagation delay change of the inverter chains. The subthreshold current as well as gate-tunneling and band-to-band-tunneling currents are monitored and minimized adaptively by the optimally generated body-bias voltage. The proposed design method reduces the leakage power at least by 500 times for ISCAS'85 benchmark circuits designed using 32-nm CMOS technology comparing to the case where the method is not applied.