Time-dependent-dielectric-breakdown characteristics of Hf-doped Ta2O5/SiO2 stack

The Time-Dependent-Dielectric Breakdown (TDDB) characteristics of MOS capacitors with Hf-doped Ta₂O₅ films (8 nm) have been analyzed. The devices were investigated by applying a constant voltage stress at gate injection, at room and elevated temperatures. Stress voltage and temperature dependences of hard breakdown of undoped and Hf-doped Ta₂O₅ were compared. The doped Ta₂O₅ exhibits improved TDDB characteristics in regard to the pure one. The maximum voltage projected for a 10 years lifetime at room temperature is −2.4 V. The presence of Hf into the matrix of Ta₂O₅ modifies the dielectric breakdown mechanism making it more adequate to the percolation model. The peculiarities of Weibull distribution of dielectric breakdown are discussed in terms of effect of three factors: nature of pre-existing traps and trapping phenomena; stress-induced new traps generation; interface layer degradation.     

Charge storage peculiarities in poly-Si–SiO2–Si memory devices with Si nanocrystals rich SiO2

The paper focuses on the study of charge trapping processes in non-volatile memory metal-oxide-silicon (MOS) structures with Si nanocrystal floating gate formed by Si ion implantation. Careful electrical studies of the MOS structures based on the analysis of the capacitance–voltage (C–V) characteristics during pulse charge injection in the oxide enabled the distinguishing of the electron emission from the nanoclusters and the charge trapping in structural defects of the dioxide matrix. The trapping model is discussed.     

Investigation of Ta2O5/SiO2/4H-SiC MIS capacitors

Tantalum pentoxide (Ta₂O₅) deposited by pulsed DC magnetron sputtering technique as the gate dielectric for 4H-SiC based metal-insulator-semiconductor (MIS) structure has been investigated. A rectifying current-voltage characteristic was observed, with the injection of current occurred when a positive DC bias was applied to the gate electrode with respect to the n type 4H-SiC substrate. This undesirable behavior is attributed to the relatively small band gap of Ta₂O₅ of around 4.3 eV, resulting in a small band offset between the 4H-SiC and Ta₂O₅. To overcome this problem, a thin thermal silicon oxide layer was introduced between Ta₂O₅ and 4H-SiC. This has substantially reduced the leakage current through the MIS structure. Further improvement was obtained by annealing the Ta₂O₅ at 900 °C in oxygen. The annealing has also reduced the effective charge in the dielectric film, as deduced from high frequency C-V measurements of the Ta₂O₅/SiO₂/4H-SiC capacitors.     

SiO2 masking against phosphorus diffusion using a P2O5 source

The masking of silicon against deep P₂O₅ diffusion by a 1-μ thick SiO₂ layer has been investigated. One aspect of masking failure has been related to mounds of phosphorus silicate glass, grown on the oxide during the P₂O₅ deposition, causing spot penetration of phosphorus through the oxide and into the silicon. Such spots can increase in density, diameter and depth during the subsequent diffusion. They link up and form a continuous, but not uniform n-type layer under the oxide. Residual water vapour in the deposition systems and particle deposits on wafers during washing have been shown to be the factors that contribute to the growth of mounds.     

The doped Si/SiO2 interface

A study is reported of the influence of dopant atoms on the SiSiO₂ interface states of thermally oxidized silicon. It was found that acceptor or donor atoms induce interface states and oxide charges. The effect is largest in the case of acceptor dopants and is independent of the doping process. The influence of the dopant atoms on oxide charge is probably related to the different segregation coefficients of acceptors and donors.     

Finite element analysis of LiNbO3 waveguides with Si orSi/SiO2 overlay

LiNbO₃ waveguides with Si overlays are emerging as a basic building block for a variety of integrated-optic components, including modulators, high-efficiency gratings, and narrowband WDM filters. However, the development and optimization of these devices are, in large part, hindered by the lack of understanding of the specifics of the Si-on-LiNbO₃ structure which appear to differ dramatically from those of the Si and LiNbO₃ waveguides, considered separately. In this work, we provide a specific insight into the waveguiding properties of vertically stacked Si-on-LiNbO₃ waveguides. In particular, we present a detailed theoretical analysis of the effect of the Si film on the modal characteristics (propagation constant and field distribution) of the structure. The vectorial finite element method (VFEM) is used to numerically investigate a step-index and graded-index single-mode channel waveguide in LiNbO₃, with a Si or Si/SiO₂ multimode overlay. We show that for ~70% of all Si thicknesses, in the range from 0 to 1.6 μm, the highest order normal mode of the entire structure has more than 99.9% of the total energy confined in the LiNbO₃ region, i.e., beneath the Si overlay. This fact is quite intriguing given the fact a planar Si layer of submicron thickness on bulk LiNbO₃ is already multimoded. Furthermore, we show that the effective mode index of the structure is considerably modified compared to that of the LiNbO₃ waveguide while the propagation loss is, on the other hand, practically unaffected (~0.3 dB/cm) even in the presence of the lossy Si film, as confirmed by our previous experimental results. Evidently, large modulation of the effective index and low-loss propagation provide an ideal combination of properties suitable for the fabrication of high-reflectance corrugated waveguide gratings, essential for a number of practical devices, in particular, WDM filters     

Flat-field spectrograph in SiO2/Si

The operation of a flat-field spectrograph in silica glass on silicon (SiO₂/Si) as a demultiplexer with 4-nm channel spacing in the 1.5-μm waveguide length region is demonstrated. The concept allows fabrication tolerances to be compensated simultaneously with the adjustment of fan-out. Fiber-to-fiber insertion loss of 10.1 dB and crosstalk attenuation >15 dB have been achieved     

Ferroelectricity-modulated resistive switching in Pt/Si:HfO2/HfO2-x/Pt memory

It is investigated for the effect of a ferroelectric Si:HfO₂ thin film on the resistive switching in a stacked Pt/Si:HfO₂/highly-oxygen-deficient HfO_2-x/Pt structure. Improved resistance performance was observed. It was concluded that the observed resistive switching behavior was related to the modulation of the width and height of a depletion barrier in the HfO_2-x layer, which was caused by the Si:HfO₂ ferroelectric polarization field effect. Reliable switching reproducibility and long data retention were observed in these memory cells, suggesting their great potential in non-volatile memories applications with full compatibility and simplicity.     

高反Al2O3/SiO2膜内超快激光预损伤动力学过程

利用紫外飞秒激光光谱技术研究了Al2O3/SiO2高反射膜内的超快载流子动力学。通过实验,发现该反射膜Al2O3层的载流子动力学在紫外反射膜的激光诱导损伤中起着至关重要的作用。通过泵浦-探测实验,发现紫外飞秒激光与光学薄膜作用后,光学薄膜反射率有所下降,且探测光反射率变化的峰值在约2.3 ps的时间内从417 nm左右转移到402 nm左右。为了更好的解释激光诱导载流子动力学,一个具体的理论模型被提出来,该模型指出导带自由电子弛豫过程中与晶格相互作用,产生距导带一个光子能量的中间缺陷态,其初始电子密度影响了材料损伤阈值高低。通过该理论模型得出的激光损伤阈值数据和实验数据吻合得很好。     

Distribution and generation of traps in SiO2/Al2O3 gate stacks

In this work we combine charge-pumping measurements with positive constant voltage stress to investigate trap generation in SiO₂/Al₂O₃ n-MOSFET. Trap density has been scanned either in energy or in position based on charge-pumping (CP) measurements performed under different operating conditions in terms of amplitude and frequency of the gate pulse. Our results have revealed that the traps are meanly localized shallow in energy level, deeper in spatial position and they are mostly generated near the Si/SiO₂ interface.     

Si衬底上具有Poly-Si/SiO2堆叠缓冲层的Pb (Zr0.52Ti0.48)O3 存储电容

在p型Si衬底上沉积多晶硅薄膜和Pb(Zr0.52Ti0.48)O3 (PZT)薄膜形成过渡层。测试淀积在多晶硅上的PZT薄膜不同退火温度的X射线衍射峰。Pt/PZT/poly-Si电容被研究。由于PZT薄膜的铁电极化特性,金属/铁电/多晶硅/二氧化硅/Si结构存储电容在650度退火展示了其顺时针的电压-电容曲线。存储窗口随着SiO2电容和PZT电容的耦合比的增加而增大。     

An epitaxial Si/SiO2 superlattice barrier

An epitaxial strain layer Si/SiO₂ superlattice barrier (SLSB) for silicon formed by monolayers of adsorbed oxygen, sandwiched between adjacent thin silicon layers deposited with molecular beam, showed good epitaxy with an effective barrier height of 1.7 eV. Such a barrier should be important for future quantum devices in silicon, as well as new applications in conventional MOS technology.     

Visible light emitting Si/SiO2 superlattices

Six-period superlattices of Si/SiO₂ have been grown at room temperature using molecular beam epitaxy. With this mature technology, the ultra-thin (1–3 nm) Si layers were grown to atomic layer precision. These layers were separated by 1 nm thick SiO₂ layers whose thickness was also well controlled by using a rate-limited oxidation process. The chemical and physical structures of the multilayers were characterized by cross-sectional TEM, X-ray diffraction, Raman spectroscopy, Auger sputter-profile, and X-ray photoelectron spectroscopy. The analysis showed that the Si layer is free of impurities and is amorphous, and that the SiO₂/Si interface is sharp (0.5 nm). Photoluminescence (PL) measurements were made at room temperature using 457.9 nm excitation. The PL peak occurred at wavelengths across the visible range for these multilayers. The peak energy position E was found to be related to the Si layer thickness d by E (eV) = 1.60+0.72d⁻² in accordance with a quantum confinement mechanism and the bulk amorphous-Si band gap.     

Low-frequency noise in Si0.7Ge0.3 surface channel pMOSFETs with ALD HfO2/Al2O3 gate dielectrics

Low-frequency noise was characterized in Si_0.7Ge_0.3 surface channel pMOSFETs with ALD Al₂O₃/HfO₂/Al₂O₃ stacks as gate dielectrics. The influences of surface treatment prior to ALD processing and thickness of the Al₂O₃ layer at the channel interface were investigated. The noise was of the 1/f type and could be modeled as a sum of a Hooge mobility fluctuation noise component and a number fluctuation noise component. Mobility fluctuation noise dominated the 1/f noise in strong inversion, but the number fluctuation noise component, mainly originating from traps in HfO₂, also contributed closer to threshold and in weak inversion. The number fluctuation noise component was negligibly small in a device with a 2 nm thick Al₂O₃ layer at the SiGe channel interface, which reduced the average 1/f noise by a factor of two and decreased the device-to-device variations.     

在SiO2中掺A1对Au／纳米（SiO2／Si／SiO2）／p—Si结构电致发光的影响

利用射频磁控溅射方法,制成纳米SiO2层厚度一定而纳米Si层厚度不同的纳米（SiO2/Si/SiO2）/p-Si结构和纳米（SiO2:A1/Si/SiO2:A1)/p-Si结构,用磁控溅射制备纳米SiO2:A1时所用的SiO2/A1复合靶中的A1的面积百分比为1%。上述两种结构中Si层厚度均为1-3nm,间隔为0.2nm。为了对比研究,还制备了Si层厚度为零的样品。这两种结构在900℃氮气下退火30min,正面蒸半透明Au膜,背面蒸A1作欧姆接触后,都在正向偏置下观察到电致发光（EL）。在一定的正向偏置下,EL强度和峰位以及电流都随Si层厚度的增加而同步振荡,位相相同。但掺A1结构的发光强度普遍比不掺A1结构强。另外,这两种结构的EL具体振荡特性有明显不同,对这两种结构的电致发光的物理机制和SiO2中掺A1的作用进行了分析和讨论。     

Effects of the metal gate on the stress-induced traps in Ta2O5/SiO2 stacks

The degradation of Ta₂O₅-based (10 nm) stacked capacitors with different top electrodes, (Al, W, Au) under constant current stress has been investigated. The variation of electrical characteristics after the stress is addressed to gate-induced defects rather than to poor-oxidation related defects. The main wearout parameter in Ta₂O₅ stacks is bulk-related and a generation only of bulk traps giving rise to oxide charge is observed. The post-stress current–voltage curves reveal that stress-induced leakage current (SILC) mode occurs in all capacitors and the characteristics of pre-existing traps define the stress response. The results are discussed in terms of simultaneous action of two competing processes: negative charge trapping in pre-existing electron traps and stress-induced positive charge generation, and the domination of one of them in dependence on both the stress level and the gate used. The charge build-up and the trapping/detrapping processes modify the dominant conduction mechanism and the gate-induced defects are precursors for device degradation. It is concluded that the impact of the metal gate on the ultimate reliability of high-k stacked capacitors should be strongly considered.     

脉冲激光对石英基底Ta2O5/SiO2滤光膜的损伤效应研究

随着高能激光系统的发展,对光学薄膜抵抗激光损伤能力的要求越来越高,而激光脉宽是脉冲激光对薄膜损伤行为的重要影响因素。针对Ta₂O₅/SiO₂多层膜,基于1-on-1测试方法,分析其在飞秒、皮秒、纳秒激光作用下的损伤特性。测得800 nm飞秒激光作用下的损伤阈值为1.67 J/cm₂;532 nm和1 064 nm皮秒激光作用下的损伤阈值分别为1.08 J/cm²和1.98 J/cm²;532 nm和1 064 nm纳秒激光作用下的损伤阈值分别为9.39 J/cm₂和21.57 J/cm₂,并使用金相显微镜观察了滤光膜的损伤形貌。实验结果表明：飞秒激光对滤光膜的损伤机理主要是多光子电离效应,而皮秒和纳秒激光对滤光膜的损伤机制主要是热效应。滤光膜在飞秒激光作用下的损伤阈值与皮秒激光作用下的损伤阈值相当,纳秒激光作用下的损伤阈值要高一个数量级,透射通带外损伤阈值约为通带内损伤阈值的2倍。     

Stack gate PZT/Al2O3 one transistorferroelectric memory

We have developed a single transistor ferroelectric memory using stack gate PZT/Al₂O₃ structure. For the same ~40 Å dielectric thickness, the PZT/Al₂O₃/Si gate dielectric has much better C-V characteristics and larger threshold voltage shift than those of PZT/SiO₂/Si. Besides, the ferroelectric MOSFET also shows a large output current difference between programmed on state and erased off state. The <100 us erase time is much faster than that of flash memory where the switching time is limited by erase time     

Interface states in SiSiO2 interfaces

Interface state parameters were studied in MOS capacitors over a wide range of energy by conductance and capacitance measurements at various temperatures from room temperature to liquid nitrogen temperature. A new technique was developed for analysis of the data which allows to obtain the density of states, the capture cross section, the surface potential and the dispersion parameter from the conductance and capacitance vs. frequency curves. The density of interface states as well as the electron capture cross section were found to be a function of energy only and to be independent of temperature. Maxima in the density of states have not been found.     

MOS transistors with stacked SiO2-Ta2O5-SiO2 gate dielectrics for giga-scale integration ofCMOS technologies

Advances in lithography and thinner SiO₂ gate oxides have enabled the scaling of MOS technologies to sub-0.25-μm feature size. High dielectric constant materials, such as Ta₂O₅ , have been suggested as a substitute for SiO₂ as the gate material beyond t_ox≈25 Å. However, the Si-Ta ₂O₅ material system suffers from unacceptable levels of bulk fixed charge, high density of interface trap states, and low silicon interface carrier mobility. In this paper we present a solution to these issues through a novel synthesis of a thermally grown SiO₂(10 Å)-Ta₂O₅ (MOCVD-50 Å)-SiO₂ (LPCVD-5 Å) stacked dielectric. Transistors fabricated using this stacked gate dielectric exhibit excellent subthreshold behaviour, saturation characteristics, and drive currents