一种用于接收机的低功耗自动增益控制环路

This paper proposes a new structure to lower the power consumption of a variable gain amplifier (VGA) and keep the linearity of the VGA unchanged. The structure is used in a high rate amplitude-shift keying (ASK) based IF-stage. It includes an automatic gain control (AGC) loop and ASK demodulator. The AGC mainly consists of six-stage VGAs. The IF-stage is realized in 0.18 μ m CMOS technology. The measurement results show that the power consumption of the whole system is very low. The system consumes 730 μ A while operating at 1.8 V. The minimum ASK signal the system could detect is 0.7 mV (peak to peak amplitude).     

一个新型的带自动增益控制环路的低功耗ASK接收机

实现了一个适用于短距离无线系统的低功耗ASK中频接收机电路.该接收机包括一个用于补偿信道衰减的自动增益控制环和一个ASK检波器.自动增益控制环中采用了新型的限流跨导器和带前馈的差分峰值检测器,从而以较低的功耗实现了较高的压缩比及较快的响应速度.通过在峰值存储单元中引入零点及在峰值检测电路中引入前馈,实现了对自动增益控制环阻尼特性的调整.ASK检波器中传统的整流器和低通滤波器被整合为更紧凑的结构,从而进一步降低了功耗.仿真结果验证了本文所提技术的有效性.     

一种低功耗快速起振晶体振荡器

基于CSMC0.5μm40VBCD工艺,设计了一种32.768kHz的晶体振荡器电路。通过Matlab分析振荡条件,以指导电路设计;通过自动增益控制环路,使振荡器的起振时间低至206ms;由微电流的跨导放大器实现了集成电路中的大电阻,用在反馈电阻和滤波器中;环路稳定后,振荡器核心电路的电流仅为195nA,同时,该电路还提供占空比为46%的方波输出。     

一种VHF频段具有抗振性能的晶体振荡器的设计

描述了一个100.0 MHz的石英晶体振荡器的设计和性能,提出了一种在振动条件下获得较好相位噪声性能的方法。测试结果表明:在静止状态下,晶体振荡器的相位噪声为:-143.0 dBc/Hz@1 kHz,-156.8 dBc/Hz@10 kHz;在任一方向的随机振动条件下,晶体振荡器的相位噪声优于-137.4 dBC/Hz@1 kHz,-150.9 dBC/Hz@10 kHz。     

一种20M低相位噪声晶体振荡器的设计

设计了一种20M低相位噪声晶体振荡器.通过对振荡原理的分析,选取了Santos结构的振荡器进行设计.该晶体振荡器由主振荡电路、振幅控制电路两部分组成,用标准的0.18 μm CMOS工艺实现,并通过Cadence平台下的软件进行仿真.结果表明,所设计的晶体振荡器的相位噪声在偏离中心频率1kHz、10kHz、1MHz处的...     

一种和接收机前端自动增益控制相集成的自适应天线

本文介绍一种准备用于轻便接收机的新型自适应天线,研究了一种线性自适应反馈调节器以控制两个接收单元间的相位关系,同时文中还叙述了调节器及一台完整射频样机。     

一个新型的带自动增益控制环路的低功耗ASK接收机

实现了一个适用于短距离无线系统的低功耗ASK中频接收机电路.该接收机包括一个用于补偿信道衰减的自动增益控制环和一个ASK检波器.自动增益控制环中采用了新型的限流跨导器和带前馈的差分峰值检测器,从而以较低的功耗实现了较高的压缩比及较快的响应速度.通过在峰值存储单元中引入零点及在峰值检测电路中引入前馈,实现了对自动增益控制环阻尼特性的调整.ASK检波器中传统的整流器和低通滤波器被整合为更紧凑的结构,从而进一步降低了功耗.仿真结果验证了本文所提技术的有效性.     

面向助听器应用的低功耗自动增益控制环路

自动增益控制环路是由可变增益放大器和负反馈回路构成的闭环系统,被广泛应用于助听器、磁盘驱动电路及各类无线通信电路.采用SMIC 0.13 μm 1P8M CMOS工艺,设计了一款用于助听器SOC的低功耗自动增益控制环路.该电路采用数字反馈回路进行增益控制.后仿真结果表明,在1V电源电压下,输入信号为8 kHz,输出信号峰峰值为126mV时,电路的无杂散动态范围为68.415dB,总谐波失真为68.397dB,整体功耗为290 μW,满足助听器SOC的应用需求.     

恒温温补石英晶体振荡器

提出了一种恒温温补晶振(OCTCXO)的实现方法,该OCTCXO由两部分组成:温度补偿晶体振荡器(TCXO)和恒温槽。TCXO放置在恒温槽中,恒温槽是一个负反馈自动控制系统,当环境温度小于恒温槽设定的温度时,OCTCXO相当于一个恒温晶体振荡器(OCXO);当环境温度大于恒温槽设定的温度时,恒温槽停止工作,整个OCTCXO的频率-温度稳定性由TCXO决定,由于OCTCXO最高工作温度与恒温槽设定的温度之间的温度区间很小,使得TCXO在该温度区间内的频率-温度稳定性得到较大的改善,从而提高OCTCXO的频率-温度稳定性。实验结果表明,该OCTCXO标称频率10 MHz,在-40～70℃温度范围内频率-温度稳定性为±1×10-7;最大功耗为1.15 W,常温工作时功耗为410 mW;体积为21.0 mm×13.0 mm×5.1 mm。     

具有自动增益控制的射频振荡器稳定性分析

设计了一个具有自动增益控制(AGC)的电路来稳定射频功率振荡器的输出幅度,然而在加入AGC负反馈环路之后,该环路可能会产生自激振荡,使得振荡器输出的幅度更加不稳定。通过对整个电路系统传递函数的分析,采用调节反馈电路中三极管发射极电阻阻值的方法,使该电路工作在稳定的状态,进而达到稳定振荡器输出幅度的目的。     

50 MHz低噪声Colpitts石英晶体振荡器设计

该文在振荡器Leeson模型的基础上分析了有载品质因数（QL）对振荡器相位噪声的影响,且通过分析Colpitts振荡电路得到了其QL的表达式,明确了QL与电路参数的精确关系。并用安捷伦ADS软件对50 MHz Colpitts晶体振荡器的相位噪声进行了仿真,根据仿真结果在提高QL的基础上设计了一晶体振荡器样机,样机采用AT切三次泛音、49U电阻焊封装的晶体谐振器,其无载品质因数（Q0）为1.45×105。经测试得到其相位噪声指标优于-107 dBc/Hz@10Hz、-134 dBc/Hz@100 Hz和-152 dBc/Hz@1 kHz。实验结果表明,基于提高QL设计低相噪晶体振荡器的方法是可行的。     

A Low Power Injection Locked LC-Tank Oscillator With Current Reused Topology

This letter presents a new current reused LC-tank injection locked oscillator (ILO), which is implemented by using a standard TSMC 0.18-mum CMOS process. The ILO, used as a divide-by-two (divide2) divider, is consisted of two switching transistors stacked in series. The injection locking is performed by adding an injection nMOS between the differential outputs of the divider. The divider can operate with a lower power due to the reuse of dc current. The measurement results show that at the supply voltage of 1.5V, the divider free-running frequency is tunable from 2.11 to 2.42GHz, and at the incident power of 0dBm the locking range of the divider in the divide2 mode is about 0.9GHz (19.8%), from the incident frequency 4.1 to 5GHz. The core power consumption is 0.97mW     

Eight-Way Substrate Integrated Waveguide Power Divider With Low Insertion Loss

We describe a compact radial cavity power divider based on the substrate integrated waveguide (SIW) technology in this paper. The equivalent-circuit model is used to analyze the multiport structure, and a design procedure is also established for the structure. An eight-way C-band SIW power divider with low insertion loss is designed, fabricated, and measured. Good agreement between simulated and measured results is found for the pro posed power divider. The measured minimum insertion loss of the eight-way power divider is approximately 0.2 dB and return loss is approximately 30 dB at 5.25 GHz. The measured 15-dB return-loss bandwidth is found to be approximately 500 MHz, and its 1-dB insertion-loss bandwidth is approximately 1.2 GHz. Furthermore, the isolations between the output ports of the eight-way power divider are also discussed.     

一种低功耗低温漂振荡器的设计

基于0.15 μm BCD工艺,提出了一种低功耗低温漂振荡器。分析了环形振荡器的振荡频率温度漂移特性,采用翻转电平优化技术,结合短路电流控制技术,获得了低温度漂移的振荡频率。且电流消耗极低。该振荡器适用于锂电池保护监测芯片。测试结果表明,在-40 ℃~100 ℃温度范围、32 kHz振荡频率、5 V电源电压条件下,该振荡器的振荡频率随温度的变化率小于3.3%,电流消耗仅为170 nA。     

基于锁相频率合成器的电压控制LC振荡器

详细描述了电压控制LC振荡器的设计思路、实现方法及指标测试。采用西勒振荡器作为振荡器的主体部分,通过改变变容二极管两端的电压来调节振荡器输出频率,实现输出频率在15MHz～35MHz范围内可变;采用集成锁相环芯片MC145152来提高振荡器输出频率的稳定度,使其达到10-5;通过AT89C51改变锁相环的分频比,实现频率步进为100kHz/1MHz的两种工作模式,并实时显示。     

Analysis and Implementation of a 0.9-V Voltage-Controlled Oscillator With Low Phase Noise and Low Power Dissipation

A voltage-controlled oscillator (VCO) with low phase noise and low power dissipation for IEEE 802.11b is proposed. A negative resistance multiple-gated circuit with a bypass capacitor is adopted to improve phase noise. The chip is implemented in 0.18-$mu{hbox {m}}$ CMOS process under a supply voltage of 0.9 V and power consumption of 2.7 mW. Its measured results show that the VCO has a phase noise of $-$122.3 dBc/Hz at 1-MHz offset frequency from the carrier frequency, and the tuning frequency from 2.17 to 2.73 GHz can be obtained under the tuning voltage of $-$0.9 to 0.9 V. The theoretical analysis and design consideration are also conducted in detail to show the benefits of the proposed VCO.      

Self-Biased Unity-Gain Buffers With Low Gain Error

This paper describes self-biased unity-gain buffers that use cascaded, complementary source followers with feed forward and feedback to reduce input-output offset and gain error. Single-ended and differential buffers have been designed, fabricated and tested.