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介绍了一种基于小数分频锁相技术的X波段频率合成器的设计方法。该频率合成器采用了内部集成VCO的锁相芯片进行电路设计,可在8.45~9.55 GHz频率范围内实现任意步进点频输出,并可实现大带宽线性调频信号输出,具有低相位噪声、大带宽、高集成度、小体积、低功耗和低成本等优点。最后给出了频率合成器的测试结果,包括信号的频谱测试图、跳频时间测试曲线和相位噪声测试曲线等。 相似文献
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《固体电子学研究与进展》2016,(6)
锁相环频率合成器环路带宽值的选取直接影响其输出相位噪声。基于此,本文首先介绍了锁相环的基本组成部分,然后分析了晶振、集成锁相芯片和压控振荡器相位噪声对频率合成器环路输出端的噪声影响,从而导出了最优环路带宽计算公式。并且通过基于PE3236芯片的频率合成器的输出相位噪声测量对最优环路带宽公式正确性进行了验证。结果表明:当根据最优环路带宽公式取值时,锁相环频率合成器的输出相位噪声满足实际应用需求。 相似文献
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在单边带通信中,相位噪声是代表短期稳定度的一种起伏量,也是频率合成器的主要技术指标。目前国内试制的频率合成器很多是在想方设法改善这一指标。本文仅就改善压控振荡器(以下简称VCO)的相位噪声提出一些切实可行的有效措施。 VCO的电压频率特性决定了VCO的压控灵敏度。若压频特性的线性不好,则引起压控灵敏度不均匀,从而使频率合成器的环路稳定性和相位噪声这二个主要技术指标之间的矛盾突出,同时也影响到环路阻尼因子ξ和自然频率ω_(n0)此外,在借助于LC压控 相似文献
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QAM全数字接收机载波相位恢复环路 总被引:2,自引:0,他引:2
本文着重研究全数字QAM接收机中载波恢复环路的设计,采用快慢两个数字环路来进行载波恢复,慢环路由锁频器(Frequency Detector),锁频锁相器(Phase and Frequency Detector)等组成,快环路由相痊解旋器和锁相器(Phase Detector)组成,仿真结果表明,在AWGN条件下,两个环路的环路参数设置存在一个最佳点,当两个环路工作在这个最佳点附近时接收机能够很好的进行载波频率,相位的恢复,相位噪声对接收机性能的影响最小,最后,给出了在不同信噪比下的最佳环路参数表。 相似文献
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低相噪,低杂波数字锁相环路滤波器的设计 总被引:11,自引:0,他引:11
较详细地分析数字锁相频率合成器的相位噪声,着重用控制论方法对低相噪、低杂波锁相环的环路滤波器进行设计,并用某S波段频率合成器的实验结果进行了验证。 相似文献
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A low noise phase locked loop (PLL) frequency synthesizer implemented in 65 nm CMOS technology is introduced. A VCO noise reduction method suited for short channel design is proposed to minimize PLL output phase noise. A self-calibrated voltage controlled oscillator is proposed in cooperation with the automatic frequency calibration circuit, whose accurate binary search algorithm helps reduce the VCO tuning curve coverage, which reduces the VCO noise contribution at PLL output phase noise. A low noise, charge pump is also introduced to extend the tuning voltage range of the proposed VCO, which further reduces its phase noise contribution. The frequency synthesizer generates 9.75-11.5 GHz high frequency wide band local oscillator (LO) carriers. Tested 11.5 GHz LO bears a phase noise of-104 dBc/Hz at 1 MHz frequency offset. The total power dissipation of the proposed frequency synthesizer is 48 mW. The area of the proposed frequency synthesizer is 0.3 mm^2, including bias circuits and buffers. 相似文献
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L波段低相噪、快锁定频率合成器研制 总被引:1,自引:0,他引:1
小数分频(FNPLL)频率合成器是近年来出现的一种新技术,它与传统的整数分频频率合成器相比具有频率分辨率高、相位噪声低、快速锁定等优点。用ANALOGDE.VICES公司的最新的小数分频锁相环频率合成器芯片ADF4193,设计了一个L波段锁相环频率合成器。文章系统地阐述了ADF4193的组成、工作原理,使用ADISimPLL软件进行环路滤波器设计,通过仿真得到各种性能指标,并对仿真结果和改变参数避开杂散的方法进行了详细分析。通过测试,结果证明了ADF4193组成的频率合成器具有优良的性能。 相似文献
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基于130 nm CMOS工艺设计了一款特高频(UHF)频段的锁相环型小数分频频率综合器.电感电容式压控振荡器(LC VCO)片外调谐电感总值为2 nH时,其输出频率范围为1.06~1.24 GHz,调节调谐电感拓宽了频率输出范围,并利用开关电容阵列减小了压控振荡器的增益.使用电荷泵补偿电流优化了频率综合器的线性度与带内相位噪声.此外对电荷泵进行适当改进,确保了环路的稳定.测试结果表明,通过调节电荷泵补偿电流,频率综合器的带内相位噪声可优化3 dB以上,中心频率为1.12 GHz时,在1 kHz频偏处的带内相位噪声和1 MHz频偏处的带外相位噪声分别为-92.3和-120.9 dBc/Hz.最小频率分辨率为3 Hz,功耗为19.2 mW. 相似文献
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设计了一款应用于CMMB数字电视广播接收的全集成低噪声宽带频率综合器。采用三阶ΣΔ调制器小数分频器完成高精度的频率输出,使用仅一个低相位噪声的宽带VCO输出频率范围覆盖900~1 600 MHz,产生的本振信号覆盖UHF的数字电视频段(470~790 MHz)。设计中的频率综合器能在所有的频道下保证环路的稳定以及最小的环路性能偏差。测试结果表明,整个频率综合器的带内相位噪声小于-85 dBc/Hz,并且带外相位噪声在1MHz时均小于-121 dBc/Hz,总的频率综合器锁定时间小于300μs。设计在UMC 0.18μm RFCMOS工艺下实现,芯片面积小于0.6 mm2,在1.8 V电源电压的测试条件下,总功耗小于22 mW。 相似文献
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Yido Koo Hyungki Huh Yongsik Cho Jeongwoo Lee Joonbae Park Kyeongho Lee Deog-Kyoon Jeong Wonchan Kim 《Solid-State Circuits, IEEE Journal of》2002,37(5):536-542
A fully integrated CMOS frequency synthesizer for PCS- and cellular-CDMA systems is integrated in a 0.35-μm CMOS technology. The proposed charge-averaging charge pump scheme suppresses fractional spurs to the level of noise, and the improved architecture of the dual-path loop filter makes it possible to implement a large time constant on a chip. With current-feedback bias and coarse tuning, a voltage-controlled oscillator (VCO) enables constant power and low gain of the VCO. Power dissipation is 60 mW with a 3.0-V supply. The proposed frequency synthesizer provides 10-kHz channel spacing with phase noise of -121 dBc/Hz in the PCS band and -127 dBc/Hz in the cellular band, both at 1-MHz offset frequency 相似文献
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Debashis Mandal T. K. Bhattacharyya 《Analog Integrated Circuits and Signal Processing》2010,62(2):253-257
This paper presents a very low-power linearization technique to improve the linearity of frequency-voltage characteristic of LC-VCO (voltage controlled oscillator) using MOS varactor. This reduces the VCO gain (K VCO) variation and its required value over the tuning voltage range. Low K VCO improves noise and reference spur performances at the output of phase lock loop/frequency synthesizer (FS). Low K VCO variation reduces FS loop stability problem. Using this VCO circuit, a fully on-chip integer-N frequency synthesizer has been fabricated in 0.18 μm epi-digital CMOS technology for 2.45 GHz ZigBee application. The measured VCO phase noise is ?115.76 and ?125.23 dBc/Hz at 1 and 3 MHz offset frequencies, respectively from 2.445 GHz carrier and the reference spur of the frequency synthesizer is ?68.62 dBc. The used supply voltage is 1.5 V. 相似文献
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A wideband low phase noise frequency synthesizer at X/Ku band has been developed by using phase locking and mixing technique
at half frequency of voltage controlled oscillator (VCO). The half frequency output signal of the VCO is down converted by
a balanced mixer at C band to obtain an intermediate frequency (IF) signal used for phase locking of the VCO. An ultra low
phase noise local signal source at 6 GHz is developed with a frequency multiplying chain driven by a 100 MHz oven controlled
crystal oscillator (OCXO). Coupling circuit outside the VCO chip to the mixer does not need to be specially designed, which
is beneficial to simplify the circuit scheme and improve the phase noise performance. Measurement results show that the phase
noise of the output signal at 10.6 GHz to 11.8 GHz and 12.3 GHz to 13.0 GHz is better than −102 dBc/Hz at 10 kHz away form
the carrier center. This frequency synthesizer can be used as local signal source or driving source for the development of
wideband millimeter-wave frequency synthesizer systems. 相似文献
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A 900-MHz phase-locked loop frequency synthesizer implemented in a 0.6-μm CMOS technology is developed for the wireless integrated network sensors applications. It incorporates an automatic switched-capacitor (SC) discrete-tuning loop to extend the overall frequency tuning range to 20%, while the VCO gain (KVCO) resulting from the CMOS varactor continuous-tuning is kept low at only 20 MHz/V in order to improve the reference spurs and noise performance. This frequency synthesizer achieves a phase noise of -102 dBc/Hz at 100 kHz offset frequency and reference spurs below -55 dBc. The synthesizer, including an on-chip VCO, dissipates only 2.5 mA from a 3-V supply 相似文献
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Phase Noise Model of Single Loop Frequency Synthesizer 总被引:7,自引:0,他引:7
Young Wan Kim Jae Du Yu 《Broadcasting, IEEE Transactions on》2008,54(1):112-119
The phase noise spectrum of a single loop frequency synthesizer for S-band, which can be utilized in broadcasting terminals, was predicted based on the analyses for phase noise contributions of noise sources. The proposed phase noise model in this paper more accurately predicts the phase noise spectrum of a frequency synthesizer. To accurately model the phase noise contributions of noise sources in the frequency synthesizer, the phase noise sources were analyzed via modeling of the frequency divider and phase noise components using Leeson model for the reference signal source and VCO. The phase noise transfer functions to VCO from noise sources were analyzed by superposition theory and linear operation of the phase-locked loop. The frequency synthesizers were fabricated and the phase noise prediction model was evaluated by measured data and prediction data. 相似文献
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A fractional-N frequency synthesizer fabricated in a 0.13 μm CMOS technology is presented for the application of IEEE 802.11 b/g wireless local area network (WLAN) transceivers.A monolithic LC voltage controlled oscillator (VCO) is implemented with an on-chip symmetric inductor.The fractional-N frequency divider consists of a pulse swallow frequency divider and a 3rd-order multistage noise shaping (MASH) △ ∑ modulator with noise-shaped dithering techniques.Measurement results show that in all channels,phase noise of the synthesizer achieves -93 dBc/Hz and -118 dBc/Hz in band and out of band respectively with a phase-frequency detector (PFD) frequency of 20 MHz and a loop bandwidth of 100 kHz.The integrated RMS phase error is no more than 0.8°.The proposed synthesizer consumes 8.4 mW from a 1.2 V supply and occupies an area of 0.86 mm2. 相似文献