共振隧穿器件应用电路概述——共振隧穿器件讲座(2)

在“共振隧穿器件概述”的基础上,对共振隧穿器件应用电路作了全面概括的介绍。首先对共振隧穿器件应用电路的特点、分类和发展趋势作了简述;进一步对由RTDH/EMT构成的单-双稳转换逻辑单元(MOBILE)和以它为基础构成的RTD应用电路,包括柔性逻辑、静态随机存储(SRAM)、神经元、静态分频器等电路的结构、工作原理和逻辑功能等进行了介绍。关于RTD/HEMT构成的更为复杂的电路,如多值逻辑、AD转换器以及RTD光电集成电路等将在本讲座最后部分进行讲解。     

Monolithically Fabricated OEICs Using RTD and MSM

报道了GaAs基共振隧穿二极管(RTD)与金属-半导体-金属光电探测器(MSM PD)单片集成的两种光电集成电路,并在室温条件下分别测试了RTD器件、MSM器件和集成电路的电学特性.测试表明:RTD器件的峰谷电流比为4;由于改进了在半绝缘GaAs衬底上制作MSM的方法,5V偏压下的电流由原来的2μA增加到了18μA,基本实现了两种电路的逻辑功能.     

GaAs基RTD与MSM光电集成

报道了GaAs基共振隧穿二极管(RTD)与金属-半导体-金属光电探测器(MSM PD)单片集成的两种光电集成电路,并在室温条件下分别测试了RTD器件、MSM器件和集成电路的电学特性.测试表明:RTD器件的峰谷电流比为4;由于改进了在半绝缘GaAs衬底上制作MSM的方法,5V偏压下的电流由原来的2μA增加到了18μA,基本实现了两种电路的逻辑功能.     

UTC-PD和RTD单片集成的器件模拟研究

单行载流子光电二极管与共振隧穿二极管单片集成器件是一种新型高速光电探测器,也是高速光电单稳双稳转换逻辑电路的一个基本单元。用Atlas软件对该集成电路单元进行了直流和交流特性的模拟研究,模拟得到的3dB带宽最高可达9THz。模拟发现,光照强度、吸收层厚度、掺杂浓度、收集层浓度是影响器件3dB带宽的主要因素。研究了器件材料参数、结构参数与器件3dB带宽之间的关系,并得到在现行工艺下优化后的单行载流子光电二极管和共振隧穿二极管单片集成器件的工艺参数,模拟出3dB带宽为1.03THz。同时,对器件模拟和半导体工艺间的误差进行了分析和估计。这一工作为单行载流子光电二极管和共振隧穿二极管单片集成器件的设计和研制提供了工艺参数基础。     

MSM-PD与RTD光电集成的模拟

设计了由谐振隧穿二极管(RTD)为驱动器件,以金属-半导体-金属光探测器(MSM-PD)为光敏元件的光电集成电路单元,利用通用电路模拟软件PSPICE基于其物理意义的电流-电压方程建立直流电路模型,模拟其暂态特性,结果表明器件具有反相输出功能和双稳态特性.     

单稳双稳态转变逻辑单元等效电路模型

基于共振隧穿二极管的单片集成的单稳双稳态转变逻辑单元电路是近年出现的一种新型电路逻辑单元．本文介绍一种简单的ＭＯＢＩＬＥ电路结构,给出了适合于ＰＳＰＩＣＥ模拟的模型,并根据模拟结果分析了共振隧穿二极管电容的充放电过程,同时讨论了ＭＯＢＩＬＥ电路工作的内部物理过程．     

硅基隧穿二极管

隧穿二极管是一种很有前途的基于带隙工程的异质结构量子器件,其电流电压(I-V)曲线中所呈现的微分负阻特性能够用于开发多种不同的电路功能。在最近的研究中,空穴型双势垒单势阱共振隧穿二极管得到了实现,为Si1-xGex/Si异质结隧穿二极管器件的改进和电路应用打下了良好的基础。     

基于共振隧穿二极管的阈值逻辑单元电路设计

共振隧穿二极管作为较为成熟的纳米电子器件,已被广泛应用于高速低功耗电路。由于其具有负内阻特性,单一门电路的功能大大增加,减少了电路的复杂度。在阈值逻辑函数的硬件实现方面,共振隧穿器件也体现出显著的优势。结合谱技术,基于共振隧穿二极管,设计了可实现任意三变量阈值逻辑函数的阈值逻辑单元电路。该电路还可作为阈值逻辑网络中的基本单元,实现复杂的逻辑功能。通过HSPICE软件,仿真验证了所设计电路的正确性。     

基于共振隧穿二极管的阈值逻辑单元电路设计

共振隧穿二极管作为较为成熟的纳米电子器件,已被广泛应用于高速低功耗电路。由于其具有负内阻特性,单一门电路的功能大大增加,减少了电路的复杂度。在阈值逻辑函数的硬件实现方面,共振隧穿器件也体现出显著的优势。结合谱技术,基于共振隧穿二极管,设计了可实现任意三变量阈值逻辑函数的阈值逻辑单元电路。该电路还可作为阈值逻辑网络中的基本单元,实现复杂的逻辑功能。通过HSPICE软件,仿真验证了所设计电路的正确性。     

直接隧穿栅电流对CMOS逻辑电路的影响

对于纳米级的CMOS电路,由于MOS器件具有超薄的氧化层,栅隧穿漏电流的存在严重地影响了电路的正常工作。本文基于可靠性理论和电路级仿真深入地研究直接隧穿电流对CMOS逻辑电路的影响。仿真结果很好地与理论分析相符合,这些理论和仿真将有助于以后的集成电路设计。     

Design of a DTCTGAL circuit and its application

By research on the switch-signal theory for multiple-valued logic circuits, the theory of three essential elements and the principle of adiabatic circuits, a design scheme for a double power clock ternary clocked transmission gate adiabatic logic (DTCTGAL) circuit is presented. The energy injection and recovery can be conducted by the bootstrapped NMOSFET, which makes the circuit maintain the characteristics of energy recovery as well as multiple-valued input and output. An XOR/XNOR circuit based on DTCTGAL is also presented using this design scheme. Finally, using the parameters of a TSMC 0.25 μm CMOS device, PSPICE simulation results indicate that the proposed circuits have correct logic and significant low power characteristics.     

Modified super pass gate for multiple-valued logic circuits

A model of a super pass gate (SPG) is adapted to allow multiple-valued logic circuit connections and designs that are normally prohibited by the formal synthesis and minimisation technique for the device. The modification of the SPG allows more efficient circuit minimisation to be achieved for functions that do not readily reduce under the formal synthesis technique     

CMOS门电路电磁信息泄漏评估

通过将CMOS工艺中的导线转化为电偶极子模型,提出了一种对CMOS工艺的门电路进行电磁信息泄漏评估的方法.仿真实验采用TSMC0.18μm工艺,实现了基于单轨逻辑以及SABL双轨逻辑的与非门,并用提出的评估方法对门电路的电磁信息泄漏进行评估.仿真结果表明,该评估方法能够对CMOS门电路的电磁信息泄漏程度进行量化评估,同时还表明了双轨门电路电磁信息泄漏弱于单轨门电路.     

Circuit testable design and universal test sets for multiple-valued logic functions

The circuit testable realizations of multiple-valued functions are studied in this letter. First of all, it is shown that one vector detects all skew faults in multiplication modulo circuits or in addition modulo circuits, and n＋1 vectors detect all skew faults in the circuit realization of multiplevalued functions with n inputs. Secondly, min（max） bridging fault test sets with n＋2 vectors are presented for the circuit realizations of multiple-valued logic functions. Finally, a tree structure is used instead of cascade structure to reduce the delay in the circuit realization, it is shown that three vectors are sufficient to detect all single stuck-at faults in the tree structure realization of multiplevalued logic functions.     

Module compiler for high-radix CCD-PLAs

A compiler has been developed that translates a multiple-valued logic expression into a circuit which realizes that expression. The circuits produced are for the high-radix peristaltic charge-coupled device (P2CCD) technology described by us in 1986. Each design is a programmable logic array (PLA), including the required sense amplifiers, dummy registers, voltage-to-charge converters, and precharge transistors. The multiple-valued expression is represented as a sum-of-products of literal operations, where product is the minimum operation and sum is the truncated sum operation. An example of a PLA implementation produced by the compiler is given.     

Compatible cell connections for multifamily dynamic logic gates

Dynamic logic is an alternative way of making logic circuit cells and numerous techniques have been developed to take advantage of its unique characteristics. Particularly, techniques such as the true-single-phase-clock (TSPC) have been used very successfully for fast and low-power applications. However one cannot synthesize dynamic logic gates with the same ease as static gates. One reason is there are no simple rules to connect the many circuit types of dynamic gates to static gates. This paper addresses the problem of finding connection rules for a given set of gate types. The fundamental cell circuit types for dynamic logic gates are analyzed first together with static logic gates. A common set of principles of operation and connections is then identified and later applied to discover which are the feasible connections between cell circuit types identified.     

基于多值逻辑电路和二值PLA的硬件模糊控制器

本文基于多值逻辑电路和二值可编程逻辑阵列，提出一种模糊控制器硬件设计方案。     

A 1.5 V full-swing BiCMOS dynamic logic gate circuit suitable forVLSI using low-voltage BiCMOS technology

This paper presents a 1.5 V full-swing BiCMOS dynamic logic gate circuit, based on a dynamic pull-down BiPMOS configuration, suitable for VLSI using low-voltage BiCMOS technology. With an output load of 0.2 pf, the 1.5 V full-swing BiCMOS dynamic logic gate circuit shows a more than 1.8 times improvement in speed as compared to the CMOS static one     

基于RT器件的三值与非门、或非门电路设计

共振隧穿（resonant tunnel,RT）器件本身所具有的微分负阻（negative differential resistance,NDR）特性使其成为天然的多值器件，文中利用RT器件的负阻特性,以开关序列原理为指导,设计了基于RT电路的开关模型,实现了更为简单的三值RT与非门和或非门电路,并利用MOS网络模型,通过SPICE软件仿真验证了所设计电路的正确性，该设计思想可推广到更高值的多值电路设计中。