宽板激光拼接技术及设备

论文介绍了所研制的一种采用激光切割——焊接组合工艺进行宽板拼接的关键技术及成套设备。工艺参数优化后的激光无氧切割可获得基本无挂渣、无氧化的光滑切割断口。两坯板在切割——焊接全过程中始终被左右夹钳夹持,分别先后在同一切割头运动下完成切割程序。左右夹钳在原切割位置自动拼合坯板。宽度为2m的坯板拼缝间隙可控制在0.05mm以下。为了保证拼缝与焊接头的运动轨迹重合,切割与焊接采用同一组反射聚焦镜片,切割与焊接功能的转换通过自动装上和卸下切割喷嘴实现,避免了一般光路传输反射镜切换方案可能产生的重合误差。该设备配备有激光焊接过程稳定性的实时监测系统,可识别2mm以上未焊透和烧穿缺陷。该设备不仅能拼焊等厚板,也能拼焊不等厚板,拼焊接头性能可满足汽车零件冲压成型的要求。     

低温共烧陶瓷生坯块切割毛边的分析及改善

生瓷坯切割作为低温共烧陶瓷（LTCC）工艺中的重要工序,对产品的外形尺寸和产品外观形貌具有关键的影响。针对热切时生坯外形毛边产生原因进行了分析,确定了浆料的分散特性、粘结剂含量及粘结剂/增塑剂的比值、切割温度是切割时产生毛边的主要原因。通过对粉体形貌及粒度分布、浆料分散特性、浆料配方中的粘结剂含量以及粘结剂/增塑剂含量之比、切割温度进行优化,明显改善了切割毛边问题。     

影响LCD玻璃切割机切割精度的参数的优化

随着LCD行业的产品技术的日新月异,产线工艺设备的精度指标和使用要求也不断提升.阐述了LCD玻璃切割机中影响切割精度的重要参数.从工作台的综合性能、切割位置精度、切割压力精度着手,分析了三种参数对切割精度的影响,给出了提升性能的优化方法.通过分析和优化,可以有效提高设备的整机性能,提升设备的市场竞争力.     

共边排样件激光切割路径的规划

排样软件的应用使材料利用率得到了很大提高，然而后续切割软件若不能保证有效地切割零件、保证零件质量及提高生产率，则排样软件在材料利用率上获得的收益将丧失。基于图论学理论，建立了规则与非规则零件共边排样时激光切割路径规划的数学模型，给出了在充分考虑加工质量、加工效率、制造成本情况下的激光切割路径优化目标：打孔点最少以及切割中割嘴空行程最短。提出了满足激光切割工艺要求的三个切割路径优化算法：用于求解理想情况下共边切割路径优化问题的一个新的欧拉回路算法；基于奇度顶点完全图最小权最大匹配算法来求解一般情况下共边切割路径优化问题的算法；利用废料区域进一步减少打孔点的处理策略与求解算法。给出了各种算法的运行实例，验证了所提出的算法的有效性。     

少无废料激光板材切割技术

采用少无废料激光板材切割技术,可以大幅度地提高材料利用率,缩短切割时间,提高生产效率。激光切割路径优化算法和板材的无搭边排样技术是少无废料激光板材切割的关键技术问题。文章研究了少无废料激光切割路径优化原则,在此基础上,研究了少无废料激光切割编程技巧,并结合纺机板材的激光切割实践,进行了少无废料激光板材切割技术研究,结果表明,采用少无废料激光切割技术,材料利用率可10%~30%,切割长度可减少5%~10%。     

激光切割排样系统在硅钢板材加工中的应用

激光切割技术是当前世界上最先进的切割工艺之一，加之排样软件的应用，使板材的利用率得到了很大提高。为了填补扇片零件研究的不足，借鉴传统多边形顶点射线算法的基本原理，提出扇片零件顶点射线算法，解决了任意包角以及任意半径的扇片零件在硅钢板材上的优化排样问题。同时，以该算法为基础，利用VC++6.0开发了一套激光切割排样系统，进行了大量实际排样优化计算。实验结果表明，该算法既满足了实际生产中激光切割的工艺要求，又能够有效地提高硅钢板材的利用率。     

定尺切割技术在莱钢板坯连铸机中的应用

本文介绍了定尺切割技术在板坯连铸机铸坯切割中的应用,对该自控系统的硬件结构、控制功能及其实现进行了描述,两种定尺切割模式灵活选用,结构化的编程模式功能可进一步扩展,使整个火焰切割自控系统更具有可读性、实用性和维护性.     

分层实体制造激光头切割路径的建模与优化

分层实体制造(LOM)技术中分层制造时间是由该层的切割速度与切割路径确定的，当切割工艺参数(如：切割功率、切割速度)确定之后，每一层制造的时间是由该层切割(扫描)路径确定的。因此优化切割(扫描)路径对提高成型效率有重要意义，而分层实体制造技术中激光切割路径优化的实质是空行程路径的优化。建立了切割路径空行程路径优化的数学模型。由于求解该模型的复杂性，采用了分级规划的两个分步算法：首先用改进的最近邻域算法求解轮廓边界线上的切割起点，然后当切割点确定后把路径优化问题归结为旅行售货员问题(TSP)，采用了高效的智能仿生算法一蚁群系统算法来求解。运行结果表明，该算法显著缩短了分层制造中的空行程，提高了快速原型制造的效率。     

包含多重嵌套轮廓线的激光切割空移路径规划

包含多重嵌套轮廓线的空移路径规划是开发激光切割系统的主要问题之一,在满足嵌套图形由内到外的激光切割工艺要求下,提出启发式排序和网格排序算法,实现优化排序。首先通过射线法,判断多重嵌套轮廓线的位置关系;然后采用最佳适应度优先的启发式排序算法,将空移距离、轮廓线的面积作为评价指标,分别赋值权重得到总体适应度,选择适应度高的轮廓线作为下一个切割图形;最后,为了满足不同应用场景,提出另外一种网格排序方法,根据轮廓线控制点的疏密程度,基于层次聚类算法划分网格,按照规则的路线遍历网格,依次确定定位到每个网格中的轮廓线。仿真与试验结果表明,相比于智能优化排序算法,启发式排序和网格排序在满足激光切割工艺要求的前提下,不仅可以有效缩短空移路径,还大大减少了计算时间,显著提高激光切割效率和质量。     

提高三维激光切割平顺性的切割头空间位姿优化方法

三维激光切割头空间位姿变化的平顺性直接影响机床切割效率、安全和稳定性。建立了三维激光切割机五轴联动运动学模型,分析切割轨迹刀位点几何信息转换为机床五个运动轴空间坐标的可选值。结合B和C旋转轴运动部件间的摩擦力、质量和转动惯量,建立相邻刀位点间的旋转轴旋转运动耗能模型。将完整切割环上旋转轴运动最低总耗能作为优化目标,通过Dijkstra最小路径优化算法,获得完整切割环上的最佳切割方式。通过实例分析,该方法可避免B和C轴瞬间摆动过大情况,提高了切割头运动的平顺性。     

Ranking Potential Reply-Providers in Community Question Answering System

Community Question Answering （CQA） websites have greatly facilitated users＇ lives, with an increasing number of people seeking help and exchanging ideas on the Internet. This newlymerged community features two characteristics： social relations and an ask-reply mechanism. As users＇ behaviours and social statuses play a more important role in CQA services than traditional answer retrieving websites, researchers＇ concerns have shifted from the need to passively find existing answers to actively seeking potential reply providers that may give answers in the near future. We analyse datasets derived from an online CQA system named ＂Quora＂, and observed that compared with traditional question answering services, users tend to contribute replies rather than questions for help in the CQA system. Inspired by the findings, we seek ways to evaluate the users＇ ability to offer prompt and reliable help, taking into account activity, authority and social reputation char- acteristics. We propose a hybrid method that is based on a Question-User network and social network using optimised PageRank algorithm. Experimental results show the efficiency of the proposed method for ranking potential answer-providers.     

一个全差分可编程的多通道神经信号记录芯片

A multi-channel,fully differential programmable chip for neural recording application is presented.The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain,eight 4thorder Bessel switch capacitor filters,an 8-to-1 analog time-division multiplexer,a fully differential successive approximation register analog-to-digital converter(SAR ADC),and a serial peripheral interface for communication.The neural recording amplifier presents a programmable gain from 53 dB to 68 dB,a tunable low cut-off frequency from 0.1 Hz to 300 Hz,and 3.77 μVrms input-referred noise over a 5 kHz bandwidth.The SAR ADC digitizes signals at maximum sampling rate of 20 kS/s per channel and achieves an ENOB of 7.4.The integrated circuit is designed and fabricated in 0.18-μm CMOS mix-signal process.We successfully performed a multi-channel in-vivo recording experiment from a rat cortex using the neural recording chip.     

A power-efficient 12-bit analog-to-digital converter with a novel constant-resistance CMOS input sampling switch

Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter（ADC）implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two op- amp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode （RFC） amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC＇s performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range （SFDR） of 75.7 dB and a signal-to-noise-plus-distortion ratio （SNDR） of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity （DNL） and integral nonlinearity （INL） are -0.43 to ＋0.48 LSB and -1.62 to ＋ 1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure- of-merit （FOM） of 0.63 pJ per conversion-step.     

Low power high gain gain-controlled LNA and mixer for GNSS receivers Wei Binbin(魏斌斌)1, Jiang Jinguang(江金光)1,2,3*

A low power high gain gain-controlled LNA ＋ mixer for GNSS receivers is reported. The high gain LNA is realized with a current source load. Its gain-controlled ability is achieved using a programmable bias circuit. Taking advantage of the high gain LNA, a high noise figure passive mixer is adopted. With the passive mixer, low power consumption and high voltage gain of the LNA ＋ mixer are achieved. To fully investigate the performance of this circuit, comparisons between a conventional LNA ＋ mixer, a previous low power LNA ＋ mixer, and the proposed LNA ＋ mixer are presented. The circuit is implemented in 0.18 #m mixed-signal CMOS technology. A 3.8 dB noise figure, an overall 45 dB converge gain and a 10 dB controlled gain range of the two stages are measured. The chip occupies 0.24 mm2 and consumes 2 mA current under 1.8 V supply.     

一种应用于GPS接收机的高线性度SiGe HBT低噪声放大器

A high linearity 1.575 GHz SiGe：HBT low noise amplifier （LNA） for global positioning system applications is described. The bipolar cascoded with an MOSFET LNA was fabricated in a commercial 0.18 μm SiGe BiCMOS process, A resistor bias feed circuit with a feedback resistor was designed for the LNA input transistor to improve its intermodulation and compression performance. The packaged chip tested on board has displayed a noise figure of 1. I 1 dB, a power gain of 18 dB, an output 1 dB compression point of ＋7.8 dBm and an input third-order intercept point of ＋1.8 dBm. The chip occupies a 500 × 560μm^2 area and consumes 3.6 mA from a 2.85 V power supply.     

一种应用于GNSS接收机的低噪声和低杂散频率综合器

A low phase noise and low spur phase locked loop （PLL） frequency synthesizer for use in global navigation satellite system （GNSS） receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector （PFD） produces four control signals, which can reach the charge pump （CP） simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc.     

Secure Network Coding Based on Lattice Signature

To provide a high-security guaran- tee to network coding and lower the comput- ing complexity induced by signature scheme, we take full advantage of homomorphic prop- erty to build lattice signature schemes and sec- ure network coding algorithms. Firstly, by means of the distance between the message and its sig- nature in a lattice, we propose a Distance-bas- ed Secure Network Coding （DSNC） algorithm and stipulate its security to a new hard problem Fixed Length Vector Problem （FLVP）, which is harder than Shortest Vector Problem （SVP） on lattices. Secondly, considering the bound- ary on the distance between the message and its signature, we further propose an efficient Bo- undary-based Secure Network Coding （BSNC） algorithm to reduce the computing complexity induced by square calculation in DSNC. Sim- ulation results and security analysis show that the proposed signature schemes have stronger unforgeability due to the natural property of lattices than traditional Rivest-Shamir-Adleman （RSA）-based signature scheme. DSNC algo- rithm is more secure and BSNC algorithm greatly reduces the time cost on computation.     

用于U波段移动数字电视的宽带大动态范围高线性度射频前端

A wideband large dynamic range and high linearity U-band RF front-end for mobile DTV is introduced,and includes a noise-cancelling low-noise amplifier(LNA),an RF programmable gain amplifier(RFPGA) and a current communicating passive mixer.The noise/distortion cancelling structure and RC post-distortion compensation are employed to improve the linearity of the LNA.An RFPGA with five stages provides large dynamic range and fine gain resolution.A simple resistor voltage network in the passive mixer decreases the gate bias voltage of the mixing transistor,and optimum linearity and symmetrical mixing is obtained at the same time.The RF front-end is implemented in a 0.25 μm CMOS process.Tests show that it achieves an ⅡP3(third-order intercept point) of –17 dBm,a conversion gain of 39 dB,and a noise figure of 5.8 dB.The RFPGA achieves a dynamic range of –36.2 to 23.5 dB with a resolution of 0.32 dB.     

一种电流复用共栅低噪声放大器的低功耗433/915-MHz射频前端的设计

This paper presents a wideband RF front-end with novel current-reuse wide band low noise amplifier(LNA),current-reuse V –I converter,active double balanced mixer and transimpedance amplifier for short range device(SRD) applications.With the proposed current-reuse LNA,the DC consumption of the front-end reduces considerably while maintaining sufficient performance needed by SRD devices.The RF front-end was fabricated in 0.18 μm RFCMOS process and occupies a silicon area of just 0.11 mm2.Operating in 433 MHz band,the measurement results show the RF front-end achieves a conversion gain of 29.7 dB,a double side band noise figure of 9.7 dB,an input referenced third intercept point of –24.9 dBm with only 1.44 mA power consumption from 1.8 V supply.Compared to other reported front-ends,it has an advantage in power consumption.