High speed III-V electrooptic waveguide modulators at λ-1.3μm

Traveling wave GaAs electrooptic waveguide modulators at a wavelength of 1.3 μm with bandwidth in excess of 20 GHz have been developed and characterized. The design and characteristics of both p-i-n modulators in microstrip configuration and Schottky barrier on n ^--GaAs/semi-insulating (SI) GaAs in the coplanar strip configuration modulators are discussed. It is shown that microwave loss and slowing on n⁺ GaAs substrates will limit the bandwidth of the microstrip modulator to less than 10 GHz for a device 8 mm in length. Modulators with bandwidths in excess of 10 GHz are fabricated on SI GaAs substrates     

Effects of neutral buried p-layer on high-frequency performance ofGaAs MESFETs

Fully ion-implanted n⁺ self-aligned GaAs MESFETs with Au/WSiN refractory metal gates have been fabricated by adopting neutral buried p-layers formed by 50-keV Be-implantation. S-parameter measurements and equivalent circuit fittings are discussed. When the Be dose is increased from 2×10¹² cm^-2 to 4×10¹² cm^-2, the maximum value of the cutoff frequency with a 0.2-μm gate falls off from 108 to 78 GHz. This is because a neutral buried player makes the intrinsic gate-source capacitance increase markedly, while its influence on gate-drain capacitance and gate-source fringing capacitance is negligible. The maximum oscillation frequency recovers, however, due primarily to the drain conductance suppression by the higher-concentration buried p-layer. An equivalent value of over 130 GHz has been obtained for both 0.2-μm-gate GaAs MESFETs     

A monolithic gallium arsenide interval timer IC with integrated PLLclock synthesis having 500-ps single shot resolution

A gallium arsenide (GaAs) integrated circuit for measuring single shot time intervals with 500-ps resolution has been designed, fabricated, and tested. The circuit contains a 12-b counter that can be extended externally and control circuitry for the detection of multiple intervals. Options such as number of intervals, minimum interval time, and timing resolution are user programmable. The circuit employs a self-contained 2.0-GHz phase-locked loop (PLL) clock synthesizer with less than 5 ps rms jitter and a lock time of 2.5 μs. The circuit is packaged in a 14-mm², 52-pin thermally enhanced plastic package and operates from a single +5-V supply. The nominal power dissipation is 2.8 W. The circuit is fabricated in a 0.6-μm gate length, enhancement/depletion GaAs MESFET process utilizing four layers of gold interconnect metallization. Inductors, capacitors, and thin film resistors can be fabricated in this process, enabling integrated analog circuitry. The die size is 3.28 by 3.15 mm. The circuit has applications in collision avoidance sensors, laser rangefinders, surveying, police radar, and test instrumentation     

Monolithic integration of InGaAs p-i-n photodetector with fullion-implanted InP JFET amplifier

A monolithically integrated p-i-n FET amplifier, fabricated using ion-planted indium-phosphide (InP) JFETs, is described. The vertically integrated structure consists of a vapor-phase epitaxy (VPE)-grown InGaAs photoabsorption layer and a metal-organic-chemical-vapor-disposition (MOCVD)-grown Fe-doped semi-insulating layer. A Zn diffusion was performed to complete the p-i-n photodiode. High-performance fully implanted InP JFETS were used to form the integrated amplifier with a symmetrical design to remove the DC offset. With a receiver sensitivity of -36.4 dBm measured at 200 Mb/s NRZ for 10^-9 BER, it is thought to be the most sensitive monolithic p-i-n FET preamp yet reported in this frequency range. The p-i-n amplifier has a dynamic range of 15 dB     

Fully Integrated Broadband CPW Left-Handed Metamaterials Based on GaAs Technology for RF/MMIC Applications

A fully integrated broadband coplanar waveguide left-handed metamaterial medium using GaAs technology for radio frequency/monolithic microwave integrated circuit (RF/MMIC) applications is reported and validated by the full wave simulation and measured results. The unit cell of the fabricated structures has a size of 0.09 mm². The left handedness of the integrated left-handed structure extends from 2.3 to 17.5 GHz. The compactness and broad left-handed operating bandwidth make the presented left-handed metamaterial be well incorporated with RF/MMIC applications.     

Double-implanted GaAs complementary JFET's

The fabrication and performance characteristics of double-implanted GaAs complementary junction field-effect transistors (JFET's) suitable for low-power digital integrated circuit applications are described. Effective mobilities for the n-channel enhancement-mode JFET are 3500 cm²/V.s and for the p-channel 300 cm²/V.s. Experimental results of an ultra-low-power static RAM are presented.     

Analysis of CMOS-compatible lateral insulated base transistors

The authors describe the performance of various lateral insulated base transistors (LIBTs) fabricated with a 2.5-μm digital CMOS-compatible high-voltage integrated circuit (HVIC) process. Structural modifications have been proposed to the LIBTs reported to date, in order to improve their on-stage performance. The modifications have been achieved with the use of charge-controlled n⁺ buried layers incorporated within the device structures. These LIBTs are implemented with a novel HVIC process which is based on a 2.5-μm digital CMOS fabrication sequence. This process utilizes three additional steps carried out prior to the CMOS fabrication sequence. An important feature of this HVIC process is the use of a 400-Å gate oxide, which makes the power devices, fully compatible with the low-voltage digital circuits. During this work, a specific on-resistance of 0.016 Ω-cm² and a turn-off delay of 90 ns have been obtained in an improved LIBT structure which is capable of withstanding up to 250 V     

Characterization of double pulse-doped channel GaAs MESFETs

The fabrication and characterization of a double pulse-doped (DPD) GaAs MESFET grown by organometallic vapor phase epitaxy (OMVPE) are reported. The electron mobility of a DPD structure with a carrier concentration of 3×10¹⁸/cm³ was 2000 cm²/V-s, which is about 20% higher than that of a pulse-doped (PD) structure. Implementing the DPD structure instead of the conventional PD structure as a GaAs MESFET channel, the drain breakdown voltage, current gain cutoff frequency, and maximum stable gain (MSG) increase. The maximum transconductance of 265 mS/mm at a drain current density of 600 mA/mm, a current gain cutoff frequency of 40 GHz, and an MSG of 11 dB at 18 GHz were obtained for a 0.3 μm n⁺ self-aligned DPD GaAs MESFET     

New self-aligned T-gate InGaP/GaAs field-effect transistors grownby LP-MOCVD

This paper reports on self-aligned T-gate InGaP/GaAs FETs using n ⁺/N⁺/δ(P⁺)/n structures. N⁺ -InGaP/δ(P⁺)-InGaP/n-GaAs forms a planar-doped barrier. The inherent ohmic gate of camel-gate FETs together with a highly selective etch between an InGaP and a GaAs layers offers a self-aligned T-shape gate with a reduced effective length. A fabricated device with a reduced gate dimension of 1.5×100 (0.6×100) μm² obtained from 2×100 (1×100) μm² gate metal exhibits an extrinsic transconductance, unity-current gain frequency, and unity-power gain frequency of 78 (80) mS/mm, 9 (19.5), and 28 (30) GHz, respectively     

AlGaAs/GaAs heterojunction bipolar transistors fabricated using a self-aligned dual-lift-off process

This paper describes a self-aligned heterojunction-bipolar-transistor (HBT) process based on a simple dual-lift-off method. Transistors with emitter width down to 1.2 µm and base doping up to 1 × 10²⁰/cm³have been fabricated. Extrapolated current gain cutoff frequency ftof 55 GHz and maximum frequency of oscillationf_{max}of 105 GHz have been obtained. Current-mode-logic (CML) ring oscillators with propagation delays as low as 14.2 ps have been demonstrated. These are record performance results for bipolar transistors. The dual-lift-off process is promising for both millimeter-wave devices and large-scale integrated circuit fabrication.     

High-transconductance p-channel AlGaAs/GaAs HFETs with low-energyberyllium and fluorine co-implantation self-alignment

The fabrication and electrical characteristics of p-channel AlGaAs/GaAs heterostructure FETs with self-aligned p⁺ source-drain regions formed by low-energy co-implantation of Be and F are reported. The devices utilize a sidewall-assisted refractory gate process and are fabricated on an undoped AlGaAs/GaAs heterostructure grown by MOVPE. Compared with Be implantation alone, the co-implantation of F⁺ at 8 keV with 2×10¹⁴ ions/cm² results in a 3× increase in the post-anneal Be concentration near the surface for a Be⁺ implantation at 15 keV with 4×10¹⁴ ions/cm². Co-implantation permits a low source resistance to be obtained with shallow p⁺ source-drain regions. Although short-channel effects must be further reduced at small gate lengths, the electrical characteristics are otherwise excellent and show a 77-K transconductance as high as 207 mS/mm for a 0.5-μm gate length     

Numerical modeling of energy balance equations in quantum well AlxGa1-xAs/GaAs p-i-n photodiodes

The energy balance equations coupled with drift diffusion transport equations in heterojunction semiconductor devices are solved modeling hot electron effects in single quantum well p-i-n photodiodes. The transports across the heterojunction boundary and through quantum wells are modeled by thermionic emission theory. The simulation and experimental current-voltage characteristics of a single p-i-n GaAs/Al _xGa_1-xAs quantum well agree over a wide range of current and voltage, The GaAs/Al_xGa_1-xAs p-i-n structures with multi quantum wells are simulated and the dark current voltage characteristics, short circuit current, and open circuit voltage results are compared with the available experimental data, In agreement with the experimental data, simulated results show that by adding GaAs quantum wells to the conventional cell made of wider bandgap Al_x Ga_1-xAs, short circuit current is improved, but there is a loss of the voltage of the host cell, In the limit of radiative recombination, the maximum power point of an Al_0.35Ga_0.65As/GaAs p-i-n photodiode with 30-quantum-well periods is higher than the maximum power point of similar conventional bulk p-i-n cells made out of either host Al_0.35Ga_0.65As or bulk GaAs material     

LSI processing technology for planar GaAs integrated circuits

A planar GaAs integrated circuit (IC) fabrication technology capable of LSI complexity has been developed. The circuit and fabrication approaches were chosen to satisfy LSI requirements for high yield, high density, and low power. This technology utilizes Schottky-diode FET logic (SDFL) incorporating both high-speed switching diodes and 1-µ m GaAs MESFET's. Circuits are fabricated directly on semi-insulating GaAs using multiple localized implantations. Rapid progress in the development of this technology has already led to the successful demonstration of high-speed (tau_{d} sim 100ps) low-power (∼500 µW/gate) GaAs MSI (∼60-100 gates) circuits. Extension of the current MSI technology to the LSI/VLSI domain will depend critically on device yield which will be dictated by the GaAs material properties and by the fabrication processes used. The purpose of this paper is to describe a GaAs IC process technology which combines advanced planar device and multilevel interconnect structures with several LSI compatible processes including multiple localized ion implantations, reduction photolithography, plasma etching, reactive ion etching, and ion milling.     

All-GaAs/AlGaAs readout circuit for quantum-well infrared detectorfocal plane array

We report the fabrication and testing of an all-GaAs/AlGaAs hybrid readout circuit operating at 77 K designated for use with an GaAs/AlGaAs background-limited quantum-well infrared photodetector focal plane array (QWIP FPA). The circuit is based on a direct injection scheme, using specially designed cryogenic GaAs/AlGaAs MODFET's and a novel n⁺ -GaAs/AlGaAs/n⁺-GaAs semiconductor capacitor, which is able to store more than 15 000 electrons/μm² in a voltage range of ±0.7 V. The semiconductor capacitor shows little voltage dependence, small frequency dispersion, and no hysteresis. We have eliminated the problem of low-temperature degradation of the MODFET I-V characteristics and achieved very low gate leakage current of about 100 fA in the subthreshold regime. The MODFET electrical properties including input-referred noise voltage and subthreshold transconductance were thoroughly tested. Input-referred noise voltage as low as 0.5 μV/√Hz at 10 Hz was measured for a 2×30 μm² gate MODFET. We discuss further possibilities for monolithic integration of the developed devices     

A three mask bipolar integrated circuit structure

A new bipolar integrated circuit structure has been fabricated that compares favorably to the MOS structure in terms of fabrication simplicity and performance. The new structure is basically a modified isolated lateral transistor and requires only three photolithographic masking operations up to and including first level of metalization. The fabrication of the structure is as follows: a shallow nonselective p-type base region is diffused into a lightly doped p-type substrate; n⁺emitter and collector regions are then simultaneously and selectively diffused into and through the p-type base region thus forming a lateral n-p-n transistor. The second and third masks define the contact holes and the metalization pattern, respectively. Lateral isolation of the structure is obtained by encircling the emitter and base regions with the collector region. Vertical isolation is achieved by the large collector-depletion region that extends beneath the emitter and base regions. Since the substrate is lightly doped a low collector voltage will adequately isolate the emitter and base regions from adjacent devices. The new technology permits the fabrication of transistors, resistors, and crossunders. Transistors with 2-to 3-µm spacings occupy 500 µm²of silicon area and have the following characteristics:beta = 35, peakf_{t} = 0.1GHz at 0.5 mA, BV(SUSTAIN) = 3 to 5 V,t_{r} = 20ns,t_{f} = 120ns,t_{s} = 20ns. Resistors with values as high as 40 kΩ have been fabricated within 600 µm². Active nonlinear loads with effective resistance up to 200 kΩ have been fabricated. TTL gates have been made with power-delay products of 3.6 pJ, and propagation delays of 34 ns.     

Lateral tunneling transistors fabricated by plane-dependent Si-doping in nonplanar epitaxy on GaAs (311)A and (411)A substrates

We have demonstrated the lateral tunneling transistors on GaAs (311)A and (411)A patterned substrates by using the plane-dependent Si-doping technique. Lateral p⁺-n⁺ tunneling junctions are formed by growing heavily Si-doped layers on patterned substrates. Current—voltage curves for both transistors show gate-controlled negative differential resistance characteristics. Furthermore, the peak current density of the lateral tunneling diodes fabricated on the (311)A patterned substrates increases as buffer layer thickness is increased, and a typical peak current density of 58 A/cm² for p = 6 × 10¹⁹ cm⁻³ and n = 7 × 10¹⁸ cm⁻³ is obtained when the buffer layer thickness is 1.2 μm. This study shows that plane-dependent Si-doping in non-planar epitaxy is a promising technique for fabricating tunneling transistors.     

Optoelectronic characteristics of a-SiC:H-based P-I-N thin-filmlight-emitting diodes with low-resistance and high-reflectance N+-a-SiCGe:H layer

The graded-gap a-SiC:H-based p-i-n thin-film light-emitting diodes (TFLEDs) with an additional low-resistance and high-reflectance n⁺ -a-SiCGe:H layer were proposed and fabricated on indium-tin-oxide (ITO)-coated glass substrate in this paper. For a finished TFLED, a brightness of 720 cd/m² could be obtained at an injection current density of 600 mA/cm², and its EL (electroluminescence) threshold voltage was lowered to 8.6 V. In addition, the effects of reflectance and resistance of a-SiCGe:H film on the performance of TFLED were discussed. The optimum rapid thermal annealing (RTA) conditions for fabrication of TFLED after metallization were also studied and employed to improve the optoelectronic characteristics of TFLED     

Micromechanical accelerometer integrated with MOS detection circuitry

A cantilever beam accelerometer is described in which the small cantilever sensing element is integrated with and fabricated alongside MOS detection circuitry. The total area of the detector/circuit combination is about 15000 µm²(24 mil²). Fully compatible and conventional materials and processing steps are employed throughout the fabrication schedule. Accelerations of the chip normal to its surface induce motions in the cantilever beam. These motions result in capacitance variations which drive the simple MOS detection circuit. Sensitivities of about 2.2 mV/g of acceleration were measured, corresponding to beam motions of about 68 nm/g, with a beam mechanical resonant frequency of 2.2 kHz. These results were in close agreement with detailed mechanical calculations and circuit modeling.     

A low-noise K-Ka band oscillator AlGaAs/GaAsheterojunction bipolar transistors

The design considerations, fabrication process, and performance of the first K-Ka-band oscillator implemented using a self-aligned AlGaAs/GaAs heterojunction bipolar transistor (HBT) are described. A large-signal time-domain-based design approach has been used which applies a SPICE-F simulator for optimization of the oscillator circuit parameters for maximum output power. The oscillator employs a 2×10-μm² emitter AlGaAs/GaAs HBT that was fabricated using a pattern inversion technology. The HBT has a base current 1/f noise power density lower than 1×10^-20 A²/Hz at 1 kHz and lower than 1×10^-22 A/²/Hz at 100 kHz for a collector current of 1 mA. The oscillator, which is composed of only low-Q microstrip transmission lines, has a phase noise of -80 dBc/Hz at 100 kHz off carrier when operated at 26.6 GHz. These results indicate the applicability of the HBTs to low-phase-noise monolithic oscillators at microwave and millimeter-wave frequencies, where both Si bipolar transistors and GaAs FETs are absent     

Compensation-circuit to improve radiation-hardness in GaAsdigital-circuits, based on X-ray studies

Earlier results have shown that GaAs devices do not exhibit appreciable degradation up to a radiation dose of nearly 10⁸ rad (GaAs). The results of this work suggest that GaAs devices and circuits are sensitive to radiation exposure at dose levels below 10⁸ rad(GaAs). Degradation was observed in E-MESFET and D-MESFET parameters and in circuit performance for devices which were designed and fabricated in a 1.2 μm GaAs process, when exposed to varying doses of 1.49 keV X-rays in the range 40-65 Mrad (GaAs). The degradation is attributed to the change in the properties of the MESFET channel region, caused by the transport of the atomic hydrogen from the passivation layer to the channel. A compensation circuit, based on the observed behavior of radiation effects on GaAs devices, has been designed to improve the radiation insensitivity of GaAs (E/D) based circuits under SPICE (Simulation Program with IC Emphasis) simulated conditions. Its usefulness is demonstrated through a DCFL inverter circuit up to nearly 10⁸ rad (GaAs) dose level. The results of this work can be used in the design of complex-function radiation-insensitive DCFL based circuits