Characterization of particle swarm optimization with diversive curiosity

For obtaining superior search performance in particle swarm optimization (PSO), we proposed particle swarm optimization with diversive curiosity (PSO/DC). The mechanism of diversive curiosity in PSO can prevent premature convergence and ensure exploration. To clarify the characteristics of PSO/DC, we estimated the range for appropriate parameter values, and investigated the trade-off between exploration and exploitation. Applications of the proposed method to a two-dimensional multimodal optimization problem and a suite of five-dimensional benchmark problems well demonstrate its effectiveness. Our experimental results basically accord with the findings in psychology, i.e., diversive curiosity being prone to exploration and anxiety.

High performance motion detection: some trends toward new embedded architectures for vision systems

The goal of this article is to compare some optimised implementations on current high performance platforms in order to highlight architectural trends in the field of embedded architectures and to get an estimation of what should be the components of a next generation vision system. We present some implementations of robust motion detection algorithms on three architectures: a general purpose RISC processor—the PowerPC G4—a parallel artificial retina dedicated to low level image processing—Pvlsar34—and the Associative Mesh, a specialized architecture based on associative net. To handle the different aspects and constraints of embedded systems, execution time and power consumption of these architectures are compared.

CTL* model checking on a shared-memory architecture

In this article we present the parallelisation of an explicit-state CTL^* model checking algorithm for a virtual shared-memory high-performance parallel machine architecture. The algorithm uses a combination of private and shared data structures for implicit and dynamic load balancing with minimal synchronisation overhead. The performance of the algorithm and the impact that different design decisions have on the performance are analysed using both mathematical cost models and experimental results. The analysis shows not only the practicality and effective speedup of the algorithm, but also the main pitfalls of parallelising model checking for shared-memory architectures.

Legal safeguards for privacy and data protection in ambient intelligence

To get the maximum benefit from ambient intelligence (AmI), we need to anticipate and react to possible drawbacks and threats emerging from the new technologies in order to devise appropriate safeguards. The SWAMI project took a precautionary approach in its exploration of the privacy risks in AmI and sought ways to reduce them. It constructed four “dark scenarios” showing possible negative implications of AmI, notably for privacy protection. Legal analysis of the depicted futures showed the shortcomings of the current legal framework in being able to provide adequate privacy protection in the AmI environment. In this paper, the authors, building upon their involvement in SWAMI research as well as the further advancement of EU privacy analysis, identify various outstanding issues regarding the legal framework that still need to be resolved in order to deal with AmI in an equitable and efficacious way. This article points out some of the lacunae in the legal framework and postulates several privacy-specific safeguards aimed at overcoming them.

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Designing a novel high-performance FPGA architecture for data intensive applications

A wide variety of real-time applications (e.g. multimedia, communication, etc.) require implementations that meet tight timing constraints. This work introduces novel high-performance FPGA architecture capable of implementing efficiently any time critical application. The fundamental contribution of the proposed reconfigurable architecture is the design of a highly efficient (performance and power consumption) interconnection structure, taking into consideration the statistical and spatial data extracted from applications, which are implemented on Virtex FPGAs. The derived architecture is software-supported by the MEANDER design framework. Using a number of real-time applications, extensive comparison study in terms of several design parameters proves the effectiveness of the proposed architecture against to Virtex one. More specifically, the proposed architecture achieves performance improvement and power savings up to 20 and 16%, respectively. Moreover, compared to a Virtex architecture with same power budget, our architecture achieves performance improvement by 42%.

A time-predictable VLIW processor and its compiler support

Time predictability is an important requirement for real-time embedded application domains such as automotive, air transportation, and multimedia processing. However, the architectural design of modern microprocessors mainly concentrates on improving the average-case performance, which can significantly compromise the time predictability and can make accurate worst-case performance analysis extremely difficult if not impossible. This paper studies the time predictability of VLIW (Very Long Instruction Word) processors and its compiler support. We analyze the impediments to time predictability for VLIW processors and propose compiler-based techniques to address these problems with minimal disturbance on the VLIW hardware design. The VLIW compiler is enhanced to support full if conversion, hyperblock scheduling, and intra-block nop insertion to enable efficient WCET (Worst Case Execution Time) analysis for VLIW processors. Our experiments indicate that the time-predictability of VLIW processor can be improved significantly.

Empirical analysis on the correlation between GCC compiler warnings and revision numbers of source files in five industrial software projects

This article discusses whether using warnings generated by the GNU C++ compiler can be used effectively to identify source code files that are likely to be error prone. We analyze five industrial projects written in C++ and belonging to the telecommunication domain. We find a significant positive correlation between the number of compiler warnings and the number of source files changes. We use such correlation to conclude that compiler warnings may be used as an indicator for the presence of software defects in source code. The result of this research is useful for finding defect-prone modules in newer projects, which lack change history.

On-line and post-processing timestamp correspondence for free-running clock nodes,using a network clock

Timestamp conversion is an important consideration in the deployment of distributed architectures. In this article we propose a precise, low-cost solution for on-line and post-processing timestamp conversion in distributed architectures, robust as regards the plugging and unplugging of hardware and the addition of new nodes (that is to say the different pieces of hardware connected to the network), not synchronized, and with no negative impact on the conversion quality. Each node (e.g., a computer) has at least one free-running clock. This clock’s time is the reference for all events used by the node. When the local node needs to record the time of an event timestamped by a remote node, the time is converted from the remote node’s time to the local node’s time. Interval timestamping is used, to take account of time imperfections (e.g. sensor and computer latencies, or due to time conversion between the different computers). A network clock is used, enabling a precise conversion and avoiding exchanges of messages for the conversion of clock correspondences. Moreover, it allows an unlimited number of nodes in the network.

Model-based mapping of reconfigurable image registration on FPGA platforms

Image registration is a computationally intensive application in the medical imaging domain that places stringent requirements on performance and memory management efficiency. This paper develops techniques for mapping rigid image registration applications onto configurable hardware under real-time performance constraints. Building on the framework of homogeneous parameterized dataflow, which provides an effective formal model of design and analysis of hardware and software for signal processing applications, we develop novel methods for representing and exploring the hardware design space when mapping image registration algorithms onto configurable hardware. Our techniques result in an efficient framework for trading off performance and configurable hardware resource usage based on the constraints of a given application. Based on trends that we have observed when applying these techniques, we also present a novel architecture that enables dynamically-reconfigurable image registration. This proposed architecture has the ability to tune its parallel processing structure adaptively based on relevant characteristics of the input images.

ARIS Method Extension for Business-Driven SOA

Service-oriented architecture (SOA) promises making companies more flexible enabling them to react quickly to changing market conditions. To leverage those advantages, SOA must be integrated with other existing approaches like business process management and enterprise architecture management. The authors describe how they extended the enterprise architecture management and business process management modelling method ARIS. They first created a SOA meta model by abstracting from existing modelling methods as well as extracting expert knowledge through interviews. In a second step, they mapped the SOA meta model to ARIS to provide a concrete modelling language for service-oriented enterprises. The ARIS extension allows describing and governing service architectures, describing services, linking service development initiatives to projects and company strategy, and discovering services for business process automation.

Mixed architectures for H.264/AVC digital video transrating

In this paper, we investigate transrating architectures for H.264/AVC video streams. Basic architectures are presented with their strengths and weaknesses. None of the existing architectures provide an appropriate solution for H.264/AVC transrating with an optimal balance between visual quality and complexity. In order to find such an appropriate solution, we propose the use of mixed transrating architectures. These architectures combine different transrating techniques which are applied depending on the picture/macroblock type. The intra-predicted pictures are decoded and re-encoded, while open-loop transrating or transrating with compensation is applied to motion-compensated pictures. Performance results show that the mixed architecture which applies spatial compensation to motion-compensated pictures gives rate-distortion results which approach the cascade of decoder and re-encoder with a complexity only slightly higher than the open-loop transrater. Adding temporal compensation for motion-compensated pictures further improves the visual quality, albeit to a lower extent, at the expense of increased complexity.

Adaptive real-time image processing exploiting two dimensional reconfigurable architecture

Fine grained reconfigurable architectures, like Xilinx field programmable gate arrays (FPGAs) provide a high flexibility through runtime re-programming, called dynamic and partial reconfiguration. This feature allows for runtime adaptation of the system architecture and behavior configured on the FPGA. The exploitation of this feature enables to load video image processing algorithms on-demand in order to adapt the configuration in correspondence to the changing requirements of the application depending on the image content. For high resolution sensor images, this novel computing paradigm can provide a huge benefit in power reduction and performance gain for actual and future embedded electronic systems. This paper presents a two dimensional system approach exploiting dynamic and partial reconfiguration in order to adapt the system architecture to the actual requirements of image processing applications. The methodology of runtime reconfiguration can be exploited beneficially for highly adaptive multiprocessor systems. Such systems, different from the traditional static approach for multi- and many-core architectures have the advantage, for providing computational performance directly linked to the requirements of the application. The architecture presented in this paper allows for adapting the processing elements as well as the communication infrastructure which is a novel 2D switch-based Network-on-Chip. The presented approach follows and extends the actual trend in computer science of using many- and multi-core processors for bridging the gap between required computation performance for future application in the field of image processing.

Profile-based dynamic pipeline scaling

Low power has played an increasingly important role for embedded systems. To save power, lowering voltage and frequency is very straightforward and effective; therefore, dynamic voltage scaling (DVS) has become a prevalent low-power technique. However, DVS makes no effect on power saving when the voltage reaches a lower bound. Fortunately, a technique called dynamic pipeline scaling (DPS) can overcome this limitation by switching pipeline modes at low-voltage level. Approaches proposed in previous work on DPS were based on hardware support. From viewpoint of compiler, little has been addressed on this issue. This paper presents a DPS optimization technique at compiler time to reduce power dissipation. The useful information of an application is exploited to devise an analytical model to assess the cost of enabling DPS mechanism. As a consequence, we can determine the switching timing between pipeline modes at compiler time without causing significant run-time overhead. The experimental result shows that our approach is effective in reducing energy consumption.

Architecture of an application-specific processor for real-time implementation of H.264/AVC sub-pixel interpolation

This paper presents an efficient VLSI architecture for fast implementation of sub-pixel interpolation of H.264/AVC. Several optimization techniques at different design levels, such as parallel processing, vector register, pipeline architecture, and in-place computation, are utilized to reduce the number of memory access and accelerate the interpolation computations. The proposed application-specific processor can meet the real-time constraint of the sub-pixel interpolation algorithm for the 16:9 video format (4,690 × 2,304) at 30 frames per second (fps) at 100 MHz clock rate.

Defect-Tolerance in Cellular Nanocomputers

For the manufacturing of computers built by nanotechnology, defects are expected to be a major problem. This paper explores this issue for nanocomputers based on cellular automata. Known for their regular structure, such architectures promise cost-effective manufacturing based on molecular self-organization. We show how a cellular automaton can detect defects in a self-contained way, and how it configures circuits on its cells while avoiding the defects. The employed cellular automaton is asynchronous, i.e., it does not require a central clock to synchronize the updates of its cells. This mode of timing is especially suitable for the high integration densities of nanotechnology implementations, since it potentially causes less heat dissipation.

PECOLE: P2P multimedia collaborative environment

PECOLE (Peer-to-pEer COLlaborative Environment) is a fully decentralized multimedia collaborative environment that supports a wide range of collaborative multimedia applications, including chat, shared browsing, shared telepointer, multipoint-to-multipoint audio/video conferencing and multilingual collaboration. PECOLE can intelligently run on very constrained resources, is highly resilient, scalable and does not rely on dedicated servers. Instead, PECOLE is built upon a Peer-to-Peer (P2P) overlay network, using SUN’s JXTA framework and SWT technology. In this paper, we present the architecture and implementation of PECOLE with the performance results of the tests we conducted.

Model-based control architecture for attentive robots in rescue scenarios

In this paper we present a control architecture for an autonomous rescue robot specialized in victim finding in an unknown and unstructured environment. The reference domain for rescue robots is the rescue-world arenas purposefully arranged for the Robocup competitions. The main task of a rescue mobile robot is to explore the environment and report to the rescue-operators the map of visited areas annotated with its finding. In this context all the attentional activities play a major role in decision processes: salient elements in the environment yield utilities and objectives. A model-based executive controller is proposed to coordinate, integrate, and monitor the distributed decisions and initiatives emerging from the modules involved in the control loop. We show how this architecture integrates the reactive model-based control of a rescue mission, with an attentive perceptual activity processing the sensor and visual stimuli. The architecture has been implemented and tested in real-world experiments by comparing the performances of metric exploration and attentive exploration. The results obtained demonstrate that the attentive behavior significantly focus the exploration time in salient areas enhancing the overall victim finding effectiveness.

Designing a smart-card-based face verification system: empirical investigation

To design a smart card face verification system many key factors have to be considered. In this study we discuss the implementation of such a system and investigate the trade-off between performance and computational complexity. Two optimisation strategies are considered. The studies are performed on the XM2VTS, BANCA and FERET databases demonstrating that the judicial choice of spatial and grey level resolution as well as JPEG compression settings for face representation can optimise verification error. We show that the use of a fixed precision data type does not affect system performance very much but can speed up the verification process. Since the optimisation framework of such a system is very complicated, the search space is simplified by applying some heuristics to the problem. In the adopted suboptimal search strategy one or two parameters are optimised at a time. The system was evaluated using half total error rate (HTER) as the performance criterion. The conclusions reached on different databases indicate that the selection of the optimum parameters may call for different optimum operating points.