互连铝通孔电迁移特征及其可靠性研究

研究了超大规模集成电路铝互连系统中铝通孔的电迁移失效机理及其可靠性寿命评价技术.试验采用CMOS和BiCMOS两种工艺各3组的铝通孔样品,分别在三个温度、恒定电流的加速条件下试验,以通孔开路为电迁移失效判据,最后得到了在加速条件下互连铝通孔的电迁移寿命,其结果符合标准的威布尔分布,试验准确可行.通过电迁移模型对试验数据进行了拟合,得到了激活能、电流加速因子和温度加速因子,计算出了正常工作条件下通孔电迁移的寿命,完成了对铝通孔电迁移的研究和寿命评价.     

阵列化互连LED模组寿命分布的蒙特卡洛模拟

利用蒙特卡洛方法对阵列化互连LED模组的可靠寿命进行了模拟,假设分档后的大功率白光LED的正向电压符合正态分布,额定电流下的寿命符合对数正态分布,且寿命和电流、温度的关系符合Eying模型,研究了n×n(6≤n≤12)LED阵列的寿命分布.模拟结果表明,对于n×n LED阵列,寿命随LED数目的增加没有下降反而略有增加...     

Circuit level interconnect reliability study using 3D circuit model

Integrated circuit (IC) reliability is gaining increasing concerns in IC technology with decreasing device size, and the impact of interconnect failure mechanisms on IC failure rate increases significantly with decreasing interconnect dimension and increasing number of interconnect levels. In this work, we attempt a first step in the study of interconnect electromigration reliability in integrated circuit using a complete 3D circuit model. 3D circuit model is necessary because all integrated circuits are 3D in their actual physical implementation, and 3D model is essential for the study of today interconnect reliability. As temperature and stress distributions in the interconnect are crucial to its reliability, we demonstrate our method through the computation of their distributions in a simple inverter circuit under typical normal operating condition, and the locations of the electromigration weak spots in the interconnect system are identified.     

Interconnect Reliability Analysis for Power Amplifier Based on Artificial Neural Networks

In order to learn the interconnect reliability of the complicated integrated circuit, a power amplifier 3D model is constructed and analyzed. The modeling and computation are completely automatic using the APDL. In order to predict the interconnect reliability of the power amplifier for the given design index effectively, the artificial neural networks model is used, then the prediction can be done fast. Training the simulation data from ANSYS, the neural network is used to model the relationship between the input and output. Then, a reliability database can be obtained which can help the designer to get the reliability performance of any design solution and the tradeoff decisions on the transistor’s size and the operation condition.     

Self-consistent design issues for high frequency Cu interconnect reliability incorporating skin effect

This paper presents a self-consistent method to guide high frequency reliability design for a two-level Cu interconnect structure, incorporating the impact of skin effect. A skin-effect-related parameter “Effective Cross Section Area” is introduced to make a more precise prediction of interconnects’ thermal profile due to self-heating. Since via and contact interfaces in Cu interconnects are at the highest risk of failure, via temperature is used to calculate the interconnect stress evolution and lifetime. From the research of the interconnect structure stressed by a type of arbitrary rectangular alternating current, we notice that the direction of the average current must be taken into account, while that consideration is not involved in self-consistent design for Al interconnects. We also found that generally, temperature, current density/intensity, frequency, and duty cycle are four specifications that restrict one another in high frequency interconnect reliability design, and if one increases, interconnects’ tolerance of the other three will decrease.     

Circuit sensitivity to interconnect variation

Deep submicron technology makes interconnect one of the main factors determining the circuit performance. Previous work shows that interconnect parameters exhibit a significant amount of spatial variation. In this work, we develop approaches to study the influence of the interconnect variation on circuit performance and to evaluate the circuit sensitivity to interconnect parameters. First, an accurate interconnect modeling technique is presented, and an interconnect model library is developed. Then, we explore an approach using parameterized interconnect models to study circuit sensitivity via a ring oscillator circuit. Finally, we present an alternative approach using statistical experimental design techniques to study the sensitivity of a large and complicated circuit to interconnect variations     

Reliability computer-aided design tool for full-chip electromigration analysis and comparison with different interconnect metallizations

We have developed a set of methodologies for thermal aware circuit-level reliability analysis with either Al or Cu metallization in a circuit layout and implemented it in a public domain reliability CAD tool, SysRel. SysRel utilizes a hierarchical reliability analysis flow, with interconnect trees treated as the fundamental reliability unit, that sufficiently captures the differences in electromigration failure between Al and Cu metallizations. Under similar test conditions, the electromigration reliability of Al and Cu interconnect trees demonstrates significant differences because of the differences in interconnect architectural schemes. Using the best estimates of material parameters and an analytical model, we present a detail comparison of electromigration reliability of a sample test-structure as well as of actual circuit layouts with Al and Cu dual-damascene interconnect systems. We also demonstrate fast thermal-analysis in SysRel for circuit performance driven chip-level reliability assessment.     

Reliability design of current stress in LSI interconnects using the estimation of failure rate due to electromigration

A method for the flexible and systematic design of the current stress level is proposed to assure reliability concerning electromigration open failure in aluminum interconnects of LSI. The proposed design rule can satisfy reliability requirements without excess restrictions on LSI performance. The required reliability is quantitatively defined using the failure rate and lifetime. The requirements for interconnects are hierarchically decided from LSI reliability design.The equation used in the design is induced using the acceleration factor of the testing condition to the operating condition considering the statistical difference between a test sample and an LSI, and consists of three terms corresponding to reliability requirements, parameters of circuit design and the EM failure resistance of the interconnect technology used.The interconnects in an LSI are classified into those for power use and those for signal use. The solution for each use is represented using a map that follows allowable areas of design parameters. The map makes it easy to change the designed parameters for the purpose of high performance within the reliability requirement limit.The error of the reliability estimation is analyzed as a function of the parameters used in the equations. To avoid optimistic estimations, a safety factor is introduced in relation to the standard deviation of the error.     

Statistical lifetime reliability optimization considering joint effect of process variation and aging

Aging effect degrades circuit performance in the runtime, interacts with fabrication-induced device parameter variation, and thus posing significant impact on circuit lifetime reliability. In this work, a statistical circuit optimization flow is proposed to ensure lifetime reliability of the manufactured chip in the presence of process variation and aging effects. It exploits a variation-aware gate-level statistical aging degradation model to characterize circuit lifetime reliability, identifies a set of worst duty cycles on the inputs of statistically critical gates to estimate the worst delay degradations on these gates. Based on the delay degradation information, statistical gate sizing is performed which enables the manufactured chip to satisfy lifetime reliability constraint in term of low area overhead.     

Numerical analysis on compliance and electrical behavior of multi-copper-column flip-chip interconnects for wafer-level packaging

This paper presents modeling and simulation results of a modified copper-column-based flip-chip interconnect with ultrafine pitch for wafer-level packaging, and the process and prototyping procedure are described as well. This interconnect consists of multiple copper columns which are electrically in parallel and supporting a solder bump. A simple analytical model has been developed for correlation between the interconnect geometry and the thermal fatigue life. In comparison to the conventional single-copper-column (SCC) interconnects, numerical analysis reveals that the multi-copper-column (MCC) interconnect features enhanced compliances and, hence, higher thermomechanical reliability, while the associated electrical parasitics (R, L, and C) at dc and moderate frequencies are still kept low. Parametric studies reveal the effects of geometric parameters of MCC interconnects on both compliances and electrical parasitics, which in turn facilitate design optimization for best performance. By using coplanar waveguides (CPWs) as feed lines on both chip and package substrate, a high-frequency (up to 40 GHz) S-parameter analysis is conducted to investigate the transmission characteristics of the MCC interconnects within various scenarios which combines various interconnect pitches and common chip and package substrates. An equivalent lumped circuit model is proposed and the circuit parameters (R, L, C, and G) are obtained throughout a broad frequency range. Good agreement is achieved for the transmission characteristics between the equivalent lumped circuit model and direct simulation results.     

基于40nm CMOS工艺电路的NBTI退化表征方法

负偏压温度不稳定性(NBTI)退化是制约纳米级集成电路性能及寿命的主导因素之一,基于40 nm CMOS工艺对NBTI模型、模型提参及可靠性仿真展开研究。首先对不同应力条件下PMOS晶体管NBTI退化特性进行测试、建模及模型参数提取,然后建立了基于NBTI效应的VerilogA等效受控电压源,并嵌入Spectre^TM仿真库中,并将此受控电压源引入反相器及环形振荡器模块电路中进行可靠性仿真分析,可有效反映NBTI退化对电路性能的影响。提出了一套完整可行的电路NBTI可靠性预测方法,包括NBTI模型、模型参数提取、VerilogA可靠性模型描述以及电路级可靠性仿真分析,可为纳米级高性能、高可靠性集成电路设计提供有效参考。     

A Method for Predicting VLSI-Device Reliability Using Series Models for Failure Mechanisms

A series model is used to determine the intrinsic reliability of an integrated circuit. An analysis of electromigration in the interconnect system of a 200 000 transistor VLSI device, shows that the failure rate exceeds 10 FIT (failures per 109 hours) within 2 years when operating at a temperature of 800 C. These results indicate the importance of fundamental wear-out mechanisms as factors in VLSI device reliability, under usual operating conditions. The analysis, as applied to a generic chip, predicts that temperature, burn-in, and complexity all adversely affect the device reliability. The paper demonstrates the feasibility of using the information available in the design database together with specific failure models to predict (during the design phase) the reliability of an IC. These techniques can be used to develop a CAD tool for reliability prediction.     

Effect of IC layout on the reliability of CMOS amplifiers

With shrinking device size and increasing circuit complexity, interconnect reliability has become the main factor that affects the integrated circuit (IC) reliability. Electromigration (EM) is the major failure mechanism for interconnect reliability. However, little research had been done on the effect of IC layout on the void nucleation time (i.e. the time where the vacancies in the metal gather and nucleate into a tiny void) in the interconnections of the circuits due to electromigration using 3D modeling. In this paper, we construct the 3D models for a CMOS class-AB amplifier and a RF low noise amplifier (LNA), and investigate the impact of layout design on the void nucleation time through the computation of the atomic flux divergence (AFD) of the 3D circuit models. From the simulation results we find that, there is a change in the value of the maximum total AFD with the change in the number of contacts or the inter-transistor distance. A change in the location of the maximum total AFD is observed in the LNA circuit with different finger number as a result of the change in the line width and the transistor rotation. This indicates a different reliability lifetime and void formation location with different layout designs.     

Electromigration challenges for advanced on-chip Cu interconnects

As technology scales down, the gap between what circuit design needs and what technology allows is rapidly widening for maximum allowed current density in interconnects. This is the so-called EM crisis. This paper reviews the precautions and measures taken by the interconnect process development, circuit design and chip integration to overcome this challenge. While innovative process integration schemes, especially direct and indirect Cu/cap interface engineering, have proven effective to suppress Cu diffusion and enhance the EM performance, the strategies for circuit/chip designs to take advantage of specific layout and EM failure characteristics are equally important to ensure overall EM reliability and optimized performance. To enable future technology scaling, a co-optimization approach is essential including interconnect process development, circuit design and chip integration.     

Multi-Mechanism Reliability Modeling and Management in Dynamic Systems

Reliability failure mechanisms, such as time-dependent dielectric breakdown (TDDB), electromigration, and negative bias temperature instability (NBTI), have become a key concern in integrated circuit (IC) design. The traditional approach to reliability qualification assumes that the system will operate at maximum performance continuously under worst case voltage and temperature conditions. In reality, due to widely varying environmental conditions and an increased use of dynamic control techniques, such as dynamic voltage scaling and sleep modes, the typical system spends a very small fraction of its operational time at maximum voltage and temperature. In this paper, we show how this results in a reliability ";slack"; that can be leveraged to provide increased performance during periods of peak processing demand. We develop a novel, real time reliability model based on workload driven conditions. Based on this model, we then propose a new dynamic reliability management (DRM) scheme that results in 20%-35 % performance improvement during periods of peak computational demand while ensuring the required reliability lifetime.     

LTCC微波多芯片组件中键合互连的微波特性

键合互连是实现微波多芯片组件电气互连的关键技术,键合互连的拱高、跨距和金丝根数对其微波特性具有很大的影响。本文采用商用三维电磁场软件HFSS和微波电路设计软件ADS对低温共烧陶瓷微波多芯片组件中键合互连的微波特性进行建模分析和仿真优化。仿真优化结果与LTCC试验样品的测试结果吻合较好。     

Study of swing potential on deep submicron on-chip interconnect

The low energy limit of signal on deep submicron on-chip interconnect is deduced from Shannon's communication theorem considering the influence of noise. Based on this energy limit, the analytic model of minimum swing potential considering transmission line effects is constructed. Applying the analytic model to interconnect in deep submicron technology nodes from 0.18 to 0.05 μm, it is shown that the swing potential with present low-swing technique such as SDVST could be reduced further by 70–95% according to the analysis of this work. Correspondingly, by using the low-swing interconnect technique with the minimum swing potential obtained in this work, the decrement of interconnect dynamic power dissipation can be further decreased by about 10–20% of their original one by using SDVST technique, and that of interconnect propagation delay, by one third. Furthermore, the maximum interconnect length is evaluated with a minimum swing potential value in interconnect design. All the results are valuable for interconnect performance optimization, such as repeater insertion in deep submicron circuits. As an application, the design of low swing potential interconnect with interface circuit is introduced.     

Modeling the effect of barrier thickness and low-k dielectric on circuit reliability using 3D model

The continuous scaling down of the device size and escalating circuit speed drives the requirement for EM-resistant Cu interconnect with diffusion barrier and the low-k dielectric. The study of barrier layer thickness and low-k dielectric effect in a complete 3D circuit is necessary as the actual physical implementation of an integrated circuit in a wafer is indeed 3D in nature. This paper investigates the effect of barrier layer thickness and low-k dielectric on the circuit reliability of a complete 3D circuit model. It was found that the maximum atomic flux divergence (AFD) value increases with decreasing barrier layer thickness, which implied a shorter EM lifetime with thinner barrier. Low-k dielectric will give a higher maximum AFD due to higher stress gradient, and thus a shorter EM lifetime.     

An effective thermal circuit model for electro-thermal simulation of SOI analog circuits

A physics-based thermal circuit model is developed for electro-thermal simulation of SOI analog circuits. The circuit model integrates a non-isothermal device thermal circuit with interconnect thermal networks and is validated with high accuracy against finite element simulations in different layout structures. The non-isothermal circuit model is implemented in BSIMSOI to account for self-heating effect (SHE) in a Spice simulator, and applied to electro-thermal simulation of an SOI cascode current mirror constructed using different layouts. Effects of layout design on electric and thermal behaviors are investigated in detail. Influences of BOX thickness are also examined. It has been shown that the proposed non-isothermal approach is able to effectively account for influences of layout design, self-heating, high temperature gradients along the islands, interconnect temperature distributions, thermal coupling, and heat losses via BOX and interconnects, etc., in SOI current mirror structures. The model provides basic concepts and thermal circuits that can be extended to develop an effective model for electro-thermal simulation of SOI analog ICs.     

Global (interconnect) warming

This article presents a comprehensive analysis of the thermal effects in advanced high-performance VLSI interconnect systems arising due to self-heating under various circuit conditions, including electrostatic discharge (ESD). Technology (Cu, low-k, etc.) and scaling effects on the thermal characteristics of the interconnects, and on their electromigration (EM) reliability, have been analyzed simultaneously, which have important implications for providing robust and aggressive deep sub-micron (DSM) interconnect design guidelines. The analysis takes into account the effects of increasing interconnect (Cu) resistivity with decreasing line dimensions and the effect of a finite barrier metal thickness. Furthermore, the impact of these thermal effects on the design (driver sizing) and optimization of the interconnect length between repeaters at the global-tier signal lines are investigated. Finally, the reliability implications for minimum-sized vias in optimally buffered signal nets will also be quantified