Hot-electron currents in very short channel MOSFET's

The behaviors of the hot-electron gate and substrate currents in very short channel devices were studied. For a test device with electrical channel length of 0.14 µm, the hot-electron substrate current can be detected at 0.9-V drain voltage which is lower than the silicon band gap. The gate current can be measured at 2.35-V drain voltage, which is lower than the oxide-silicon energy barrier for electrons. These measurements support the quasi-thermal-equilibrium approximation and suggest that the hot-electron-induced problems cannot be eliminated in future VLSI MOSFET's of arbitrarily short channels by reducing the drain bias below some constant critical energies. An empirical relationship between the effective electron temperature and the field is found to be Te= 9.05 × 10^-3E.     

New experimental findings on hot carrier effects in sub-0.1 μmMOSFET's

The behaviors of the substrate current and the impact ionization rate are investigated for deep submicron devices in a wide temperature range. New important features are shown for the variations of the maximum substrate current as a function of applied biases and temperature. It is found that the gate voltage V_gmax, corresponding to the maximum impact ionization current conditions, is quasi-constant as a Function of the drain bias for sub-0.1 μm MOSFET's in the room temperature range. At low temperature, a substantial increase of V_gmax is observed when the drain voltage is reduced. It is also shown that, although a significant enhancement of hot carrier effects is observed by scaling down the devices, a strong reduction of the impact ionization rate is obtained for sub-0.1 μm MOSFET's operated at liquid nitrogen temperature in the low drain voltage range     

A pseudo-lucky electron model for simulation of electron gatecurrent in submicron NMOSFET's

An energy parameterized pseudo-lucky electron model for simulation of gate current in submicron MOSFET's is presented in this paper. The model uses hydrodynamic equations to describe more correctly the carrier energy dependence of the gate injection phenomenon. The proposed model is based on the exponential form of the conventional lucky electron gate current model. Unlike the conventional lucky electron model, which is based on the local electric fields in the device, the proposed model accounts for nonlocal effects resulting from the large variations in the electric field in submicron MOSFET's. This is achieved by formulating the lucky electron model in terms of an effective-electric field that is obtained by using the computed average carrier energy in the device and the energy versus field relation obtained from uniform-field Monte Carlo simulations. Good agreement with gate currents over a wide range of bias conditions for three sets of devices is demonstrated     

Observation of hot-hole injection in NMOS transistors using a modified floating-gate technique

A modified floating-gate technique for measuring small gate currents in MOSFET's with very high resolution (0.01 fA) is described. Using this technique, gate oxide currents due to hot-carrier injection are measured in n-channel MOSFET's. The conventional negative channel hot-electron gate oxide current is observed nearV_{g} = V_{d}and a small positive gate current occurs at low Vg. We argue that the dependencies of this small positive current on Vgand gate length, together with results from a separate floating-source experiment, are consistent only with hot-hole injection.     

Effects of ionizing radiation on n-channel MOSFET's fabricated in zone-melting-recrystallized Si films on SiO2

We have investigated the effects of irradiation with 1.5 MeV electrons on the electrical characteristics of n-channel MOSFET's fabricated in zone-melting-recrystallized Si films on SiO2-coated Si substrates. With a -15 V bias applied to the Si substrate during irradiation and device operation, the subthreshold leakage current remains below 0.2 pA/µm (channel width) for ionizing doses up to 10⁶rad(Si). The negative substrate bias also reduces the shift of threshold voltage to less than 0.3 V for devices with 50 nm-thick gate oxide.     

A self-consistent pseudo-two-dimensional model for hot-electron current in MOST' s

A theoretical formulation for the hot-electron currents (substrate and gate currents) in MOST's with nonuniform impurity profile has been built. By applying a gradual channel approximation for the source section and a pseudo-two-dimensional approximation for the drain section, saturation voltage is obtained by considering the voltage and channel current continuity at the boundary of the two sections. Three fitting parameters in the model are determined by comparing the theoretical calculation results with the observed substrate current in samples with various device parameters. The present model was successfully applied to describe the two experimental results: the gate oxide thickness dependence of the gate current injection efficiency and the kink in the maximum channel electric field strength versus gate voltage (= drain voltage) relation. The nonuniform channel impurity profile is approximated by the modified Gaussian distribution, which is found to agree well with the estimation by the substrate bias effect of MOST's. The calculated gate currents for the device can well explain the implantation energy dependence of the measured gate currents.     

MOS沟道和衬底电流的二维分布理论建模

小尺寸ＭＯＳ器件参量具有很强的分布效应,需要二维模型描述,本文从ｙ截面流函数方程求解获得了ＭＯＳ器件中的沟道电流和衬底电流二维分布解析模型,模型是横向场Ｅｒ（ｙ）和纵向场Ｅｘ（ｙ）的函数,二维分布模型截有较充分的物理过程,可以基本反映电流密度的实际分布,模型可应用于与电流路径相关的ＭＯＳ器件特性的研究,特别重要的应用领域是ＭＯＳ热载流子可靠性电子学中的栅电流分布建模,选和深亚微米ＭＯＳ器件的横向场     

Current-voltage characteristics of thin-film SOI MOSFET's in strong inversion

A simple analytic model for the steady-state current-voltage characteristics of strongly inverted silicon-on-insulator (SOI) MOSFET's is developed. The model, simplified by a key approximation that the inversion charge density is described well by a linear function of the Surface potential, clearly shows the dependence of the drain current on the device parameters and on the terminal voltages, including the back-gate (substrate) bias. The analysis is supported by measurements of current-voltage characteristics of thin-film (laser-recrystallized) SOI MOSFET's. The dependence of carrier mobility on the terminal voltages, especially the back-gate bias, is analyzed and shown to underlie discrepancies between the theoretical (constant mobility) and experimental results at high gate voltages. The mobility dependence on the back-gate bias enhances the strong influence of the back gate on the drain current, especially when the device is saturated.     

A model for the relation between substrate and gate currents in n-channel MOSFET's

The gate current in n-channel MOSFET's normalized to the source current is expressed as a function of the substrate current normalized to the source current by means of an impact ionization model. The ratio of the electron mean free path for impact ionization to that for optical phonon scattering, which is the most important among the various related device parameters, is determined by indirect measurement of the gate current using stacked-gate MOSFET's. The present model has been applied to interpret the experimental results obtained from samples with a variety of device dimensions. Limitation by the hot-electron emission, which is an important design constraint for submicrometer-gate MOS devices, is studied for single-gate and stacked-gate MOSFET's in comparison with other limiting factors.     

Mechanisms for low-frequency oscillations in GaAs FET's

Low-frequency oscillations in GaAs MESFET's were observed under back-gating conditions. The FET oscillations are directly related to oscillations in leakage currents in the semi-insulating GaAs substrate. The occurrence of these oscillations in the substrate is strongly dependent upon GaAs material. It is proposed that oscillating substrate leakage currents modulate the FET current in two ways; first, by modulating the active channel-substrate junction and second, by inducing periodic voltage fluctuations on the gate via gate pad contacts on the semi-insulating substrate. The latter mechanism is dominant and dependent upon gate bias and gate impedance.     

Lucky-electron model of channel hot-electron injection in MOSFET'S

The lucky-electron concept is successfully applied to the modeling of channel hot-electron injection in n-channel MOSFET's, although the result can be interpreted in terms of electron temperature as well. This results in a relatively simple expression that can quantitatively predict channel hot-electron injection current in MOSFET's. The model is compared with measurements on a series of n-channel MOSFET's and good agreement is achieved. In the process, new values for many physical parameters such as hot-electron scattering mean-free-path, impact-ionization energy are determined. Of perhaps even greater practical significance is the quantitative correlation between the gate current and the substrate current that this model suggests.     

Transient behavior of the kink effect in partially-depleted SOIMOSFET's

The behavior of transients in the drain current of partially-depleted (PD) SOI MOSFET's down to L_eff=0.2 μm is examined as a function of drain bias, gate pulses of varying magnitude (V_GS), pulse duration, and pulse frequency. At fixed V_DS, the gate is pulsed to values ranging from 0.1 V above V_T to V_GS=V_DS. A slow transient is seen when the drain is biased at a V_DS where the current kink is observable. This slow transient can be on the order of microseconds depending on the relative magnitude of the impact ionization rate. For short times after the pulse edge or for very short pulses at low frequencies, it is shown that the subthreshold drain current value can be very different from the corresponding DC, and that the kink characteristic of PD MOSFET's disappears. However, the kink values can be approached when the pulse frequency and/or duration applied to the gate is increased, due to the latent charge maintained in the floating body at higher frequencies. No transient current effects were observed in fully-depleted SOI MOSFET's     

Generation of interface states by hot hole injection in MOSFET's

The emission of hot electrons and hot holes from n-channel MOSFET's into the gate oxide is investigated as a function of the gate bias for a given lateral electric field. The resulting electron gate current as well as the substrate current are analyzed for both the saturation and the linear regime of the transistor. In the saturation regime, a remarkable increase of interface states occurs which can be correlated with the hole generation due to avalanche multiplication in the high-field region. In this case, the electric field normal to the Si-SiO2interface near the drain aids in the injection of hot holes along the channel which initiates acceptor-type interface states. In the linear operation regime, however, no pronounced generation of interface states can be detected.     

A STUDY ON HOT-CARRIER-INDUCED GATE OXIDE BREAKDOWN IN PARTIALLY DEPLETED SIMOX MOSFET''''S

The hot-carrier-induced oxide regions in the front and back interfaces are systemati-cally studied for partially depleted SOI MOSFET's. The gate oxide properties are investigated forchannel hot-carrier effects. The hot-carrier-induced device degradations are analyzed using stressexperiments with three typical hot-carrier injection, i.e., the maximum gate current, maximumsubstrate current and parasitic bipolar transistor action. Experiments show that PMOSFET's     

Transconductance of Silicon-on-insulator (SOI) MOSFET's

Transconductance of n-channel Silicon-on-Insulator (SOI) MOSFET's has been measured with backside gate (substrate) bias as a parameter. For negative values of the backside gate bias, transconductance of SOI transistors is similar to that of bulk devices. On the other hand, transconductance exhibits an unusual behavior when backside gate is positively biased. This is caused by mutual influence between the front-and the backside gate-related depletion zones. Modeling of transconductance using numerical solution of Poisson's equation show good agreement with experimental results.     

Effects of hot-carrier trapping in n- and p-channel MOSFET's

Detailed measurements of hot-carrier gate current and its trapping effects were studied on both n- and p-channel MOSFET's down to submicrometer channel lengths. Comparison of the measurements for these two types of devices is made. No hot-hole gate current or hot-hole trapping was detected in p-channel MOSFET's. A hot-electron gate current is present not only in n-channel MOSFET's, but also in p-channel MOSFET's where the current is increased by hot-electron trapping. By trapping hot electrons uniformly over the channel in n-MOSFET's, it was shown that hot-electron trapping produces only negative oxide charge without generating interface traps.     

MOSFET衬底电流模型在深亚微米尺寸下的修正

建立精确的衬底电流模型是分析ＭＯＳＦＥＴ器件及电路可靠性和进行ＭＯＳＦＥＴ电路设计所必需的．在分析载流子输运的基础上建立了一个常规结构深亚微米ＭＯＳＦＥＴ衬底电流的解析模型,模型公式简单．对模型进行了验证,研究了衬底掺杂浓度与栅氧化层厚度对拟合因子的影响,并分析了模型中拟合因子的物理意义．     

Analytical explanation to double-hump substrate current in funnel-shape transistors

Measurements of double-hump substrate current and enhanced gate current in funnel-shape (FS) MOSFET's have been recently reported [1]. In this letter an analytical explanation of these observations is given. It is shown that contrary to conventional transistors, the maximum lateral field along the channel of FS transistors operated in the wide-drain mode, and therefore the hot-carrier generation region, is shifted towards the source side as the gate voltage is increased. In addition, the maximum lateral field is increased at high gate voltages, giving rise to the abnormal increase of the substrate current. These results are derived from a simple one-dimensional solution of FS transistor characteristics.     

The relationship between gate bias and hot-carrier-inducedinstabilities in buried- and surface-channel PMOSFETs

For accurate predictions of device reliability with respect to hot-carrier effects, it is necessary to establish worst-case stress bias conditions. Detailed measurements of hot-carrier-induced instabilities in short-channel PMOSFETs have revealed that stress gate bias conditions corresponding to peak gate currents result in maximum shifts in device parameters. However, for some parameters, notably those measured at low drain bias, comparable shifts are observed for stress gate bias conditions that correspond to peak substrate currents. These observations are valid for both buried-channel (n-type polysilicon gate) and surface-channel (p-type polysilicon gate) PMOSFETs. An interpretation of these results based on the generation of tapped oxide charge and interface traps is proposed