刻蚀液的调整对Array Mura影响的研究

生产中经常出现常温污渍(Array Mura)不良。针对TFT面板布线细线化及低电阻电极的要求,纯铝工艺迫切需要新型湿法刻蚀液的对应。目前,本文通过对比3种产线中测试的刻蚀液,得出Array Mura的产生主要与纯铝工艺的顶层金属钼的刻蚀后缩进有关,其中测试的刻蚀液C可以有效控制金属钼的缩进至0.1μm以内。控制顶层金属钼缩进的主要原因与刻蚀液C的硝酸浓度和添加剂含量有关,通过控制药液进而控制了刻蚀过程内的电化学反应,最终使得Array Mura得到了有效的改善,后续无相关不良发生。采用刻蚀液C刻蚀后线宽、坡度角等相关刻蚀参数均满足要求,目前已经导入量产使用。     

金属的腐蚀和蚀刻

前言在集成电路中应用了各种金属膜,例如:导体中主要是采用Al(铝)蒸发膜,另外,在一部分导体中也使用Au膜和高熔点金属的复合膜。而且Au的复合膜可以应用在梁式引线里。除此之外,在自对准MOS晶体管的栅电极里采用的是Mo膜或W膜。在集成电路工序中对于这些金属膜必须作出图形来,该方法大多采用照相蚀刻法,是在整个金属膜形成后进行的。在此想从电化学角度出发对金属膜的蚀刻进行展望。     

TFT-LCD制造工艺中金属残留的解决方案

在TFT-LCD阵列的四次掩模技术中,复合层刻蚀是非常难控制的一道工序,最突出的问题是在复合层刻蚀后信号线的两边有金属残留,金属残留会对之后的绝缘层产生影响,导致断层等不良.调整复合层刻蚀工艺是目前解决金属残留问题的通用方法,但是都没有根本地解决这个问题.文章通过研究信号线刻蚀时间对复合层刻蚀后金属残留的影响,认为通过...     

Mo/Al/Mo结构电极的坡度角和关键尺寸差研究

Mo/Al/Mo结构金属作为TFT的电极,刻蚀后的坡度角和关键尺寸差是重要的参数。明确影响坡度角和关键尺寸差的工艺参数,进而控制坡度角和关键尺寸差,这对工艺制程至关重要。本文探究了膜层结构、曝光工艺、刻蚀工艺对坡度角和关键尺寸差的影响,并对刻蚀工艺进行正交试验设计。实验结果表明:Al膜厚每减小60nm,坡度角下降约9°,关键尺寸差增加0.1μm。曝光工艺中,显影后烘烤会增加光阻粘附力,导致关键尺寸差减小0.1μm,同时坡度角增加约9°。刻蚀工艺中,过刻量每增加10%,坡度角下降3.3°,关键尺寸差增加0.14μm;正交试验结果表明,对关键尺寸差、刻蚀均一性、坡度角影响因素的重要性顺序是:液刀流量Air Plasma电压水刀流量。经上述探究表明,坡度角和关键尺寸差呈负相关关系,刻蚀程度增加,关键尺寸差增加,而坡度角则减小。可以通过调节工艺参数对坡度角和关键尺寸差进行控制。     

TFT-LCD阵列腐蚀性缺陷分析(英文)

在TFT-LCD的生产过程中,阵列金属被腐蚀是造成TFT-LCD产品缺陷(亮线、薄亮线等)的常见原因。文章对实际生产过程中阵列基板的一种典型腐蚀性缺陷,应用扫描电子显微镜(SEM)、聚焦离子束(FIB)和能谱仪(EDS)等工具,并且结合BO(Business Objects)、CIM(Computer Integrated Manufacturing)等数据统计软件进行了分析。确定了造成缺陷的原因是栅金属暴露在含氯元素的酸性气体中被腐蚀,还确定了酸性气体的泄露源,并且推断出其形成机理:腐蚀发生在栅金属刻蚀(Gate Etch)工艺和多层膜沉积(Multi-Deposition)工艺之间,随后的多层膜沉积工艺的抽真空过程促进了缺陷的进一步形成。另外,针对发生此种缺陷时的应急措施进行了探讨。     

湿法刻蚀FI CD均一性的影响因素及提高刻蚀均一性的研究

随着高分辨率产品导入,TFT-LCD阵列段各项参数范围越来越小,工艺要求更为严格,为了更好地管控湿法刻蚀各项参数,本文以湿法刻蚀FI CD(Final Inspection Critical Dimension)均一性的影响因素及如何提高FI CD均一性为目的进行研究。首先,通过对湿法刻蚀设备参数(主要包括刻蚀液温度、流量、压力、浓度、Nozzle Sliding、Oscillation Speed、刻蚀时间等)进行试验,验证各项参数对FI CD均一性的影响。其次,对沉积工序、曝光工序以及产品设计等进行试验,获悉影响因素并进行改善。通过对湿法刻蚀设备自身参数的调整,如减少设备温度、流量、压力波动,使参数保持相对稳定状态,可有效改善湿法刻蚀FI CD均一性,FI CD的均一性可从1.0降低至0.5。通过对湿法刻蚀设备参数进行试验并做相应调整,湿法刻蚀FI CD均一性改善效果显著。     

阵列基板栅极制程的Cu腐蚀研究

在大尺寸液晶显示器的薄膜晶体管(Thin Film Transistor,简称TFT)TFT工艺技术中,Cu正逐步取代Al作为电极材料。与Al电极制程相比,在进行栅极(Gate)制程时Cu容易发生腐蚀,这会降低产品良率。本文结合ADS(Advanced Super Demension Switch)显示模式下0+4掩膜板(mask)技术的Gate刻蚀制程和1+4掩膜版技术Gate光刻胶(Photo Resist,简称PR)剥离制程的Cu腐蚀现象进行分析,结合实验验证,确定Cu腐蚀原因,最终提出改善方案。实验结果表明:0+4mask技术的Gate制程中,ITO刻蚀液所含的HNO3会使MoNb/Cu结构电极的Cu发生电化学腐蚀;将电极结构更改为单Cu层则可以避免电化学腐蚀。在1+4mask技术的PR剥离(Strip)制程中,基板经历的剥离时间长或进行多次剥离或在剥离设备中停留,均会引起Cu腐蚀;增加剥离区间与水区间空气帘(Air Curtain)吹气量、增加TFT基板在过渡区间(H2O与剥离液接触的区间)的传输速度,管控剥离液使用时间等措施可以缓解Cu腐蚀。     

双层金属布线中隔离介质淀积工艺研究

隔离介质淀积是微波硅功率器件双层金属布线工艺中的核心工序.从隔离介质结构层次的选取入手,通过理论分析,选取SiO2-Si2N4两层介质为最佳隔离介质结构;着重对隔离介质淀积工艺进行深入研究.通过实验对比分析,确定芯片的隔离介质淀积工艺条件,从而避免光刻胶、腐蚀液等物质残留在芯片内部,提高双层金属布线的可靠性.     

磁存储器驱动电路界面平坦化研究

利用原子力显微镜(AFM)和扫描电镜(SEM)对磁存储器(MRAM)驱动电路与存储单元--磁性隧道结(MTJ)的连接界面的表面平坦化进行了研究.原子力显微镜照片表明:磁控溅射沉积的金属铝膜的表面由尺寸约为300nm的颗粒组成,其表面粗糙度约为几十纳米的量级,用统计平均值(均方根值root mean square,RMS)描述约为10nm;在铝膜的表面沉积一层难溶金属Ti或Ta膜以后,可很好地改善过渡层金属表面的平坦化效果.通过用化学机械平坦化设备(chemical mechanical planarization,CMP)在小压力和低转速的条件下,可使过渡层金属表面的RMS值达到小于1nm的平坦化效果.扫描电镜照片的结果也显示:利用光刻胶平坦化,然后通过调节反应离子刻蚀的条件,使刻蚀的过程中对氧化硅和光刻胶的刻蚀速率相等,去掉光刻胶,达到平坦化整个芯片表面的效果.     

磁存储器驱动电路界面平坦化研究

利用原子力显微镜(AFM)和扫描电镜(SEM)对磁存储器(MRAM)驱动电路与存储单元--磁性隧道结(MTJ)的连接界面的表面平坦化进行了研究.原子力显微镜照片表明:磁控溅射沉积的金属铝膜的表面由尺寸约为300nm的颗粒组成,其表面粗糙度约为几十纳米的量级,用统计平均值(均方根值root mean square,RMS)描述约为10nm;在铝膜的表面沉积一层难溶金属Ti或Ta膜以后,可很好地改善过渡层金属表面的平坦化效果.通过用化学机械平坦化设备(chemical mechanical planarization,CMP)在小压力和低转速的条件下,可使过渡层金属表面的RMS值达到小于1nm的平坦化效果.扫描电镜照片的结果也显示:利用光刻胶平坦化,然后通过调节反应离子刻蚀的条件,使刻蚀的过程中对氧化硅和光刻胶的刻蚀速率相等,去掉光刻胶,达到平坦化整个芯片表面的效果.     

Experimental analysis of galvanic corrosion of a thin metal film in a multilayer stack for MEMS application

Experimental analysis of galvanic corrosion of an aluminium (Al)–chromium (Cr)–gold (Au) multilayer stack is presented in this paper. The use of two or more stacks of different metal films is common for realisation of various microelectromechanical system (MEMS) devices. However, patterning of the multilayer metal films by lithographic and etching process is very critical due to galvanic corrosion. In a multilayer metal stack film, the knowledge of etch rate of the individual metal layers is very important for designing the process flow for the fabrication of micro-sensors. In the present study, galvanic corrosion characteristics of Al–Cr binary metal stack and Al–Cr–Au ternary metal stack in different etching solutions have been studied. The intermetallic contact area and the exposed metal area in the electrolyte solution were varied using an innovative process step involving silicon shadow mask technique and lithographic process. It is observed from the experimental results that for an intermetallic contact area to exposed metal area ratio of 2, etch rate of aluminium layer is increased by more than two times in aluminium etchant and 80% in Cr etchant as compared to the etch rate of the aluminium layer without intermetallics effect. The results obtained from this study have been applied for designing the fabrication flow and successful realisation of a MEMS piezoresistive accelerometer.     

Microline-etching technique

This paper describes a technique of etching composite layers of molybdenum + gold into lines of micron dimensions. The technique makes use of sputter etching the composite layer of gold + molybdenum using the photo-resist as the mask and then using the chemical etching method to selectively etch the under layer of molybdenum. As a result, it is possible to under-cut the molybdenum film in a controllable manner thereby achieving lines of micron dimensions while leaving a wide and thick gold layer on the top. The various advantages of the technique are also pointed out.     

(中国微米纳米)一种牺牲层工艺中金属电极保护方法研究

为了在牺牲层工艺中保护金属电极不被腐蚀,提出了一种利用铝层保护金属电极的方法。在试验中采用了两种铝保护层厚度300nm和1μm,在两种腐蚀液体4NH4F:1HF:2甘油和1HAC: 1NH4F中进行了试验,通过试验表明,铝金属层在两种腐蚀液体中都能够有效保护金属电极,延长牺牲层的腐蚀时间。最后,通过SOI微加速度计加工工艺进一步验证了该方法的有效性。     

Selective wet etch of a TaN metal gate with an amorphous-silicon hard mask

The appropriate wet etch process for the selective removal of TaN on the HfSiON dielectric with an amorphous-silicon(a-Si) hardmask is presented.SCI(NH_4OH:H_2O_2:H_2O),which can achieve reasonable etch rates for metal gates and very high selectivity to high-k dielectrics and hardmask materials,is chosen as the TaN etchant. Compared with the photoresist mask and the tetraethyl orthosilicate(TEOS) hardmask,the a-Si hardmask is a better choice to achieve selective removal of TaN on the HfSiON dielectric be...     

Development of an etchant for selectively etching TiWNxin the presence of electroplated 95%Pb-5%Sn solder

Shrinking die sizes and increasing I/O density is motivating the push toward flip chip packages. A flip chip interconnection system with a under bump metallurgy stack containing sputtered TiWN_X/sputtered Cu/electroplated Cu stud/electroplated 95%Pb-5%Sn was developed. An important step in the above process is the selective etching of the sputtered Cu bus layer and the TiWN_X barrier layer, in the presence of the Pb-Sn solder. The Cu bus layer was selectively etched using commercial etchants. However, no commercial etchants were available for selectively etching the TiWN_X layer, H₂O₂-NH₄OH based etching systems, popularly known as Standard Clean-1 cleaning solutions, have been extensively used to clean silicon wafers in front end wafer fabrication where only trace metal contamination exists. Since metals like lead, copper, titanium, tin and tungsten catalyze the heterogeneous decomposition of the peroxide, the unstable H₂O₂-NH₄OH based etching systems are rarely used to etch metal films. In this paper the development of a H ₂O₂-NH₄OH based etchant to selectively etch the sputtered TiWN_X films in the presence of electroplated 95%Pb-5%Sn solder bumps is discussed. A 2³ full factorial experiment with mid point was conducted to establish the etchant composition, as well as process temperature, that give satisfactory responses with respect to etch time, permissable undercut of the Cu stud (caused by the NH₄OH), and acceptable bump shape after reflow. Statistical analysis was used to understand the significant factors influencing the etch rate and undercut. An etchant containing 6% by volume of 30%-H₂O₂ and 0.75% by volume of 30%-NH₄OH operated at a temperature of 37°C was found to give satisfactory results     

以非晶硅为硬掩膜的TaN金属栅的选择性湿法腐蚀

提出了一种在HfSiON介质上,采用非晶硅为硬掩膜的选择性去除TaN的湿法腐蚀工艺。由于SC1(NH4OH:H2O2:H2O)对金属栅具有合适的腐蚀速率且对硬掩膜和高K材料的选择比很高,所以选择它作为TaN的腐蚀溶液。与光刻胶掩膜和TEOS硬掩膜相比,因非晶硅硬掩膜不受SC1溶液的影响且很容易用NH4OH溶液去除（NH4OH溶液对TaN和HfSiON薄膜无损伤）,所以对于在HfSiON介质上实现TaN的选择性去除来说非晶硅硬掩膜是更好的选择。另外,在TaN金属栅湿法腐蚀和硬掩膜去除后, 高K介质的表面是光滑的,这可防止器件性能退化。因此,采用非晶硅为硬掩膜的TaN湿法腐蚀工艺可以应用于双金属栅集成,实现先淀积的TaN金属栅的选择性去除。     

InSb(111)A面腐蚀坑成因分析

采用光学显微镜和光学轮廓仪分析了InSb晶片(111)A面经特定腐蚀剂腐蚀后出现的两种特征腐蚀坑,并通过多次腐蚀试验观察了这两种腐蚀坑形貌的演变。从理论上对腐蚀坑形貌的成因进行了分析,结果显示1类特征腐蚀坑的成因是由于晶片固有的位错缺陷,2类特征腐蚀坑可能是由于晶片表面存在一定深度的损伤层引起的。     

Modeling and algorithm development for automated optical endpointing of an HBT emitter etch

This paper discusses the development of a high-accuracy endpointing algorithm for the emitter etch of a heterojunction bipolar transistor (HBT). Fabrication of high-performance HBTs using self-aligned base-emitter processes requires etching through the emitter layer and stopping with very high accuracy on the base layer. The lack of selectivity in dry etching coupled with the high etch rates possible in high density plasmas render the use of a standard timed overetch impractical, especially as device layers continue to become thinner. The etch process under study requires the complete removal of an AlInAs emitter while etching no more than 5 nm of the underlying GaInAs base layer. Etch products are monitored using optical emission spectroscopy (OES) to determine etch endpoint. The process under study relies on the intensity of the 417.2 nm Ga emission line. The detection of the Ga line indicates that the etch has reached the GaInAs layer. However, the presence of a time-varying Ga baseline signal before endpoint and significant noise in the OES signal necessitate more than a simple threshold scheme for critical endpoint detection. The algorithm presented here is based on a generalized likelihood ratio with a signature function. This algorithm is robust to variance in the optical gains of the measurement equipment and is applicable to other etch processes. Experimental results of automated endpointing using this algorithm are presented in the form of pre- and post-etch ex situ film thickness measurements.