各膜层对光刻胶灰化的影响

研究各膜层对灰化速率的影响,增强对灰化工艺的了解,为四次光刻工艺改善提供参考。采用探针台阶仪测量在相同灰化条件下不同膜层样品的灰化速率和有源层损失量,对结果进行机理分析和讨论。实验结果表明:有源层会降低灰化速率,源/漏金属层可以增大灰化速率,栅极金属层对灰化速率无影响。对于正常膜层结构的阵列基板,源/漏层图形密度越大,灰化速率越小,图形密度每增大1%,灰化速率下降14nm/min。有源层和源/漏金属层对灰化等离子体产生影响,从而影响灰化速率。     

光刻胶灰化工艺与深亚微米线条的制作

随着器件尺寸的缩小，细线条的制作成为很关键的工艺，普通光学光刻已接近其分辨率的极限，而电子束光刻和Ｘ射线光刻技术复杂、费用昂贵。本文对光刻胶灰化工艺进行了分析和研究，并应用此工艺进行了深亚微米线条的制作，在普通光学光刻机上制作出宽度小于０．２５μｍ细线条。我们已将此工艺成功地应用在深亚微米ＭＯＳＦＥＴ的制作中。     

光刻胶涂胶厚度均匀性影响因素探究

介绍了光刻胶涂胶过程中对涂胶厚度均匀性的影响因素及发生均匀性问题的成因。对光刻工艺和光刻胶进行概述,通过对光刻工艺和光刻胶的涂胶学习可发现随着光刻工艺的不断进步,对光刻胶涂胶胶厚均匀性要求也在不断地提升,在实际的生产过程中却经常会出现涂胶均匀性较差而无法满足工艺要求。重点针对光刻胶涂胶厚度均匀性影响因素进行探究,详细介绍了会对其产生影响的因素。通过有效地管控好这些影响因素能够确保涂胶厚度均匀性,提升曝光质量,从而推动光刻技术的发展。     

光刻技术的发展与光刻胶的应用

本文根据超大规模集成电路光刻技术的不断发展对与之配套的光刻胶的不同要求，阐述了国内外光刻胶的现状、应用和发展状况等。     

OMR-85光刻胶的研究与应用

在半导体制造中，光刻胶是重要的原材料之一，本文从转速与膜厚，感光灵敏度，图形变化差等方面对ORM-85光刻胶进行了研究，得出了用于大生产的一套工艺，解决了接触式曝光方式粘版的问题及提高了产能。     

不同衬底材料对光刻胶剖面的影响

文章研究了在127mm硅片上分别生长金属铝和二氧化硅氮化硅叠两种IC常用材料作为衬底对光刻胶形貌的影响,其造成光刻胶形貌差的原因是金属底部反射率高导致光刻胶侧面曝光和入射光通过二氧化硅氮化硅叠层厚度的光程差正好为光源波长的整数倍,从而导致光刻胶底部干涉光同相位。通过增加底部抗反射层和调整最佳膜层厚度解决了在这两种衬底材料下光刻胶形貌差的问题。     

ICP刻蚀对光刻胶掩模及刻蚀图形侧壁的影响

采用AZ1500光刻胶作为掩模对GaAs和InP进行ICP刻蚀,研究了刻蚀参数对光刻胶掩模及刻蚀图形侧壁的影响。结果表明,光刻胶的碳化变性与等离子体的轰击相关,压强、ICP功率和RF功率的增加以及Cl2比例的减小都会加速光刻胶的碳化变性,Cl2/Ar比Cl2/BCl3更易使光刻胶发生变性。对于GaAs样品刻蚀,刻蚀气体中Cl2含量越高,刻蚀图形侧壁的横向刻蚀越严重。Cl2/BCl3对GaAs的刻蚀速率比Cl2/Ar慢,但刻蚀后样品的表面粗糙度比Cl2/Ar小。刻蚀InP时的刻蚀速率比GaAs样品慢,且存在图形侧壁倾斜现象。该工作有助于推动在器件制备工艺中以光刻胶作为掩模进行ICP刻蚀,从而提高器件制备效率。     

准分子激光线宽对光刻性能的影响

描述了激光线宽对光刻过程的影响模型建立过程中所使用的方法.成像透镜产生的色差结合实际激光光谱可以把激光线宽的影响包括在光刻模拟的模型中,使用PROLITH软件模拟了线宽对空间像的临界尺寸、焦深、曝光宽容度的影响,孤立线和半孤立线条尺寸在240nm到140nm的范围内完成研究.实验结果表明,光刻过程中增加激光线宽使空间成像质量变差,较大的线宽也导致了曝光宽容度的损失.     

深紫外光刻投影物镜的三维偏振像差

深紫外光刻投影物镜是光刻机的核心部件,然而无论是照明光场偏振态的空间分布,还是光刻投影物镜自身的偏振像差都将改变光束的紧聚焦特性,对成像质量造成不可忽略的影响。基于三维琼斯矩阵,把偏振像差函数推广到三维空间,建立了三维相干光场中偏振像差的评价方法,并分析了典型的偏振敏感光学系统深紫外光刻投影物镜的三维偏振像差,详细阐述了其物理意义。研究发现:三维偏振像差函数的光瞳分布与视场、光学薄膜以及光学系统的自身结构密切相关。深入讨论了光学薄膜及偏振效应对光刻投影物镜成像质量的影响,进一步研究了照明光场的偏振态分布与光学系统波像差的关系,研究表明:光学薄膜引入的附加位相将导致光刻投影物镜的像质明显下降,而采用径向矢量光场照明可以改善成像质量。     

关于单模光纤段差的研究

本文研究段差的形成机理,并实际模拟段差的形成,为解决单模光纤段差提供了理论和实际依据.     

SiO2 single layer for reduction of the standing wave effects in the interference lithography of deep photoresist structures on Si

We demonstrate that the use of a single SiO₂ film, with thickness corresponding to one standing wave (SW) period allows the recording of deep photoresist structures on silicon substrates by laser interference, without use of any additional antireflecting coating. This condition corresponds just to the opposite thickness (half SW period) previously proposed for using the SiO₂ films for phase-shifting the SW pattern. Theoretical and experimental results demonstrated that for the lithography of deep structures, the contrast of the SW pattern, the minimum light intensity of the SW pattern and the photoresist adhesion are the most important parameters of the process.     

光刻制程参数对光刻胶DICD和锥角的影响

光刻胶经过曝光、显影后的锥角(Taper)和关键尺寸(Develop Inspection Critical Dimension,DICD)是光刻工艺的重要参数。明确影响锥角和DICD的工艺参数,进而控制锥角和DICD,这对工艺制程至关重要。本文结合光刻制程,探究了光刻胶厚度、曝光剂量、Z值、显影时间对锥角和DICD的影响,并结合蒙特卡罗算法对显影制程进行评估。实验结果表明:光刻胶厚度每增加1μm,DICD增加约2.6μm。同时,厚度增加会导致光刻胶顶部的锥角逐渐由锐角向钝角演变。曝光剂量每增加10mJ/s,DICD则减小约0.8μm,锥角则呈阈值跳跃式上升趋势。基板在最佳焦平面曝光,DICD和锥角均一性最好。显影时间每增加10s,DICD下降约0.3m,锥角则增加约1.7°。最终,DICD和锥角呈负相关关系,可以通过调节光刻工艺参数对锥角和DICD进行控制。     

紫外线厚胶光刻技术研究及应用

紫外线厚胶光刻技术已广泛应用于 3D微机械结构的制作。本文选用AZ4 6 2 0和SU 8两种光刻厚胶 ,采用德国卡尔·休斯公司的MA 6双面对准光刻机 ,对紫外线光刻工艺条件进行了对比研究 ,结果表明 ,负性光刻胶SU 8的光敏性好 ,胶结构图形的侧墙较陡直 ,能够实现较大的深宽比 ,为复杂结构的三维微机械器件的制作提供了保证。     

不同光刻胶作保护层对a-IGZO TFT性能的影响

采用脉冲直流溅射的方式沉积IGZO膜层作为底栅结构TFT的有源层,并在背沟道上涂覆不同类型的光刻胶作为保护层,探讨不同保护层对器件电学特性的影响。经考察发现:采用光刻胶作为保护层时,保护层制作后短期内可维持器件的电学特性基本不变;但涂胶后暴露在空气中一定时间后,器件的电学特性开始衰退,尤其是阈值电压变化较明显,器件工作模式由增强型变为耗尽型,并推断光刻胶中溶剂接触到背沟道中IGZO,其化学反应导致沟道中氧脱附,载流子浓度增加。实验还发现:使用SU-8负性光刻胶作为保护层的器件,其电学特性衰退较小,在空气中放置一段时间后表现最稳定。     

光刻工艺对大面阵长波碲镉汞芯片性能的影响

通过分析器件工艺对大面阵长波碲镉汞芯片性能的影响,发现光刻工艺非均匀性累积进而显著影响碲镉汞芯片性能的现象.应用Matlab仿真计算,定量分析了碲镉汞材料片表面凸点对不同线宽光刻工艺非均匀性的影响,提出了降低光刻工艺非均匀性累积的方法和高质量光刻工艺对碲镉汞材料平坦度的具体要求.     

单脉冲雷达天线差斜率测试技术的改进

针对工程应用中单脉冲雷达差斜率简便测试问题,提出了一种正弦波单脉冲差斜率测试方法。推导了将非相参的正弦波信号用于差斜率测试的公式,并将正弦波信号直接用于单脉冲给差斜率测试系统,实现对单脉冲雷达系统参数的快速校正。仿真结果表明,经过该方法校正的单脉冲雷达系统可实现优于0.01的测角精度。该测试方法能够实现高精度的系统测试性能,对解决工程应用中的测试校正问题具有实际指导意义。     

Fabrication of submicron photon sieve using E-beam lithography and X-ray lithography

In this paper, a new hybrid method to fabricate submicron photon sieve is proposed, where the E-beam lithography and the X-ray lithography are used. It is found that 2.8 μm thickness of the polyimide film, 400 nm thickness of the ZEP-520 and 280 μC/cm² exposure dose are good for E-beam lithography, while 500 nm thickness of the PMMA and 30 s developing time are good for X-ray lithography. We have successfully fabricated the photon sieve with these parameters (the diameter of photon sieve: 250 μm, the focal length: 150 μm, the diameter of the outmost pinhole: 420 nm). Some key techniques of this method are analyzed respectively, and the error analysis are done at the end of this paper. It provides a direction of nanoscale optical element fabrication with higher resolution and lower cost.     

Spray coating of PMMA for pattern transfer via electron beam lithography on surfaces with high topography

Spray coating of polymethylmethacrylate (PMMA) as electron beam resist on non planar surfaces is presented as a reliable technique for deposition of uniform resist layers with adjustable thickness at wafer scale. In the experiments a commercial spray coating system with an ultrasonic spray nozzle was used. Parameters which influence the quality of the resist layer with respect to uniformity across a 4 in Si wafer, such as ultrasonic power and dispensed volume, were evaluated. The suitability of spray coated PMMA for the pattern transfer on surfaces with high topography was proven by PMMA spray coating of 8 μm deep trenches etched into Si wafers. The PMMA was then electron beam exposed and chromium line patterns were transferred on the Si surface via a lift-off process.     

Predicting mask distortion, clogging and pattern transfer for stencil lithography

One of the ultimate tasks for stencil lithography is the ability to fabricate arrays of structures with controlled dimensions on the nanometer scale precisely positioned on a suitable surface. The race to shrink feature sizes requires the limits of conventional lithography to be extended to high-throughput, low cost, reliable and well-controlled processes of which stencilling is a promising candidate for nanoscale applications. Identifying, predicting and overcoming issues accompanying nanostencil lithography is critical to the successful and timely development of this technique for a wide range of potential applications. This paper addresses phenomena associated with stencil nanopatterning and presents the results of modelling and simulation studies for predicting the deleterious effects of mask distortion and clogging during pattern transfer. It is shown that degrading effects of stress-induced deformation of stencils can be dealt with via optimal design of corrugation structures which in turn reduce stencil deformation and significantly improves pattern definition. Modelling results are validated by comparison to experiment. The corrugation structures can be used to define practical design rules for fabrication of stable large area (“full scale”) purpose-designed stencil membranes. The accurate modelling of the clogging phenomenon combined with gradually evolving stencil deformation, also presented in the paper, can be used for prediction of pattern distortion, to calculate maximum thickness of a deposited layer and/or for prediction of the stencil lifetime.