Bubble memory as small mass storage

Magnetic bubble memories (MBM) show potential of becoming a major storage technology by 1980. At the same time, the established disk technology will see continued technological and cost-performance improvements well into the 1980's. The fast development of MOS RAM in both cost per bit and bits per chip will also continue at a rapid rate. The emerging MBM technology as well as CCD and EBAM technologies must be competitive with semiconductor RAM's on one hand and disk technology on the other hand for successful market entry.This paper outlines how magnetic bubble memories can achieve status as a major mass storage technology. The key is the growth of microprocessor (MPU) based systems with resulting demand for low cost, small mass storage. MBM characteristics satisfy the requirements for microprocessor mass storage.     

Quadruply self-aligned stacked high-capacitance RAM using Ta2O5high-density VLSI dynamic memory

A new one-transistor, one-capacitor RAM cell structure called a Quadruply Self-Aligned Stacked High Capacitance (QSA SHC) RAM is proposed as a basic cell for a future one-million-bit VLSI memory. This cell consists of a QSA MOSFET and a Ta2O5capacitor stacked on it. By this cell, the ultimate cell area3F times 2Fcan be realized with sufficient operating margin. Here,Fis the minimum feature size. The basic cell was fabricated and its operation was experimentally verified. The leakage current of Ta2O5film was small enough for the storage capacitor dielectric. Using a3F times 4Fcell and a4Fpitch sense amplifier, a one-million-bit memory was designed with a 2-µm rule. A cell size of 6.5 × 8 µm², and a chip size of 9.2 × 9.5 mm²were obtained. The access time, neglecting the RC time constant of the word line, was estimated to be about 170 ns. Based on this design, it is argued that a future one-million-bit memory can be realized by QSA SHC technology with a 2-1-µm process. The mask set of the 1-Mbit RAM was actually fabricated by an electron-beam mask maker. A photomicrograph of the 1-Mbit RAM chip patterned by the mask set is shown. This chip was patterned not to get an operating sample but to show an actual chip image of the future 1- Mbit RAM. The area of each circuit block including storage array can be seen in this chip image.     

A 24-bit microprocessor for data communication systems designed on the basis of a general cell library

A 24-bit microprogrammed processor with 200 ns instruction cycle time has been realized as an experimental special purpose VLSI chip. The design was based on a general cell library and a set of advanced CAD tools. The technology used is a 3 /spl mu/m silicon gate, n-channel, single metallization MYMOS process. The chip integrates 9400 gate functions plus a 256/spl times/27 bit static RAM on 78.5 mm/SUP 2/.     

A fuzzy logic inference processor

A mixed analog-digital fuzzy logic inference engine chip fabricated in an 0.8 μm CMOS process is described. Interface to the processor behaves like a static RAM, and computation of the fuzzy logic inference is performed between memory locations in parallel by an array of analog charge-domain circuits. Eight inputs and four outputs are provided, and up to 32 rules may be programmed into the chip. The results of the inference over all rules, including a center-of-mass defuzzification, may be computed in 2 μs     

MARVLE: a VLSI chip for data compression using tree-based codes

Describes the architecture and design of a CMOS VLSI chip for data compression and decompression using tree-based codes. The chip, called MARVLE, implements a memory-based architecture for variable length encoding and decoding based on tree-based codes. The architecture is based on an efficient scheme of mapping the tree representing any binary code onto a memory device. A prototype 2-mm CMOS VLSI chip has been designed, verified, and fabricated by the MOSIS facility. The chip has a 512×12 static RAM with an access time of 4 ns and logic circuitry for compression as well as decompression. The chip occupies a silicon area of 6.8 mm×6.9 mm and consists of 49695 transistors. The prototype chip yields a compression rate of 95.2 Mb/s and a decompression rate of 60.6 Mb/s with a clock rate of 83.3 MHz. The VLSI hardware can be used to implement the JPEG baseline compression scheme     

A 32 K ASIC synchronous RAM using a two-transistor basic cell

A 32 K synchronous RAM using a two-transistor basic cell has been developed for use with a 100 K compact gate array. The basic cell consists of only two transfer gates and a storage capacitor and thus results in a very dense memory array. The RAM operates as a static RAM during system operations and provides both serial and parallel data ports. It can be reconfigured into 1 K×32, 2 K×16, 4 K×8, etc. depending on the system needs. An access time of 40 ns was achieved for a test chip at an operating power of 175 mW     

Winner-Takes-All Associative Memory: A Hamming Distance Vector Quantizer

We present a design methodology for mapping neuralyinspired algorithms for vector quantization, into VLSI hardware.We describe the building blocks used: memory cells, current conveyors,and translinear circuits. We use the basic building blocks todesign an associative processor for bit-pattern classification;a high-density memory based neuromorphic processor. Operatingin parallel, the single chip system determines the closest match,based on the Hamming distance, between an input bit pattern andmultiple stored bit templates; ties are broken arbitrarily. Energyefficient processing is achieved through a precision-on-demandarchitecture. Scalable storage and processing is achieved througha compact six transistor static RAM cell/ALU circuit. The singlechip system is programmable for template sets of up to 124 bitsper template and can store up to 116 templates (total storagecapacity of 14 Kbits). An additional 604 bits of auxiliary storageis used for pipelining and fault tolerance re-configuration capability.A fully functional 6.8 mm by 6.9 mmchip has been fabricated in a standard single–poly, double–metal2.0µmn–well CMOS process.     

A 16-Mbit/s adapter chip for the IBM token-ring local area network

The authors describe a 9.02×9.02-mm chip built in 1-μm CMOS with two levels of metal and an additional mask level for fabricating capacitors. It contains both analog and digital circuits and has provisions for self-test. The function includes the transmitter, receiver, protocol handler, an microprocessor, as well as interfaces for RAM/ROM storage, IBM PC bus, IBM PS/2 bus, IBM 3174 bus, and Motorola 68000 bus. The physical design terrains are formed by 24K circuits of standard cell gates, a 10K-circuit equivalent hand-honed custom microprocessor, and an analog macro. The chip operates from a single 5-V supply, and the power consumption is 0.8 W nominal at 16 Mb/s. The chip can also be operated at 4 Mb/s     

A 4K CMOS gate array with automatically generated test circuits

A 2-/spl mu/m CMOS 4K-gate array using a newly devised scan bus method has been developed. This method is applied to the array by using a double-latch structure, parallel scanning, and normal-test common pin techniques. The gate array can be tested for 95-100% of all DC faults using computer-generated test circuits and test data, without placing restrictions on the logic design. Due to an access-to-output flip-flop structure and a gate-isolated three-input type basic cell, including embedded transistors, the area increase and operating speed degradation due to test circuits are considerably reduced. Furthermore, besides the flip-flop blocks, a built-in RAM macroblock is available. Degradation of operating speed is evaluated as 10%. The scan operation is done at a clock cycle of 120 ns, and the access time of the RAM macroblock is 34 ns. The gate array includes 4032 three-input gates on a 7.2/spl times/7.02-mm chip.     

A high-speed low-power Hi-CMOS 4K static RAM

A high-speed low-power CMOS fully static, 4096 word by 1 bit random-access memory (RAM) has been developed, which contains a bipolar-CMOS (BCMOS) circuit on the same chip. The device is realized using low-power-oriented circuit design and high-performance CMOS technology utilizing 3-µm gate length. The fabricated 4K static RAM has an address access time of 43 ns and a power dissipation of 80 mW.     

A 20 ns 64K (4K/spl times/16) NMOS RAM

A 64K (4K/spl times/16) NMOS RAM is described which uses new circuit techniques and design concepts to achieve an average nominal access time of 20 ns. The RAM was built using a relatively straightforward NMOS technology with single-level metal, single-level polycide, an average minimum feature size of 1.7 /spl mu/m, and an effective channel length of 1.2 /spl mu/m. The chip is organized physically into four 16K blocks. Cell area is 292 /spl mu/m/SUP 2/ with a chip area of 32.6 mm/SUP 2/. A four-device split-wordline cell was used to reduce the wordline delay. Chip organization, simplified clocking and timing, and new circuits were especially important for improved performance. An address buffer with internal reference, a switched decoupled bootstrapped decoder, and a self-timed sense amplifier are described.     

A 2K/spl times/8-bit static MOS RAM with a new memory cell structure

A 2K/spl times/8-bit static MOS RAM with a new memory cell structure has been developed. The memory cell consists of six devices including four MOSFETs and two memory load resistors. Two load resistors are fabricated in the second-level polysilicon films over the polysilicon gate MOSFET used as the driver. Thus the memory cell area is determined only by the area of four MOSFETs. By applying the new cell structure and photolithography technology of 3 /spl mu/m dimensions, the cell area of 23/spl times/27 /spl mu/m and the chip area of 3.75/spl times/4.19 mm have been realized. The RAM is nonclocked and single 5 V operation. Access time of about 150 ns is obtained at a supply current of 120 mA.     

Bipolar dynamic memory cell

A bipolar dynamic memory cell for use in a high-speed random- access memory consists of a cross-coupled pair of transistors and two diodes. Information is dynamically stored using a bistable charge distribution and must be refreshed at a frequency of 1 kHz by a SELECT operation. Standby power per memory cell is in the nanowatt range. The cell requires only 3 interconnect lines and can be fabricated with standard bipolar technology on 12-mil/SUP 2/ silicon area. Cycle time is limited by the speed of decoding, driving, and sensing circuits and is estimated to be 50 ns for a 512-bit RAM chip with complete on-chip decoding.     

A fully operational 1 kb variable threshold Josephson RAM

The first fully operational Josephson RAM in LSI level integration is described. The chip is designed as a 4 b× 256-word data RAM unit for a 4 b Josephson computer. A variable-threshold memory cell and the related memory architecture are used. They are so simple in structure that the fabrication can be accomplished using current Josephson junction technology. A directly coupled driver gate for a resistive bit line applies an accurate and stable driving current to the memory cell array. The RAM chip is fabricated with a 3 μm Nb/Al-oxide/Nb junction technology. For obtaining reliable RAM chips, a plasma-enhanced CVD (chemical-vapor-deposited) silicon dioxide layer is introduced for insulation between the ground plane and the base electrode. The thermal uniformity of the wafer is improved during the oxidation process for making a tunnel barrier. Installing this RAM chip together with a Josephson processor permitted the functions of a computer, including a memory access, to be successfully demonstrated. The access time was found to be 500-520 ps by measuring a test chip     

A programmable CORDIC chip for digital signal processingapplications

A chip implementing the coordinate rotation digital computer (CORDIC) algorithm is described. It contains a 10-MHz 16-b fixed-point CORDIC arithmetic unit, 2-kb RAM, a controller, and input/output (I/O) registers. A modified data-path architecture allows cross-wire free data flow. The chip design involved development of optimized carry-select adders and a modified programmable-logic-array (PLA) cell layout, which allows speed increase in single-layer metal technology. The authors designed, fabricated, and tested a general-purpose fully parallel programmable CORDIC chip in CMOS technology and developed optimal iteration sequences     

The design of a fully integrated graphics system

The architecture and design of a CMOS chip implementing a medium-resolution graphics system are described. The chip, requiring no external support logic, outputs analog RGB signals at a 40-MHz pixel rate and directly controls a bit-map video RAM (VRAM) memory array. Scan rates and display formats are completely programmable. Pixels stored in the 1 K×1 K bit map can be any of 16 colors taken from a 4096-color palette. The chip can be directly interfaced to most common microprocessors. A 6.7-MIPS (million-instruction-per-second) internal reduced instruction set computer (RISC) CPU directly implements high-level graphics commands. The chip achieves a maximum draw speed of 10 million pixels/s. Designed in a Lisp machine environment, the 100000-transistor chip is implemented in 1.8-μm CMOS and contains standard cells, RAM, ROM, a color table, and three four-bit current-steered digital-to-analog converters (DACs)     

铁电存储器在存储测试系统中的应用

为了实现环境试验的存储测试系统,采用了FRAM存储器M28W640结合SOC片上系统C8051F340的设计,通过分析其性能和接口电路,编写了相应的读写程序。由于这种并行非易失性存储测试技术方式具有高速读写、超低功耗、几乎无限次擦写,读写程序编写简便的优点,非常适合在此类存储测试系统中使用。     

Comments on “some considerations in the formulation of IC yield statistics”

The paper by Hu[1] critiqued the basis of integrated circuit yield theory. Capitalizing on Hu's work, the present paper shows that by developing the model from a large sample statistical point of view, it is possible to widen the scope of Hu's approach. This widened approach allows the inclusion of different defect mechanisms with variations in defect sensitivities over a chip. The model also allows approximations for chip-to-chip variations by using resulting continuous fault density distributions.The model thus obtained predicted that the logarithm of yield versus chip area relationship could show a downward curvature rather than the upward curvature obtained by previous theories. Data from two different integrated circuit factories is shown to confirm this prediction.