Leakage current mechanisms in SiGe HBTs fabricated using selectiveand nonselective epitaxy

SiGe heterojunction bipolar transistors (HBTs) have been fabricated using selective epitaxy for the Si collector, followed in the same growth step by nonselective epitaxy for the p⁺ SiGe base and n-Si emitter cap. DC electrical characteristics are compared with cross-section TEM images to identify the mechanisms and origins of leakage currents associated with the epitaxy in two different types of transistor. In the first type, the polysilicon emitter is smaller than the collector active area, so that the extrinsic base implant penetrates into the single-crystal Si and SiGe around the perimeter of the emitter and the polycrystalline Si and SiGe extrinsic base. In these transistors, the Gummel plots are near-ideal and there is no evidence of emitter/collector leakage. In the second type, the collector active area is smaller than the polysilicon emitter, so the extrinsic base implant only penetrates into the polysilicon extrinsic base. In these transistors, the leakage currents observed depend on the base doping level. In transistors with a low doped base, emitter/collector and emitter/base leakage is observed, whereas in transistors with a high doped base only emitter/base leakage is observed. The emitter/collector leakage is explained by punch through of the base caused by thinning of the SiGe base at the emitter perimeter. The emitter/base leakage is shown to be due to a Poole-Frenkel mechanism and is explained by penetration of the emitter/base depletion region into the p⁺ polysilicon extrinsic base at the emitter periphery. Variable collector/base reverse leakage currents are observed and a variety of mechanisms are observed, including Shockley-Read-Hall recombination, trap assisted tunneling, Poole-Frenkel and band to band tunneling. These results are explained by the presence of polysilicon grains on the sidewalls of the field oxide at the collector perimeter     

Characterisation of emitter/base leakage currents in SiGe HBTs produced using selective epitaxy

SiGe heterojunction bipolar transistors have been fabricated using selective epitaxy for the Si collector, followed in the same growth step by non-selective epitaxy for the SiGe base and Si emitter cap. E/B leakage currents are compared with cross-section TEM images to identify sources of leakage currents associated with the epitaxy. In addition, the influence of the position of the extrinsic base implant with respect to the polysilicon emitter on the leakage currents is studied. The emitter/base leakage currents are modelled using Shockley–Read–Hall recombination, trap-assisted tunnelling and Poole–Frenkel (PF) generation. The position of the extrinsic base implant is shown to have a strong influence on the leakage currents. The PF effect dominates the emitter/base leakage current in transistors in which the collector area is smaller than the polysilicon emitter. This result is explained by penetration of the emitter/base depletion region into the p⁺ polysilicon extrinsic base at the perimeter of the emitter. These leakage currents are eliminated when the collector area is increased so that the extrinsic base implant penetrates into the single-crystal silicon at the perimeter of the emitter.     

The benefits of fluorine in pnp polysilicon emitter bipolartransistors

BF₂ implantation into polysilicon and its subsequent rapid thermal diffusion into single crystal silicon is commonly used for the fabrication of pnp polysilicon emitter bipolar transistors. In this paper the effect of the fluorine, which is introduced into the polysilicon during the BF₂ implant, is investigated. Pnp polysilicon emitter bipolar transistors are fabricated in which the boron and fluorine are implanted separately, with the fluorine only going into one half of each wafer. Electrical results show that fluorine has two interrelated effects. In devices given a low thermal budget emitter drive-in, a drop in base current by a factor of approximately 3.2 is observed when the fluorine is present, together with an improvement in the ideality of the base characteristics. This is explained by the passivation of trapping states at the polysilicon/silicon interface by the fluorine. In contrast, in devices-given a higher thermal budget emitter drive-in, an increase in base current by a factor of approximately 2.5 is observed, when fluorine is present. This is explained by the action of the fluorine in accelerating the breakup of the interfacial layer. A model is proposed to explain this behavior     

Process investigations for a 30-GHz fT submicrometerdouble poly-Si bipolar technology

Major process issues are investigated to establish a manufacturable process for a 30-GHz f_T deep-trench isolated submicrometer double polysilicon bipolar technology. A thinner deep-trench surface oxide minimizes crystal defects generated by thermal stresses during the subsequent processes, and significantly improves collector-to-emitter leakage currents in npn transistors. The effects of reactive-ion-etch (RIE) process used for the base surface oxide etch are evaluated in terms of current gain, emitter resistance, and cutoff frequency of the npn transistors. Silicon surface roughness created by an RIE process produces a nonuniform interface oxide film between the emitter polysilicon and the silicon surface, which results in a lower current gain due to a retardation of arsenic diffusion from the emitter polysilicon through the unbroken thicker portion of the interface oxide film. Lateral pnp transistors and Schottky diodes using a vanadium silicide are characterized as a function of epitaxial layer thickness. Schottky diodes are integrated with high performance npn transistors without using extra photo-masking process steps. The reverse leakage currents of Schottky diodes fabricated by using an RIE process are acceptable for practical use in circuits. A planarization process is investigated by employing an RTA reflow of BPSG films deposited in an LPCVD furnace. The maximum RTA reflow temperature is limited to 1000°C in order to maintain an acceptable integrity of TiSi₂ layer formed on top of the n+ polysilicon layer. The planarity achieved by an RTA reflow at a temperature between 975°C and 1000°C is acceptable for double polysilicon bipolar integrated circuits using metal interconnects produced by an electroplated gold process     

Low-frequency noise in polysilicon emitter bipolar transistors

The low-frequency noise in polysilicon emitter bipolar transistors is investigated. Transistors with various geometries and various properties of the oxide layer at the monosilicon polysilicon interface are studied. The main 1/f noise source proved to be located in the oxide layer. This source causes both 1/f noise in the base current S_Ib and 1/f noise in the emitter series resistance S_re The magnitude of the 1/f noise source depends on the properties of the oxide layer. The 1/f noise is ascribed to barrier height fluctuations of the oxide layer resulting in transparency fluctuations for both minority and majority carriers in the emitter, giving rise to S_Ib and S _re respectively. It is also shown that a low transparency of the oxide layer also reduces the contribution of mobility fluctuations to S_Ib     

Process and device characterization for a 30-GHz fT submicrometer double poly-Si bipolar technology using BF2-implanted base with rapid thermal process

Process and device parameters are characterized in detail for a 30-GHz f_T submicrometer double poly-Si bipolar technology using a BF₂-implanted base with a rapid thermal annealing (RTA) process. Temperature ramping during the emitter poly-Si film deposition process minimizes interfacial oxide film growth. An emitter RTA process at 1050°C for 30 s is required to achieve an acceptable emitter-base junction leakage current with an emitter resistance of 6.7×10^-7 Ω-cm², while achieving an emitter junction depth of 50 nm with a base width of 82 nm. The primary transistor parameters and the tradeoffs between cutoff frequency and collector-to-emitter breakdown voltage are characterized as functions of base implant dose, pedestal collector implant dose, link-base implant dose, and epitaxial-layer thickness. Transistor geometry dependences of device characteristics are also studied. Based on the characterization results for poly-Si resistors, boron-doped p-type poly-Si resistors show significantly better performance in temperature coefficient and linearity than arsenic-doped n-type poly-Si resistors     

Fluorine effects in n-p-n double-diffused polysilicon emitterbipolar transistors

We demonstrate that fluorine incorporation in the polysilicon emitter of n-p-n double-diffused bipolar transistors during BF₂ implantation at a dose of 1×10¹⁵ cm^-2 significantly alters the device electrical characteristics. In particular, tunneling emitter/base currents are observed at both forward and reverse voltages, due to excessive base dopant concentration at the junction. Fluorine-enhanced interfacial oxide break-up and epitaxial realignment of the poly-Si emitter are shown to be responsible for these results     

Polysilicon emitter p-n-p transistors

In-situ boron-doped polysilicon has been used to form the emitter in p-n-p transistors. Various polysilicon deposition conditions, interface preparation treatments prior to deposition, and post-deposition anneals were investigated. Unannealed devices lacking a deliberately grown interfacial oxide gave effective emitter Gummel numbers G_E of 7-9×10^-12s cm^-4 combined with emitter resistances R_E of approximately 8 μΩcm². Introduction of a chemically grown interfacial oxide increased G_E to 2×10 ¹⁴s cm^-4, but also raised R_E by a factor of three. Annealing at 900°C following polysilicon deposition raised G_E values for transistors lacking deliberate interfacial oxide to approximately 6×10¹³s cm^-4, but had little effect of G_E for devices with interfacial oxide. Both types of annealed devices gave R_E values in the range 1-2 μΩcm²     

Low-frequency noise characteristics of UHV/CVD epitaxial Si- andSiGe-base bipolar transistors

We report the first measurements of low-frequency noise in high-performance, UHV/CVD epitaxial Si- and SiGe-base bipolar transistors. The magnitude of the noise power spectral density at fixed frequency for both Si and SiGe devices is comparable for similar bias, geometry, and doping conditions, indicating that the use of strained SiGe alloys does not degrade transistor noise performance. The best recorded values of noise corner frequency were 480 Hz and 373 Hz for the Si and SiGe transistors, respectively, for multi-stripe devices with an emitter area of 0.5×10.0×3 μm². A functional dependence of the noise power spectral density on base current for both device types of I_B^1.90 was observed, and noise measurements as a function of device geometry suggest that the contributing noise sources are uniformly distributed across the emitter of the transistors, not at the emitter periphery     

Silicon npn bipolar transistors with indium-implanted base regions

In this paper, silicon npn bipolar transistors with indium-implanted base regions are discussed. Polysilicon emitter bipolar transistors are fabricated using a standard 0.5-μm BIC-MOS process flow where the base BF₂ implant is replaced by an indium implant. In indium-implanted transistors, the integrated hole concentration (G_b) in the quasi-neutral base is reduced due to incomplete ionization of indium acceptor states. The novel utilization of this impurity freeze-out effect results in much increased collector currents and common-emitter transistor gains (h_fe) compared to boron-implanted transistors. Also, since indium acceptor states in depletion regions become fully ionized, the spreading of the reverse-biased collector-base junction depletion region into the transistor base (base-width modulation) is minimized. Hence, for indium base bipolar transistor an improved h_fe-V_A product is anticipated. Our first attempt at fabricating bipolar transistors with indium-implanted base regions resulted in devices with greatly increased collector current, impressive gains of h_fe≈1600, excellent collector current saturation characteristics, an Early Voltage of V_A≈10 V, h_fe-V_A product of 16000 (implying an extended device design space), base-emitter breakdown voltages of BV_EBO≈9.6 V, and a cut-off frequency of f_t=17.8 GHz     

Lateral base design rules for optimized low-frequency noise of differentially grown SiGe heterojunction bipolar transistors

The low-frequency noise dependence on lateral design parameters was investigated for SiGe heterojunction bipolar transistors fabricated by differential epitaxy. The low-frequency noise was found to vary substantially as a function of the extrinsic base design. The dominant noise sources were located either at the interface between the polycrystalline and epitaxial Si/SiGe base, in the epitaxial Si/SiGe base link region, in the base–emitter depletion region, or at the thin SiO₂ interface layer between the polysilicon and monosilicon emitter. Boron was found to passivate interfacial traps, acting as low-frequency noise sources. Generation–recombination noise with a strong dependence on the lateral electrical field was observed for some of the designs.     

Theoretical small-signal performance of Si/SiGe/Si HBT

Application of the Monte Carlo technique to analyze electron and hole transport in bulk Si_0.8Ge_0.2 and strained Si _0.8Ge_0.2/Si is discussed. The computed minority- and majority-carrier transport properties were used in a comprehensive small-signal model to evaluate the high-frequency performance of a state-of-the-art n-p-n heterostructure bipolar transistors (HBT) fabricated with SiGe as the base material. The valence band discontinuity of a SiGe-base HBT reverses the degradation in emitter injection efficiency caused by bandgap narrowing in the base, and permits a higher ratio of base doping to emitter doping than would be practical for a bipolar transistor. Any degradative effect of increased base doping on electron and hole mobilities is offset by improved transport in the strained SiGe base, resulting in a marked decrease in the base resistance and base transit time. Compared to the Si BJT, the use of Si_0.8Ge_0.2 for the base region of an HBT leads to significant improvements in low-frequency common emitter current gain, low-frequency unilateral power gain, and maximum oscillation frequency     

Polycrystalline silicon-germanium emitters for gain control, with application to SiGe HBTs

This paper investigates germanium incorporation into polysilicon emitters for gain control in SiGe heterojunction bipolar transistors. A theory for the base current of a polySiGe emitter is developed, which combines the effects of the polySiGe grains, the grain boundaries and the interfacial layer at the polySiGe/Si interface into an expression for the effective surface recombination velocity of a polySiGe emitter. Silicon bipolar transistors are fabricated with 0, 10 and 19% Ge in the polySiGe emitter and the variation of base current with Ge content is characterized. The measured base current for a polySiGe emitter increases by a factor of 3.2 for 10% Ge and 4.0 for 19% Ge compared with a control transistor containing no germanium. These values are in good agreement with the theoretical predictions. The competing mechanisms of base current increase by Ge incorporation into the polysilicon and base current decrease due to an interfacial oxide layer are investigated.     

Low-frequency noise in UHV/CVD epitaxial Si and SiGe bipolartransistors

In this work a comprehensive investigation of low-frequency noise in ultrahigh vacuum/chemical vapor deposition (UHV/CVD) Si and SiGe bipolar transistors is presented. The magnitude of the noise of SiGe transistors is found to be comparable to the Si devices for the identical profile, geometry, and bias. A comparison with different technologies demonstrates that the SiGe devices have excellent noise properties compared to AlGaAs/GaAs heterojunction bipolar transistors (HBT's) and conventional Si bipolar junction transistors (BJT's). Results from different bias configurations show that the 1/f base noise source is dominant in these devices. The combination of a 1/Area dependence on geometry and near quadratic dependence on base current indicates that the 1/f noise sources are homogeneously distributed over the entire emitter area and are probably located at the polysilicon-Si interface. Generation/recombination (Gm) noise and random telegraph signal (RTS) noise was observed in selected Si and SiGe devices. The bias dependence and temperature measurements suggest that these G/R centers are located in the base-emitter space charge region. The activation energies of the G/R traps participating in these noise processes were found to be within 250 meV of the conduction and valence band edges     

Trade-off between emitter resistance and current gain inpolysilicon emitter bipolar transistors with intentionally growninterfacial oxide layers

Experimental measurements of emitter resistance and current gain in polysilicon emitter bipolar transistors that have received annealing to break up an intentionally grown RCA oxide interfacial layer are presented. An anneal of 900°C for 10 min in a nitrogen ambient of the interfacial layer prior to polysilicon doping resulted in a decrease in emitter resistance by approximately a factor of 5, with an increase in base saturation current of only 25% while still maintaining a current gain of around 500. The authors believe that this is the largest trade-off in emitter resistance versus current gain demonstrated so far for polysilicon transistors with an RCA interfacial layer. These results support a theory previously proposed by the authors (1991) predicting that significant trade-offs between emitter resistance and current gain can be obtained if an intentionally grown interfacial oxide layer in polysilicon emitter bipolar transistors is annealed so as to induce only partial breakup such that most of the layer remains intact     

Band-gap narrowing and high-frequency characteristics ofSi/GexSi1-x heterojunction bipolar transistorsformed by Ge ion implantation in Si

Si/Ge_xSi_1-x heterojunction n-p-n bipolar transistors (HBT's) with a double-polysilicon self-aligned structure were fabricated by using high dose Ge implantation for the formation of the Si/Ge_xSi_1-x heterostructure and As and BF₂ implantation for emitter and base doping. DC and high frequency electrical characteristics are investigated for Ge concentrations up to 7 at.% and for base widths down to 35 nm. Improvements in electrical characteristics compared to reference Si transistors are demonstrated. Experimental data indicating that these improvements are related to an effective band gap engineering are shown and discussed     

1/f noise characterization of base current and emitter interfacialoxide breakup in n-p-n polyemitter bipolar transistors

We propose using base 1/f noise to characterize the distribution of diffusion and tunneling components of base-current (I_b) at the emitter poly/monosilicon interface in n-p-n polyemitter transistors. A noise model is constructed to interpret the I_b 1/f noise (S _iEB) dependence on these combined currents. Measured I_b dependences of S_iEB increase progressively from I_b^1.2 to I_b^2.0 for transistors having emitter structures concomitant with increasing current gains and series emitter resistances ranging between 115-1800 and 7-33Ω, respectively. This is indicative of tunneling components in I_b^2.0 that increase with higher interfacial oxide continuity, and persist in epitaxially realigned emitters     

Location of 1/f noise sources in BJT's and HBJT's—I. theory

The most general case of1/fnoise in transistors can be described by three independent noise current generators: ibebetween base and emitter, ibcbetween base and collector, and iecbetween emitter and collector. By short-circuiting the base and the collector to ground and comparing the base and collector noise spectraS_{IB}(f)andS_{IC}(f)for the case of zero feedback from the emitter with the base and collector noise spectraS'_{IB}(f)andS'_{IC}(f)for the case of strong feedback from the emitter, one can evaluate the relative strength of the three noise sources. By measuring the current dependence ofS_{IB}(f),S_{IC}(f),S'_{IB}(f), andS'_{IC}(f), one can assign physical processes to the current generators ibc, ibe, and iec. It is the aim of this paper to demonstrate theoretically a simple method for locating1/fnoise sources in BJT's and HBJT's by comparing the base and collector1/fnoise for the cases without and with strong emitter feedback. In later papers we shall demonstrate experimentally how this method is applied to practical situations.     

Determination of bandgap narrowing and parasitic energy barriers inSiGe HBT's integrated in a bipolar technology

This paper describes a method for characterizing the bandgap narrowing and parasitic energy barrier in SiGe heterojunction bipolar transistors (HBTs), fabricated using a single-polysilicon self-aligned bipolar process. From a comprehensive study of the temperature dependence of the collector current, the bandgap narrowing in the base due to germanium has been dissociated from that due to the heavy dopant concentration. The same approach has been used to characterize the height and width of parasitic energy barriers which appear when boron out-diffusion from the SiGe base is present. The method has been applied to SiGe heterojunction bipolar transistors fabricated using a single polysilicon, self-aligned, bipolar process, as well as mesa transistors. The experimental results show that small geometry transistors have degraded collector currents due to boron out-diffusion around the perimeter of the emitter. This behavior has been explained by accelerated boron diffusion due to point defects generated during the extrinsic base implant. The values of undoped SiGe spacer thickness needed to suppress the parasitic energy barrier are described. Finally, high-frequency results are reported, which correlate the frequency transition to these parasitic energy barriers     

Effect of interfacial oxide thickness on 1/f noise in polysilicon emitter BJTs

The role of the interfacial oxide (IFO) between the polysilicon and monosilicon emitter regions on the noise behavior of n-p-n poly-emitter bipolar transistors was investigated through 1/f noise measurements. Bipolar junction transistors with different IFO thickness, and emitter geometry were utilized. Measurements with variable external base bias resistance (R/sub S/) were used to investigate the relative contribution of each individual noise source from the base current (S/sub IB/), the collector current (S/sub IC/) and, the internal emitter and base series resistances (S/sub Vr/). When the voltage noise power spectral densities S/sub VC/ and S/sub VB/ were measured across resistances in series with the collector and base, respectively, using a relatively large R/sub S/ (/spl sim/1 M/spl Omega/), S/sub IB/ was found to have the dominant noise contribution at lower bias currents. On the other hand, when the voltage noise power spectral densities S/sub VC/ and S/sub VE/ were measured across resistances in series with the collector and emitter, respectively, in a different experimental setup with a low R/sub S/ value, S/sub Vr/ was found to have the dominant noise contribution at higher bias currents. IFO was found to increase S/sub IB/, S/sub IC/, and S/sub Vr/. S/sub IB/ was modeled as a combination of tunneling and diffusion fluctuations of the minority carriers in the emitter; whereas S/sub IC/ was modeled as a combination of number and diffusion fluctuations of the minority carriers in the base. S/sub Vr/ was attributed to the internal emitter resistance noise originating from the fluctuation in the majority carrier flow through the IFO.