Subthreshold properties of TFTs with laser-crystallized laterally grown polysilicon layers

Trap-density analysis of laterally grown polysilicon films formed by continuous-wave laser revealed the main factor that controls the subthreshold property of low-temperature polysilicon thin-film transistors. In the low-current region, traps at the gate oxide/polysilicon interface are charged and the consequent insensitiveness of polysilicon surface potential to gate bias dominates the subthreshold property. In the higher current region, that is, close to the threshold voltage, a transport mechanism in which carriers are scattered at the grain boundaries becomes the dominant factor governing the subthreshold property.     

Observation of high interface state densities at the silicon/oxide interface for low doped polysilicon/oxide/silicon capacitor structures

In this work, we present new observations noted in the capacitance–voltage behaviour of polysilicon/oxide/silicon capacitor structures. As the active doping concentration reduces in the polysilicon layer, an anomalous capacitance–voltage behaviour is measured which is not related directly to depletion into the polysilicon gate. From examination of the frequency dependence of the capacitance–voltage characteristic, in conjunction with analysis and simulation, the anomalous capacitance–voltage behaviour is explained by the presence of a high density of near-monoenergetic interface states located at the silicon/oxide surface. The density and energy level of the interface states are determined. Furthermore, the work presents a mechanism by which the polysilicon doping level can impact on the properties of the silicon/oxide interface.     

Physics, technology, and modeling of polysilicon emitter contacts for VLSI bipolar transistors

The physics of minority-carrier injection into polysilicon-contacted emitters has been studied through a series of experiments correlating the base current of the transistor to the structure of the polysilicon/single-crystal silicon interface. Most of the relevant material and processing parameters have been examined. In addition, a novel approach has been taken in the modeling of transport in these emitters to quantify the minority-carrier blocking properties of the polysilicon contacts. Experimental results show that extremely low values of base current can be obtained for devices etched in HF prior to the polysilicon deposition, i.e., devices with only a remnant "native" oxide layer at the polysilicon/single-crystal silicon interface. For these devices, the base current is mainly determined by the recombination and blocking of minority carriers at the polysilicon/monosilicon interface. A number of competing mechanisms exist in several domains of doping, temperature, and time which influence the properties of this interface. One of these mechanisms is the blocking of minority carriers by the native oxide layer itself. The uniformity and, consequently, the blocking characteristics of this layer were found to be strongly affected by the polysilicon doping level and thermal treatment.     

A simple method for extracting average doping concentration in thepolysilicon and silicon surface layer near the oxide in polysilicon-gateMOS structures

The author demonstrates a simple technique that extracts average doping concentration in the polysilicon and silicon near the oxide in a metal/polysilicon/oxide/silicon system. The technique is based on the maximum-minimum capacitance method on two large area structures-one MOSFET and one MOSC (MOS capacitor). The technique is simple and reliable since only three data points in the C-V data are required-two points in MOSC C-V and one point in MOSFET C-V. The technique avoids inaccuracy caused by interface traps at the polysilicon/oxide and the oxide/silicon interface. The technique can be implemented into fab routine electric-test procedures for simultaneously monitoring change of doping concentration in polysilicon and silicon during process development     

多晶硅注氮制备4.6nm超薄栅介质

为了改善深亚微米CMOS器件p+ - poly栅中硼扩散问题,通过选择合适的注氮能量和剂量,采用多晶硅栅注氮工艺,既降低了硼在多晶硅栅电极中的扩散系数,又在栅介质内引入浓度适宜的氮,有效地抑制了硼在栅介质内的扩散所引起的平带电压漂移,改善了Si/Si O2 界面质量,提高了栅介质和器件的可靠性,制备出了性能良好的4 .6 nm超薄栅介质.     

In-situ processing using rapid thermal chemical vapor deposition

Metal-Oxide-Semiconductor Capacitors (MOSCAP’s) were fabricated using Rapid Thermal Processing (RTP) techniques. MOSCAP’s that received in-situ polysilicon gate deposition after oxide growth evinced significantly tighter oxide breakdown voltage distribution as compared to devices that received ex-situ polysilicon deposition. Capacitance-Voltage (C-V) measurements of electrically unstressed and stressed devices indicate that the oxide charge, interface state density, electron trapping, and interface state generation characteristics are identical, irrespective of the mode of polysilicon gate deposition. It is concluded that, while in-situ processing may be capable of reducing particle related defects, no improvement is seen in the intrinsic properties of the oxide itself.     

Model of low frequency noise in polycrystalline silicon thin-filmtransistors

A model for the low frequency noise of polycrystalline silicon thin film transistors (polysilicon TFTs) is proposed. The model takes into account fluctuations of the grain boundary potential barrier induced by those of the grain boundary interface charge and fluctuations of carriers due to trapping in oxide traps located close to the interface. Using the proposed model, it is demonstrated that both grain boundary and oxide traps can be determined in polysilicon TFTs from noise measurements     

High frequency space charge layer capacitance of strongly inverted semiconductor surfaces

The finite spatial extension of the inversion layer minority carriers shunts the dielectric capacitance of the inversion layer and increases the high frequency semiconductor surface space charge layer capacitance in the strong inversion range by about 5 per cent. This distributed minority carrier distribution also gives rise to a small (about 1 per cent) high frequency capacitance minimum near the onset of strong surface inversion. A simple two-lump model is developed which is accurate to within 0·4 per cent of the numerical solution obtained from the exact transmission line model. Applied gate voltages at the capacitance minimum are presented graphically as a function of oxide thickness with the substrate impurity concentration as a parameter. Surface quantization effect is not taken into account.     

双掺杂多晶Si栅MOSFET的截止频率研究

在前期对双掺杂多晶Si栅(DDPG)LDMOSFET的电场、阈值电压、电容等特性所作分析的基础上,仍然采用双掺杂多晶Si栅结构,以低掺杂漏/源MOS(LDDMOS)为基础,重点研究了DDPG-LDDMOSFET的截止频率特性.通过MEDICI软件,模拟了栅长、栅氧化层厚度、源漏区结深、衬底掺杂浓度以及温度等关键参数对器件截止频率的影响,并与相同条件下P型单掺杂多晶Si栅(p-SDPG)MOSFET的频率特性进行了比较.仿真结果发现,在栅长90 nm、栅氧厚度2 nm,栅极P,n掺杂浓度均为5×1019cm-3条件下,截止频率由78.74 GHz提高到106.92 GHz,幅度高达35.8%.此结构很好地改善了MOSFET的频率性能,得出的结论对于结构的设计制作和性能优化具有一定的指导作用,在射频领域有很好的应用前景.     

Influence of a resistive sublayer at the polysilicon/silicon dioxide interface on MOS properties

We suggest that a thin (≥100 Å) resistive sublayer of polysilicon neat the oxide interface can have a pronounced effect on the MOS capacitances-voltage characteristics. On the depletion side of theC-Vcurve, the lower effective work-function difference leads to a higher threshold for strong inversion. On the accumulation side, the MOS capacitance is lowered due to the added thickness of the depletion sublayer. With the help of the sublayer model, we attempt to explain the anomalous behavior often observed in MOS capacitors with silicide/polysilicon gates. The sublayer depletion activates traps due to the heavy impurities (Cu, Fe, and Ta) at the interface, a considerable amount of which were observed in these samples by Auger spectroscopy.     

Dynamic hot-carrier induced degradation in n-channel polysilicon thin-film transistors

The effects of hot-carriers under dynamic stress on the transfer characteristics and the noise performance of n-channel polysilicon thin-film transistors are analysed. The observed decrease in the on-state current is directly related to the mobility of a damaged region extended over a length of about 0.53 μm beside the drain, which is evaluated through analysis of the transfer characteristics at low drain voltage. The mobility degradation in the damaged region is due to the formation of traps located near the polysilicon/gate oxide interface as evidenced by the 1/f noise measurements.     

一种新型的CMOS集成湿度传感器

利用MEMS技术 ,对一种新型CMOS湿度传感器进行理论分析、模拟以及结果讨论。该湿度传感器采用标准CMOS工艺制造 ,采用梳状铝电极结构、梳状多晶硅加热结构 ,衬底接地 ,感湿介质采用聚酰亚胺 ,利用商业软件Coventor进行模拟绘制出敏感电容与相对湿度的曲线图。接口电路采用开关电容电路 ,输出可测电压信号 ,利用Microsim公司的Pspice模拟电路得到相对湿度与输出电压曲线关系     

The honeycomb-shape capacitor structure for ULSI DRAM

A way to increase the charge stored in polysilicon capacitors using surface modulation technology is proposed. Asperities on the polysilicon surface are achieved by reactive ion etching (RIE) of the polysilicon, using the oxide at the grain boundary as a mask. The fabricated polysilicon electrode has a honeycomb shape. With this structure, the capacitance is increased by four times for a polysilicon storage electrode of 250-nm thickness. The leakage current is comparable to that of convection stacked capacitors (STCs)     

Polysilicon emitters for bipolar transistors: a review andre-evaluation of theory and experiment

A critical review is presented of the theories proposed in the literature to explain the current gain enhancement of polysilicon emitter bipolar transistors. From these theories a simplified analytical formulation is chosen which models the blocking properties of the interface, including tunneling through the interfacial oxide, reduced grain boundary mobility at the polysilicon/silicon interface, and the potential barrier created by segregated dopant, which can all give rise to an enhanced current gain. Also modeled are the mechanisms which limit the extent of any gain enhancement, such as recombination in the single-crystal emitter, in the bulk of the polysilicon, and at the polysilicon/silicon interface. This model is then applied in an original manner to a selection of experimental data in an effort to identify the dominant current gain mechanisms in polysilicon emitter transistors as a function of a given set of fabrication conditions     

Anomalous C-V characteristics of implanted polyMOS structure in n+/p+ dual-gate CMOS technology

The C-V characteristics of arsenic-doped polysilicon show a gate-bias dependence of the inversion capacitance and a reduction in the expected value of the inversion capacitance. The characteristics have been investigated with quasistatic and high-frequency C-V as well as conductance measurements of various capacitors that have been subjected to annealing times and temperatures ranging from 900°C/30 min to rapid thermal annealing at 1050°C. The results can be explained by assuming that there is a depletion region forming in the polysilicon due to insufficient activation of the dopant at the polysilicon/oxide surface. The impact of this condition on the device characteristics is shown to be a 20-30% reduction in the G_m of NMOS transistors with 125-Å Gate oxide thickness     

Low-frequency noise in polysilicon emitter bipolar transistors

The low-frequency noise in polysilicon emitter bipolar transistors is investigated. Transistors with various geometries and various properties of the oxide layer at the monosilicon polysilicon interface are studied. The main 1/f noise source proved to be located in the oxide layer. This source causes both 1/f noise in the base current S_Ib and 1/f noise in the emitter series resistance S_re The magnitude of the 1/f noise source depends on the properties of the oxide layer. The 1/f noise is ascribed to barrier height fluctuations of the oxide layer resulting in transparency fluctuations for both minority and majority carriers in the emitter, giving rise to S_Ib and S _re respectively. It is also shown that a low transparency of the oxide layer also reduces the contribution of mobility fluctuations to S_Ib     

Investigation of the doping and thickness effects of polysilicon oxide by rapid thermal N2O oxidation

In this paper, polyoxides were grown on n+ doped polysilicon by using rapid thermal N₂O processing. The doping level of the lower polysilicon layer and the polyoxide thickness effect were investigated. Results showed that N₂O oxide grown on medium-doped polysilicon layer exhibited better characteristics than that grown on heavily-doped polysilicon layer. The polyoxide/polysilicon interface of the polyoxide grown on the heavily doped bottom poly-1 layer is smoother than that of the medium doped polyoxide, apparently due to the phosphorus concentration which facilitates SiO₂ viscous flow and prevents oxide thinning and horn formation. However, despite the smoother interface, a large amount of phosphorus via out-diffusion after subsequent oxidation process accumulates at the polysilicon/polyoxide interface and is incorporated into the polyoxide, degrading the oxide quality. Therefore, to obtain better characteristics from N₂O polyoxide grown on a medium-doped polysilicon layer, an appropriate amount of phosphorus and nitrogen should be incorporated. Further, the thicker the oxide, the worse the characteristics, due to the longer oxidation time, which results in a rougher interface, leading to larger charge trapping and smaller Qbd.     

Self-aligned transistors with polysilicon emitters for bipolar VLSI

A new bipolar process technology for fabricating self-aligned transistors with polysilicon contacted emitters is described. The extrinsic base regions of the transistor are self-aligned to the emitter contact by exploiting the effects of concentration-dependent oxidation to selectively oxidize the polysilicon. The shallow emitter is fabricated with a thin oxide layer at the polysilicon-silicon interface, thereby enhancing the emitter efficiency and thus the current gain of the device. It is demonstrated that this gain enhancement can be traded for a considerable increase in active base doping, with a resulting decrease in base resistance and potential improvement in switching performance. Under certain circumstances, non-ideal electrical characteristics can be obtained from the self-aligned transistor which are caused by lateral spread of the extrinsic base region beneath the sidewall oxide of the polysilicon emitter contact. This leads to the formation of p⁺-n⁺junction at the periphery of the emitter and hence to tunneling of carriers across this region. It is shown that the same tunneling mechanism also limits the extent to which the active base doping can be increased. In order to avoid the formation of the peripheral p⁺-n⁺junction, a polysilicon base contact is employed which allows a self-aligned extrinsic base region to be fabricated with negligible lateral movement.     

Self-Aligned Transistors with Polysilicon Emitters for Bipolar VLSI

A new bipolar process technology for fabricating self-aligned transistors with polysilicon contacted emitters is described. The extrinsic base regions of the transistor are self-aligned to the emitter contact by exploiting the effects of concentration-dependent oxidation to selectively oxidize the polysilicon. The shallow emitter is fabricated with a thin oxide layer at the polysilicon-silicon interface, thereby enhancing the emitter efficiency and thus the current gain of the device. It is demonstrated that this gain enhancement can be traded for a considerable increase in active base doping, with a resulting decrease in base resistance and potential improvement in switching performance. Under certain circumstances, non-ideal electrical characteristics can be obtained from the self-aligned transistor which are caused by lateral spread of the extrinsic base region beneath the sidewall oxide of the polysilicon emitter contact. Tlris leads to the formation of p/sup +/ -n/sup +/ junction at the periphery of the emitter and hence to tunneling of carriers across this region. It is shown that the same tunneling mechanism also limits the extent to which the active base doping can be increased. In order to avoid the formation of the peripheral p/sup +/-n/sup +/ junction, a polysilicon base contact is employed which allows a self-aligned extrinsic base region to be fabricated with negligible lateral movement.     

Impact of boron penetration at P+-poly/gate oxideinterface on deep-submicron device reliability for dual-gate CMOStechnologies

In this paper, we investigate the onset of boron penetration at the P⁺-poly/gate oxide interface. It is found that conventional detection methods such as shifts in flatband voltage or threshold voltage (V_t) and charge-to-breakdown (Q_BD) performance in accumulation mode failed to reveal boron species near this interface. On the contrary, under constant current stressing with inversion mode bias conditions, significantly lower Q_BD and large V_t shift have been observed due to boron penetration near the P⁺-poly/gate oxide interface. These results suggest that onset of boron penetration at the P⁺ -poly/gate oxide interface does not alter fresh device characteristics, but it induces severe reliability degradation for the gate oxide. Tradeoffs of boron penetration and poly depletion are also studied in this work with different combinations of polysilicon thickness, BF₂ implant energy and dose, and the post-implant RTA temperature