A 0.5-8.5 GHz fully differential CMOS distributed amplifier

A fully integrated fully differential distributed amplifier with 5.5 dB pass-band gain and 8.5 GHz unity-gain bandwidth is described. The fully differential CMOS circuit topology yields wider bandwidth than its single-ended counterpart, by eliminating the source degeneration effects of parasitic interconnect, bond wire, and package inductors. A simulated annealing CAD tool underpins the parasitic-aware methodology used to optimize the design including all on-chip active and passive device and off-chip package parasitics. Mixed-mode S-parameter measurement techniques used for fully differential circuit testing are reviewed. Integrated in 1.3/spl times/2.2 mm/sup 2/ in a standard 0.6 /spl mu/m CMOS process, the distributed amplifier dissipates 216 mW from a single 3 V supply.     

A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop

A 1.5-V 5.5-GHz fully integrated phase-locked loop (PLL) has been implemented in a 0.25-μm foundry digital CMOS process. From a 5.5-GHz carrier, the in-band phase noise can be as low as -88 dBc/Hz at a 40-kHz offset, while the phase noise for the free-running VCO is -116 dBc/Hz at an 1-MHz offset. The VCO core current is 4.6 mA. The prescaler is implemented using a variation of the source-coupled logic (SCL) structure to reduce the switching noise, and thus to reduce the PLL side-band spurs. At -18 dBm signal power measured off chip, the switching noise coupled through substrate and metal interconnect generates spurs with power levels less than -99 dBm when the loop is open. A new charge-pump circuit is developed to reduce the current glitch at the output node. By incorporating a voltage doubler, the voltage dynamic range at the charge-pump output and thus the VCO control voltage range is increased from 1.3 to 2.6 V with immeasurable phase noise and spurious level degradation to the PLL. When the loop is closed, the power levels of side-band spurs at the offset frequency equal to the ~43-MHz reference frequency are < -69 dBc. The total power consumption of the PLL including that for the output buffers is ~23 mW     

A fully integrated, untrimmed CMOS instrumentation amplifier withsubmicrovolt offset

A low-noise CMOS instrumentation amplifier intended for low-frequency thermoelectric microsensor applications is presented that achieves submicrovolt offset and noise. Key to its performance is the chopper modulation technique combined with a bandpass filter and a matching on-chip oscillator. No external components or trimming are required. The achievable offset performance depends on the bandpass filter Q and the oscillator-to-bandpass filter matching accuracy. Constraints are derived for an optimum Q and a given matching accuracy. The improvement of common-mode rejection ratio (CMRR) in chopper amplifiers is discussed. The amplifier features a total gain of 77±0.3 dB and a bandwidth of approximately 600 Hz. The measured low-frequency input noise is 8.5 nV/√Hz and the input offset is 600 nV. The measured low-frequency CMRR is better than 150 dB. The circuit has been implemented in a standard 1-μm single-poly CMOS process     

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer is designed in a standard 0.5 /spl mu/m digital CMOS process for wireless communication. The voltage-controlled oscillator (VCO) required for the low-frequency loop is designed using a ring-type VCO and achieves a tuning range of 89% from 356 to 931 MHz and a phase noise of -109.2 dBc/Hz at 600 kHz offset from 856 MHz. With an active chip area of 2000/spl times/1000 /spl mu/m/sup 2/ and at a 2 V supply voltage, the whole synthesizer achieves a tuning range from 1.8492 to 1.8698 GHz in 200 kHz steps with a measured phase noise of -112 dBc/Hz at 600 kHz offset from 1.86 GHz. The measured settling time is 128 /spl mu/s and the total power consumption is 95 mW.     

0.5 W 2?21 GHz monolithic GaAs distributed amplifier

A novel circuit concept to reduce the gate loss using series capacitors on the gate feeding lines has been implemented for a distributed amplifier design. It has significantly increased the gate width of an amplifier with a resultant increase of the broadband output power and efficiency. A monolithic GaAs distributed amplifier using 6 × 300 ?m FETs has achieved a record output power of 0.5 W over the 2 to 21 GHz frequency band with at least 4 dB gain. The poweradded efficiency was 14%. The linear gain was 5 ± 1 dB over the same frequency band.     

A 7.2 GHz bipolar operational transconductance amplifier for fully integrated OTA-C filters

Using a complementary bipolar junction transistor process having NPN transistors with a maximum short circuit common emitter gain-bandwidth product (ft) of 7.2 GHz and PNP transistors with a maximumft of 4.5 GHz, an operational transconductance amplifier has been designed for a 3-dB bandwidth of 7.2 GHz. The design process invokes new phase compensation strategies and develops innovative new ways of exploiting existing broadbanding techniques. The utility of the design is confirmed by demonstrating its application in two operational transconductance amplifier-capacitance filters. One of these examples is a 225 MHz lowpass filter, while the other is a bandpass filter with a center frequency of 250 MHz.This paper is an elaboration of work presented by the authors at the36th IEEE Midwest Symposium On Circuits And Systems in Detroit, Michigan, in August 1993.     

A fully integrated 5.8 GHz U-NII band 0.18-/spl mu/m CMOS VCO

A fully integrated 5.8 GHz CMOS L-C tank voltage-controlled oscillator (VCO) using a 0.18-/spl mu/m 1P6M standard CMOS process for 5 GHz U-NII band WLAN application is presented. The VCO core circuit uses only PMOS to pursue a better phase noise performance since it has less 1/f noise than NMOS. The measurement is performed by using a FR-4 PCB test fixture. The output frequency of the VCO is from 5860 to 6026 MHz with a 166 MHz tuning range and the phase noise is -96.9 dBc/Hz at 300 kHz (or -110 dBc/Hz at 1 MHz) with V ctrl = 0 V. The power consumption of the VCO excluding buffer amplifiers is 8.1 mW at V/sub DD/ = 1.8 V and the output power is -4 dBm.     

A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS

A fully integrated 5-GHz low-power ESD-protected low-noise amplifier (LNA), designed and fabricated in a 90-nm RF CMOS technology, is presented. This 9.7-mW LNA features a 13.3-dB power gain at 5.5 GHz with a noise figure of 2.9 dB, while maintaining an input return loss of -14 dB. An on-chip inductor, added as "plug-and-play," i.e., without altering the original LNA design, is used as ESD protection for the RF pins to achieve sufficient ESD protection. The LNA has an ESD protection level up to 1.4 A transmission line pulse (TLP) current, corresponding to 2-kV Human Body Model (HBM) stress. Experimental results show that only minor RF performance degradation is observed by adding the inductor as a bi-directional ESD protection device to the reference LNA.     

Ultra-broadband 20.5-31 GHz monolithically-integrated CMOS power amplifier

A fully monolithically-integrated power amplifier with a bandwidth (-3 dB) from 20.5 to 31 GHz was realised in a 0.13 /spl mu/m standard CMOS technology. A maximum power added efficiency of 13% with a corresponding output power of 13 dBm was achieved at 25.7 GHz with 1.5 V supply voltage.     

26-42 GHz SOI CMOS low noise amplifier

A complementary metal-oxide semiconductor (CMOS) single-stage cascode low-noise amplifier (LNA) is presented in this paper. The microwave monolithic integrated circuit (MMIC) is fabricated using digital 90-nm silicon-on-insulator (SOI) technology. All impedance matching and bias elements are implemented on the compact chip, which has a size of 0.6 mm /spl times/ 0.3 mm. The supply voltage and supply current are 2.4 V and 17 mA, respectively. At 35 GHz and 50 /spl Omega/ source/load impedances, a gain of 11.9 dB, a noise figure of 3.6 dB, an output compression point of 4 dBm, an input return loss of 6 dB, and an output return loss of 18 dB are measured. The -3-dB frequency bandwidth ranges from 26 to 42 GHz. All results include the pad parasitics. To the knowledge of the author, the results are by far the best for a silicon-based millimeter-wave LNA reported to date. The LNA is well suited for systems operating in accordance to the local multipoint distribution service (LMDS) standards at 28 and 38 GHz and the multipoint video distribution system (MVDS) standard at 42 GHz.     

1.6GHz高线性度低功耗CMOS驱动放大器

提出了一种高线性度低功耗驱动放大器的设计方法,这种设计方法采用最佳偏置(Optimum Biasing)的线性化技术提高线性度.利用这种方法设计了一个工作在1.6GHz的两级驱动放大器,第一级预放大器采用1.8V电源电压,第二级输出放大器采用3.3V电源电压.放大器在TSMC 0.18μM CMOS 工艺下仿真,仿真结果显示放大器的电压增益为31.8dB,三阶交调截取点(OIP3)为20.0dBm,输出1dB压缩点为17.7dBm,输出饱和功率为19.3dBm,静态功耗小于40mW.     

A fully integrated 2.4 GHz CMOS high power amplifier using parallel class A&B power amplifier and power-combining transformer for WiMAX application

A new structure integrated power amplifier with watt-level output power is presented in a standard 0.18 μm CMOS process for WiMAX applications. A parallel cascode class A&B power amplifier with optimized widths is proposed to increase linearity and efficiency simultaneously. A novel interleaved PCT power combiner is proposed for increasing output power that combines output current of two similar class A&B power amplifiers. Proposed interleaved transformer heightens coupling factor compared to typical transformer.     

一个全集成的CMOS脉冲超宽带发射机

本文给出了一个低功耗、全集成的CMOS脉冲式超宽带发射机电路的设计和流片测试结果,其集成了亚纳秒脉冲发生器、脉冲位置调制(PPM)器和天线驱动电路等,可支持多种调制方式并产生最高达1Gp/s的超宽带脉冲序列.设计采用数字驱动信号上升沿触发的新型反馈结构脉冲发生器,可产生稳定的脉冲信号.通过可调的脉冲宽度和PPM调制步长,设计提供了工艺参数和温度变化的补偿手段.     

3-10 GHz low-power, low-noise CMOS distributed amplifier using splitting-load inductive peaking and noise-suppression techniques

A CMOS distributed amplifier (DA) with flat and low noise figure (NF), and flat and high gain (S ₂₁) is demonstrated. A flat and low NF was achieved by adopting a RL terminating network for the gate transmission line, and a slightly under-damped Q-factor for the second-order NF response. Besides, flat and high S ₂₁ was achieved using the proposed cascade gain cell, which constitutes a cascode-stage with a low-Q RLC load and a splitting-load inductive-peaking inverter stage. In the high-gain (HG) mode, the DA consumed 27.6 mW and achieved S ₂₁ of 17.5 plusmn 1.23 dB with an average NF of 3.24 dB over the 3-10 GHz band, one of the best reported NF performances for a CMOS UWB DA or LNA in the literature. The measured IIP3 was 2.1 dBm (at 8 GHz). In the low-gain (LG) mode, the DA achieved S ₂₁ of 10.74 plusmn 1.2 dB and an average NF of 4.67 dB with a low power dissipation of 9 mW.     

A fully integrated VCO at 2 GHz

A fully integrated voltage-controlled oscillator at a frequency of 2 GHz with low phase noise has been implemented in a standard bipolar process with a f_t of 25 GHz. The design is based on an LC-resonator with vertical-coupled inductors. Only two metal layers have been used. The supply voltage of the oscillator is 2.7 V. The phase noise is only -136 dB/Hz at 4.7 MHz frequency offset. A tuning range of 150 MHz is achieved with integrated tuning diodes     

A DC-12 GHz monolithic GaAsFET distributed amplifier

A monolithic balanced traveling-wave amplifier stage using GaAs MESFET's is demonstrated. This amplifier achieves 7-9-dB gain with about 40-ps risetime and a -3-dB bandwidth of 12 GHz, on a 0.91 × 0.97-mm die. Its gain versus frequency is very flat, and |S11|, |S12|, and |S22| are less than 0.2 from 0-18 GHz. S-parameter uniformity and yield data are measured on-wafer with a special hybrid wafer probe.     

A low-voltage and variable-gain distributed amplifier for 3.1-10.6 GHz UWB systems

A low-voltage and variable-gain distributed amplifier is presented in this letter. This microwave monolithic integrated circuit amplifier achieves 12-dB gain with a 3-dB frequency band of 1.6-12.1GHz and 6.5-dB noise figure under the bias condition of 0.8-V supply voltage and 6.4-mW total dc power consumption. The gain-control range is from -18dB to +20dB. Resistive metal-oxide-semiconductor field-effect transistors are used as termination resistors to compensate the mismatch due to different bias conditions. From 3.1 to 10.6GHz, the maximum gain ripple of this amplifier is only /spl plusmn/1dB for the gain level between -4 and 20dB.