Impact of soft and hard breakdown on analog and digital circuits

The influence of gate oxide breakdown of one MOS transistor on the functionality of simple analog and digital circuits is studied. The main changes in the transistor behavior such as the additional gate current as well as transconductance and threshold voltage degradation are pointed out and their respective impact on circuit characteristics is analyzed. With this approach, it is possible to identify critical transistors during the design stage and implement appropriate countermeasures. Depending on the application, some circuits may be functional even after breakdown of one of their transistors.     

Design of improved‐reliability nanocircuits with mixed NBTI‐ and HCI‐aware gate‐sizing formulation

Negative bias temperature instability (NBTI) and hot carrier injection (HCI) are two important processes of reliability concern in nano‐scale integrated circuits. A circuit‐level design technique to combat NBTI degradation is gate oversizing. This paper presents a new technique based on PMOS and NMOS resistance variation for the NBTI‐ and HCI‐aware gate‐sizing problem for the first time. In this technique, the area of the circuit is minimized with constraints on degraded delay due to NBTI and HCI and the transitor size. Expreimental results for several gates and ISCAS'85 benchmark circuits show that this technique imposes an area overhead of less than 1% with respect to baseline design in most cases. © 2013 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Series connection of IGBT's with active voltage balancing

This paper describes an active gate drive circuit for series-connected insulated gate bipolar transistors (IGBTs) with voltage balancing in high-voltage applications. The gate drive circuit not only amplifies the gate signal, but also actively limits the overvoltage during switching transients, while minimizing the switching transients and losses. In order to achieve the control objective, an analog closed-loop control scheme is adopted. The closed-loop control injects current to an IGBT gate as required to limit the IGBT collector-emitter voltage to a predefined level. The performance of the gate drive circuit is examined experimentally by the series connection of three IGBTs with conventional snubber circuits. The experimental results show the voltage balancing by an active control with wide variations in loads and imbalance conditions     

Performance analysis and enhancement of 10-nm GAA CNTFET-based circuits in the presence of CNT-metal contact resistance

The gate-all-around (GAA) CNTFET is one of the most efficient types of CNTFETs which provides the conditions for scaling the technology to 10 nm and beyond, due to the extraordinary features of carbon nanotubes and the superior gate control through a high-k insulator over the CNT channel. However, the high CNT-metal contact resistance at the source/drain terminals can significantly degrade the device and circuit performance in CNTFET technology compared to what we have expected. In this study, first a comprehensive comparative assessment of performance and robustness of the gate-all-around CNTFET- and FinFET-based devices and circuits is performed. In the GAA CNTFET-based circuits the contact resistance can be defined as a series resistor at each contacted node of transistors. In addition, an effective circuit-level solution for improving the performance of GAA CNTFET-based circuits in the presence of contact resistance is proposed. In this approach, the contact lengths of the devices located on the critical path are increased to an effective value to reduce the contact resistance considerably and the other contact lengths remain minimum-sized. The results demonstrate that applying this solution significantly improves the speed, energy consumption and energy-delay product of GAA CNTFET-based circuits.     

一种缓解NBTI效应引起电路老化的门替换方法

45 nm工艺下,负偏置温度不稳定性（negative bias temperature instability,NBTI）效应是限制电路的性能的首要因素。为了缓解NBTI效应引起的电路老化,提出了1个基于门替换方法的设计流程框架和门替换算法。首先利用已有的电路老化分析框架来预测集成电路在其服务生命期内的最大老化,然后以门的权值作为指标来识别关键门,最后采用门替换算法对电路中的部分门进行替换。基于ISCAS85基准电路和45 nm晶体管工艺的试验结果表明,相对于已有的方法,采用文中的门替换方法,使得NBTI效应引起的电路老化程度平均被缓解了9.11%,有效地解决了控制输入向量（input vector control,IVC）方法不适用于大电路问题。     

Gate‐level body biasing technique for high‐speed sub‐threshold CMOS logic gates

An efficient technique for designing high‐performance logic circuits operating in sub‐threshold region is proposed. A simple gate‐level body biasing circuit is exploited to change dynamically the threshold voltage of transistors on the basis of the gate status. Such an auxiliary circuit prepares the logic gate for fast switching while maintaining energy efficiency. If 200 aJ is the target total energy per operation consumption, a two input NAND (NOR) gate designed as described here shows a delay reduction between 20% (16%) and 40% (48%), with respect to previously proposed sub‐threshold approaches. Copyright 2012 John Wiley & Sons, Ltd.     

A symmetric quantum-dot cellular automata design for 5-input majority gate

By the inevitable scaling down of the feature size of the MOS transistors which are deeper in nanoranges, the CMOS technology has encountered many critical challenges and problems such as very high leakage currents, reduced gate control, high power density, increased circuit noise sensitivity and very high lithography costs. Quantum-dot cellular automata (QCA) owing to its high device density, extremely low power consumption and very high switching speed could be a feasible competitive alternative. In this paper, a novel 5-input majority gate, an important fundamental building block in QCA circuits, is designed in a symmetric form. In addition to the majority gate, a SR latch, a SR gate and an efficient one bit QCA full adder are implemented employing the new 5-input majority gate. In order to verify the functionality of the proposed designs, QCADesigner tool is used. The results demonstrate that the proposed SR latch and full adder perform equally well or in many cases better than previous circuits.     

Switched current circuit using fixed gate‐potential transistor and automatic tuning circuit

Clock feedthrough (CFT) error is one of the most important problems for switched current (SI) circuits. This paper proposes a SI circuit which can reduce CFT error drastically. The proposed circuit will theoretically reduce both signal‐dependent and independent errors by using CMOS switches under a fixed and appropriate bias. Although conventional circuits based on a similar idea need operational amplifiers or additional capacitors, our proposed circuit requires only MOSFETs. The proposed circuit can reduce CFT current with less power consumption and chip area compared to those of conventional circuits. An automatic tuning circuit, which controls the gate potential appropriately, is also proposed. Simulation results demonstrate the effectiveness of the proposed circuits. © 1999 Scripta Technica, Electr Eng Jpn, 126(3): 21–29, 1999     

Noise‐immune dual‐rail dynamic circuit for wide fan‐in gates in asynchronous designs

Dual‐rail dynamic logic circuits can provide inverting and noninverting outputs, especially for asynchronous designs, to implement complicated gates at the cost of approximately doubling the area and power consumption. In this paper, a new dual‐rail dynamic circuit is proposed which has lower die area consumption and higher noise immunity without dramatic speed degradation for even wide fan‐in gates for asynchronous circuits. The main idea in the proposed circuit is that voltage due to the current of the pulldown network (PDN) is compared with the reference voltage to provide two complementary outputs. The reference voltage almost corresponds to the leakage current of the PDN with all transistors being off. The proposed circuit is compared with conventional dual‐rail circuits such as differential domino logic and differential cross‐coupled domino logic. Simulation results for 32‐bit‐wide OR gates designed using high‐performance 16‐nm predictive technology model demonstrate significant performance advantages such as 66% power reduction and at least 2.86× noise‐immunity improvement at the same delay compared to the differential domino circuits. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Solid-State Circuit Breaker Based on Cascaded Normally-On SiC JFETs for Medium-Voltage DC Distribution Networks

Solid-state circuit breakers (SSCBs) are critical components in the protection of medium-voltage DC distribution networks to facilitate arc-free, fast and reliable isolation of DC faults. However, limited by the capacity of a single semiconductor device, using semiconductor-based SSCBs at high voltage is challenging. This study presents the details of a 1.5 kV, 63 A medium-voltage SSCB, composed primarily of a solid-state switch based on three cascaded normally-on silicon carbide (SiC) junction field-effect transistors (JFETs) and a low-cost programmable gate drive circuit. Dynamic and static voltage sharing among the cascaded SiC JFETs of the SSCB during fault isolation is realized using the proposed gate drive circuit. The selection conditions for the key parameters of the SSCB gate driver are also analyzed. Additionally, an improved pulse-width modulation current-limiting protection solution is proposed to identify the permanent overcurrent and transient inrush current associated with capacitive load startup in a DC distribution network. Using the developed SSCB prototype and the fault test system, experimental results are obtained to validate the fault response performance of the SSCB.     

IGBT fault current limiting circuit

There is a growing market demand for insulated gate bipolar transistors (IGBTs) with high efficiency but long short-circuit withstand time. The inherent device tradeoff, however, does not allow device designers to achieve both goals simultaneously. The proposed circuits, by limiting the fault current magnitude, extends the short-circuit withstand time of high efficiency (high-gain) IGBTs. Limiting of the fault current magnitude also results in reduced turn-off voltage transients; a desirable byproduct, especially for higher current modules. Moreover, the adverse Miller effect is counterbalanced to a great degree. If the fault current is of a short transient type, the circuit restores normal operation, a unique and desirable feature for noise-prone systems. The circuit does not require an external DC supply to operate. This feature, combined with the simplicity of the circuit, makes it feasible to insert the circuit in IGBT modules or connect it as an interface between the gate driver and module     

Electronic model of a Ferroelectric Field Effect transistor

Abstract

A pair of electronic models has been developed of a Ferroelectric Field Effect transistor. These models can be used in standard electrical circuit simulation programs to simulate the main characteristics of the FFET. The models use the Schmitt trigger circuit as a basis for their design. One model uses bipolar junction transistors and one uses MOSFET's. Each model has the main characteristics of the FFET, which are the current hysterisis with different gate voltages and decay of the drain current when the gate voltage is off. The drain current from each model has similar values to an actual FFET that was measured experimentally. The input and output resistance in the models are also similar to that of the FFET. The models are valid for all frequencies below RF levels. Each model can be used to design circuits using FFET's with standard electrical simulation packages. These circuits can be used in designing non-volatile memory circuits and logic circuits and are compatible with all SPICE based circuit analysis programs. The models consist of only standard electrical components, such as BJT's, MOSFET's, diodes, resistors, and capacitors. Each model is compared to the experimental data measured from an actual FFET.     

A general method for small-signal circuit analysis considering thermal effects

It is well known that the behaviour of integrated circuits is strongly affected by thermal feedback. A general method for evaluating, by linear analysis, the complete circuit performance is described that considers these effects. The procedure can easily be implemented using only well known computer programs for the circuit analysis. Simple models for a number of devices (diodes, transistors and f.e.t.s) used in integrated circuits are given. Examples, using the circuit-analysis program ECAP, are shown.     

The subcircuit extraction problem

The steady down scaling of CMOS device dimensions has been the main stimulus to the growth of microelectronics and computer aided very large scale integration (VLSI) design. But the more an integrated circuit (IC) is scaled, the higher its packing density becomes. The increasing size of chips, measured in either area or number of transistors, and the waste of the large capital investment involved in fabricating and testing circuits that do not work, make layout analysis and verification an important part of physical design automation. The most efficient way to overcome these difficulties is to identify a related collection of interconnected primitive devices in a circuit as a gate-level component. This is usually called the subcircuit extraction problem. The paper presents some background on subcircuit extraction. Subcircuit extraction is becoming a more critical issue with the increasing design sizes of very large scale integrated circuits (VLSICs). In the future, one of the most important tasks is to convert current stand-alone subcircuit extraction algorithms into economic benefits. We should make every effort to find those companies who would like to incorporate these algorithms into their VLSI layout verification software to speed up the process.     

A 5.25‐V‐tolerant bidirectional I/O circuit in a 28‐nm CMOS process

A 5.25‐V‐tolerant bidirectional I/O circuit has been developed in a 28‐nm standard complementary metal‐oxide‐semiconductor (CMOS) process with only 0.9 and 1.8 V transistors. The transistors of the I/O circuit are protected from over‐voltage stress by cascode transistors whose gate bias level is adaptively controlled according to the voltage level of the I/O pad. The n‐well bias level of the p‐type metal‐oxide‐semiconductor transistors of the I/O circuit is also adapted to the voltage level of the I/O pad to prevent any junction leakage. The 5.25‐V‐tolerant bidirectional I/O circuit occupies 40 µm × 170 µm of silicon area. Copyright © 2014 John Wiley & Sons, Ltd.     

A true single‐phase clock dual‐modulus prescaler with enhanced robustness against leakage currents

A new leakage‐tolerant true single‐phase clock dual‐modulus prescaler based on a stage‐merged scheme is presented. Leakage‐restricting transistors are used to reduce the leakage currents at critical nodes, and leakage‐related malfunctions are eliminated at minimal cost in terms of speed, power, and area overheads. An HSPICE simulation in a 40‐nm process shows that the proposed divide‐by‐2/3 divider can effectively enhance robustness against leakage currents to extend the low frequency limit of the circuit over wide temperature and threshold voltage ranges. Additionally, the proposed design shows speed and power performance that is comparable with the performance levels of referenced designs. Copyright © 2016 John Wiley & Sons, Ltd.     

A three-terminal piecewise-linear modelling approach to dc analysis of transistor circuits

The simulation of electronic circuits by computer has become an important part of present-day circuit analysis and design, especially in the area of integrated circuit design. One of the goals in computer simulation of integrated circuits is to have a program ‘package’ for which the input consists of chip fabrication data (mask dimensions, impurity profiles, material data such as carrier lifetimes) and the output displays the complete circuit response. This requires both an efficient modelling approach and a fast circuit analysis method. In this paper a simulation method is described which generates dc responses (in the form of operating points or transfer characteristics) of transistor circuits directly from physical parameter data. The basis of the method is a two-dimensional piecewise-linear approach to the dc modelling of bipolar transistors. The model is directly used in a piecewise-linear circuit analysis program to simulate the dc response of a given circuit.     

Design and Simulation of Solid State Pulser with Fast Rise Time and Double-exponential Waveform

Voltage pulses with fast rise time can be obtained from Marx circuits based on avalanche transistors. In this research, the ZETEX avalanche transistors are used as the switches in a Marx circuit to generate stable voltage pulses with double-exponential waveform and fast rise time. By using these transistors, the circuit is able to generate higher pulsed voltage with fewer stages. A three stages and a ten stages Marx circuit, as well as their triggering circuits, are designed. The two Marx circuits are also tested by simulations based on the Pspice code and by experiments, results of which are consistent with each other. With the ten stages Marx circuit, we obtain positive and negative pulses with the rise time of about 1.5 ns, the amplitude above 1 100 V, and the pulse width below 5 ns. It is proved that the proposed Marx circuit equipped with avalanche transistors could be an effective kind of solid-state pulse generator.     

Design technique for mitigation of alpha-particle-induced single-event transients in combinational logic

Alpha particles incident on CMOS integrated circuits deposit charges on circuit nodes resulting in single-event transients (SETs). These transient errors propagate through the circuit and reach a latch where they may get latched under proper conditions. This paper presents circuit design techniques to remove the effects of such SET pulses from the circuit. An optimized design is developed whose area, power, and speed performance is superior to other design methods for SET mitigation. Simulation results showing SET pulse elimination are presented.     

Analysing the operation of the basic pass transistor structure

Pass transistor logic has become important for the design of low‐power high‐performance digital circuits due to the smaller node capacitances and reduced transistors count it offers. However, the acceptance and application of this logic depends on the availability of supporting automation tools, e.g. timing simulators, that can accurately analyse the performance of large circuits at a speed, significantly faster than that of SPICE based tools. In this paper, a simple and robust modelling technique for the basic pass transistor structure is presented, which offers the possibility of fast timing analysis for circuits that employ pass transistors as controlled switches. The proposed methodology takes advantage of the physical mechanisms in the pass transistor operation. The obtained accuracy compared to SPICE simulation results is sufficient for a wide range of input and circuit parameters. Copyright © 2006 John Wiley & Sons, Ltd.