Low power quadrature voltage controlled oscillator

In this article, a low voltage low power quadrature voltage controlled oscillator (QVCO) coupled by four P&N transistors is presented. First, a novel negative resistance inductance capacitor (LC) oscillator is described, the N‐metal oxide semiconductor (NMOS) and P‐metal oxide semiconductor (PMOS) transistors are in series with the LC tank in the direct‐current (DC) path, and they generate the required negative resistance to compensate the energy loss of the LC tank and maintain the steady oscillation of the oscillator. Then, based on two identical LC oscillators, four P&N transistors are used as coupling terminals to generate quadrature outputs. The proposed QVCO is designed and simulated with GlobalFoundries' 0.18 μm CMOS RF process. The Cadence IC design tools postlayout simulation results demonstrate that the oscillation frequency of the QVCO can be tuned from 2.0 to 5.6 GHz by adjusting the bias voltage, and the phase noise of the voltage controlled oscillator is ?114 dBc/Hz at 1 MHz offset. Moreover, the proposed QVCO consumes only 2.31 mW from a 1.2 V supply voltage and it occupies a compact area of 0.45 mm² including the bond pads.     

A 2.4 GHz low power CMOS transceiver for LR-WPAN applications

A 2.4 GHz low power transceiver for low-rate wireless personal area network(LR-WPAN)applications is presented.The optimized low-IF receiver consists of a novel current reuse RF front-end with an inductor-less-load balun LNA and quadrature mixer,and an adaptive analog baseband to reduce power and area.It achieves-94 dBm of sensitivity,-9 dBm of IIP3 and 28 dBc of image rejection.The phase-locked loop based direct phase modulated transmitter is proposed to reduce power and deliver a+3 dBm output power.The phase noise of the low power frequency synthesizer with current reuse stacked LC-VCO achieves-107.8 dBc/Hz at 1 MHz offset.An ultra-low power nonvolatile memory is used to store configuration data and save power.The chip is implemented in a 0.18μm CMOS process,and the area is less than 2.8 mm2.The transceiver consumes only 10.98 mW in the receiving mode and 13.32 mW in the transmitting mode.     

A low power fully differential RF receiver front-end for 2.4 GHz wireless sensor networks

In this paper, a novel merged LNA-mixer denoted as LNMA is proposed. The proposed LNMA consisting of a folded cascode LNA using improved derivative superposition technique and folded double-balanced subthreshold mixer using capacitor cross-coupled common-gate transconductor and it is integrated with on-chip LC voltage controlled oscillator (LC-VCO). In LNMA, a diode and power clamp based on-chip ESD protection circuit is used to tolerate ESD current of human-body-model specifications. To evaluate its performance, it is implemented in 0.18-µm MMRF CMOS process with 1-V supply, studied through post layout simulation and compared the results with other reported works. It achieves higher conversion gain of 27 dB, lower noise figure of 9.5 dB, lower input return loss (S11) of − 20 dB, higher third-order input intercept point (IIP₃) of – 16 dBm and higher IIP₂ of + 29.9 dBm compared to the works reported in the literature. The on-chip oscillator has the lower phase noise of – 114 dBc/Hz. The proposed LNMA and the LC-VCO achieves the power consumptions of 1.6 and 1.72 mW, respectively at 1-V power supply.

     

Characterization of indoor wireless channel at 5 GHz U-NII bands

The paper reports on the experiments undertaken at the University of Wollongong to characterise fading profiles and delay parameters of an indoor wireless channels at 5 GHz U-NII bands. The measurements were undertaken at different locations around the campus with results recorded for a post-processing to calculate the Rician K-factor, the level crossing rate and the average fade duration as well as mean excess delay, rms delay spread, and the coherence bandwidth of the channel. The presented measurement results can be useful in developing a Markov chain based model of the transport channel for IEEE802.11a or HYPRLAN-2 networks. The results also indicate scenarios where the coherence bandwidth of the channel is smaller than the width of the sub-carrier OFDM channels in either of the mentioned systems.     

A multiband carrier generation architecture for UHF, 2.4 GHz,and 5 GHz ISM applications

Novel multiband carrier generation architecture is proposed that can be applicable for RFID reader, WLAN 802.11a‐b‐g, and ZigBee sensor network, and implemented with 0.18 μm CMOS technology. In the proposed architecture, a quadrature voltage controlled oscillator (QVCO) is implemented by coupling two differential cross‐coupled LC VCOs to generate in‐phase (I) and quadrature (Q) signals operating at one‐thirds of the 5 GHz frequency range. As well, the differential second harmonic signal of the VCO core frequency is generated by mixers, and then converted to I/Q signals via a single‐stage tunable polyphase filter. By single sideband mixing of the I/Q signals of the QVCO and the polyphase filter, a cleaner carrier signal can be generated in the frequency band of 5 GHz. By including extra frequency dividers, the architecture can also be reconfigured to generate UHF band and 2.4 GHz band. The proposed architecture draws about 32 mA including the QVCO core current consumption of 2.8 mA from 1.8 V supply. The measured tuning frequency of the QVCO core ranges from 1.57 to 1.84 GHz. The measured phase noise is ?104.5 dBc/Hz at 1 MHz offset from 4.84 GHz. The chip layout occupies an area of 1.44 × 1.4 mm² on Si substrate, including the DC and RF pads. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.     

Slot line fed dual‐band dipole antenna for 2.4/5.2 GHz WLAN applications

A printed slot line fed dual‐band coplanar dipole antenna having a dimension of 0.40λ_g × 0.20λ_g suitable for both 2.4 and 5.2 GHz (IEEE 802.11 b/g and 802.11 a) WLAN application is presented. The structure comprises of a slot line fed symmetrical L strips to achieve dual‐band operation. Design equations of the antenna are developed and validated on different substrates. The simulation and experimental results show that the proposed antenna exhibits good impedance match, gain, and stable radiation patterns in both the frequency bands. © 2012 Wiley Periodicals, Inc. Int J RF and Microwave CAE , 2012.     

MFOA‐integrated modified inverted F‐based adaptive array Antenna for 2.4 GHz band applications

This research has proposed a modified fruit fly optimization algorithm (MFOA)‐integrated adaptive array antenna (AAA) for the 2.4–2.5 GHz WLAN system. The principal components of the array antenna system encompass four array elements, four band pass filters (BPF), four digital phase shifters, a four‐way power combiner/splitter, a directional coupler, a radio frequency (RF) detector, and a microcontroller unit (MCU). In the realization of the adaptive antenna system, the modified inverted F antenna with a finite ground plane was first innovated and subsequently deployed as the element of the four‐element array antenna. In the study, simulations and experiments were carried out with the four‐element AAAs of two configurations, i.e. the linear and planar array configurations. The simulation and experimental results revealed that the MFOA algorithmic scheme could determine the direction of the maximum arrival signal in an efficient and accurate manner and also was capable of manipulating the radiation pattern in the desired direction. In addition, the MFOA‐integrated four‐element AAA is of compact size (20 mm × 35 mm × 1.8 mm) and operable in the 2.31–2.55 GHz frequency band with omnidirectional radiation pattern and a gain of 1.6 dBi. © 2016 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2016.     

应用于开关电源的CMOS电流控制振荡器

提出了一种结构简单的CMOS电流控制模式振荡器。该电路利用系统内部参考电压和外接电阻产生的电流信号对电容进行充放电,通过调节外接电阻大小,振荡器输出频率在660 kHz～4.15 MHz内可调。     

Novel double fractal patches structure Antenna‐in‐Package based on LTCC technology for 2.4 GHz applications

A novel Antenna‐in‐Package with small size and low profile is designed based on Low Temperature Co‐fired Ceramic technology. In order to realize miniaturization and broadband in antenna part, a novel structure using double fractal antennas and air cavities is applied. A packaging cavity is designed for integrated with usable components and IC chips. The antenna operates at a center frequency of 2.4 GHz and the bandwidth is about 200 MHz. Its maximum gain is 5.6 dBi, and radiation efficiency is above 90% across the frequency passband. By adjusting the dimension parameters, a tradeoff between height and area can be made with its performance parameters constant, therefore the proposed Antenna‐in‐Package can easily adapt to different processes and performance.     

Hybrid wireless sensor network for building energy management systems based on the 2.4 GHz and 400 MHz bands

In this paper, a hybrid wireless sensor network (WSN) system is considered and implemented for the building energy management systems. Characteristics of the radios, which are based on the 2.4 GHz and 400 MHz bands, respectively, are analyzed for the building environments. For battery-operated portable sensors, narrow-bandwidth radios of the 400 MHz band are employed in a star connection between their parent nodes. Between the parent nodes, a mesh network is constructed for an efficient and fast data transmission based on the wide-bandwidth radios of the 2.4 GHz band. The hybrid WSN system is implemented and tested for a building environment and provides a reliable wireless communication link for gathering sensing data.     

Behavioral modeling of power amplifiers for wireless applications

In this paper, an improved empirical behavioral model for radio‐frequency power amplifiers (RF‐PAs) is presented. The model was implemented in a commercial nonlinear microwave simulator. It belongs to the category of bandpass PA models, which exhibits memory effects due to the low frequency dependence of bias and temperature. Additionally, it facilitates accurate and efficient system level simulations of RF‐PA large‐signal behaviors such as self‐bias, AM‐AM, AM‐PM, gain expansion effects, and intermodulation distortion (IMD) sweet‐spots. The model was validated using measurement data obtained from a commercial CDMA PA at 1.88 GHz. © 2007 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2007.     

Specific absorption rate reduction using metasurface unit cell for flexible polydimethylsiloxane antenna for 2.4 GHz wearable applications

This article presents the design of a polydimethylsiloxane based flexible antenna for body worn applications. In order to reduce the specific absorption rate (SAR) metasurface (MS) based unit cell is proposed. Copper foil of thickness 3 mil considered for conducting layers. The proposed antenna is designed with leaf structure and covers the WLAN ISM band 2.4 GHz without metasurface (NMS) and with metasurface (WMS) unit cell. The MS unit cell at the backside of the antenna does not cover the entire antenna but only a portion of it where the backward energy is highly concentrated. This yields better result in reducing the SAR with a very compact sized MS unit cell. This MS structure improves the gain of an antenna and also reduces the SAR, by directing the radiating energy in opposite direction from the human user. The proposed antenna NMS has a simulated SAR value of 2.53 W/kg at 2.4 GHz over volume of 1 g of tissue, whereas WMS it is reduced to 1.53 W/kg. The comparative analysis of the proposed antenna presented with the help of performance matrices like reflection coefficient, SAR, gain, and radiation patterns.     

An efficient PSP-based model for optimized cross-coupled MOSFETs in voltage controlled oscillator

This paper proposes an efficient PSP-based model for cross-coupled metal-oxide-semiconductor field-effect transistors(MOSFETs) with optimized layout in the voltage controlled oscillator(VCO).The model employs a PSP charge model to characterize the bias-dependent extrinsic capacitance instead of numerical functions with strong non-linearity.The simulation convergence is greatly improved by this method.An original scheme is developed to extract the parameters of the PSP charge model based on S-parameters measurement.The interconnection parasitics of the cross-coupled MOSFETs are modeled based on vector fitting.The model is verified with an LC VCO design,and exhibits excellent convergence during simulation.The results show improvements as high as 60.5% and 61.8% in simulation efficiency and accuracy,respectively,indicating that the proposed model better characterizes optimized cross-coupled MOSFETs in advanced radio frequency(RF) circuit design.     

A compact omnidirectional dual‐circinal rectenna for 2.45 GHz wireless power transfer

A compact dual‐circinal rectenna with omnidirectional characteristic is designed for microwave wireless power transmission at 2.45 GHz. A novel dual‐circinal receiving antenna with the reflection coefficient of ?32.5 dB is proposed which is formed by expanding folded curves. By designing an impedance matching network with a 60 ° radial stub and a single stub, a rectifier is presented with the maximum efficiency of 55.6 % and the output dc voltage of 1.19 V under the input power of 0 dBm. Simulation and measurements have been carried out for the antenna and the rectifier. The measured results agree well with the simulated value. The results of rectenna experiment show that the maximum conversion efficiency is 51% at 2.45 GHz when the input power is 0 dBm. The proposed rectenna has the characteristics of compact size and omnidirectional harvesting which are advantageous in RF energy harvesting applications.     

无线传感器网络节点的低功耗设计

无线传感器网络(WSNs)能够协作地实时监测、感知和采集各种环境对象的信息,并将信息传递给系统用户主机进行分析处理。节点具有感知和路由的功能,在实际的应用中,功耗是影响节点工作寿命的关键因素。设计分析了WSNs系统功率消耗的构成,并从硬件和软件方面提出和总结了WSNs的低功耗设计方法,设计了一种低功耗的WSNs节点,并进行了测试,结果证明:该方法适合WSNs节点的应用,具有易使用、低功耗特点。     

Stability of current-mode control for DC–DC power converters

DC–DC power converters are switched devices whose averaged dynamics are described by a bilinear second-order system with saturated input. In some cases (e.g., boost and buck–boost converters), the input output dynamics can be of nonminimum-phase nature. Current-mode control is the standard strategy for output voltage regulation in high dynamic performance industrial DC–DC power converters. It is basically composed by a saturated linear state feedback (inductor current and output voltage) plus an output voltage integral feedback to remove steady-state offset. Despite its widespread usage, there is a lack of rigorous results to back up its stabilization capability and to systematize its design. In this paper, we prove that current-mode control yields semiglobal stability with asymptotic regulation of the output voltage.     

Varifocal liquid lenses with integrated actuator, high focusing power and low operating voltage fabricated on 200 mm wafers

We developed an innovative type of varifocal liquid lens actuated by electrostatic parallel plates. The 3 mm diameter lens is made of a polymer membrane that encapsulates a high permittivity liquid in a cavity on top of a glass wafer. Annular electrodes situated below the membrane and on the glass wafer form the electrostatic parallel plates actuator. By applying a voltage between the electrodes, the electrostatic actuation generated reduces the gap and pushes the liquid towards the center of the lens changing the curvature of the membrane.Compared to previous liquid lenses, very compact devices (≤6 mm × 6 mm × 0.7 mm) working at a reduced supply voltage (<25 V) are demonstrated. Wave front measurements indicate an optical power change of 8 m⁻¹ at 22 V_RMS that can be further improved. The lenses were fabricated on 200 mm wafers using standard microelectronics processes that make our solution a promising small outline, low voltage and low cost candidate for auto-focus devices in camera phones.     

Low power FPGA-based image processing core for wireless capsule endoscopy

The paper presents an FPGA-based image and data processing core for future generation wireless capsule endoscopy (WCE). The main part of the presented core is an image compressor, for which a hardware implementation architecture requiring only two clock cycles for processing a single image pixel is proposed. Apart from the image compressor, the presented core includes a camera interface, a FIFO queue storing the compressed image bitstream, a forward error correction encoder protecting transmitted data against random and burst transmission errors, and a system controller supervising internal WCE operations. The presented core has been implemented in a single ultra low power, 65 nm FPGA chip. Power consumption of the designed FPGA core was determined to be comparable to other ASIC-based WCE systems.     

PVT‐compensated low‐voltage and low‐power CMOS LNA for IoT applications

In this paper, a low‐noise amplifier (LNA) with process, voltage, and temperature (PVT) compensation for low power dissipation applications is designed. When supply voltage and LNA bias are close to the subthreshold, voltage has significant impact on power reduction. At this voltage level, the gain is reduced and various circuit parameters become highly sensitive to PVT variations. In the proposed LNA circuit, in order to enhance efficiency at low supply voltage, the cascade technique with g_m boosting is used. To improve circuit performance when in the subthreshold area, the forward body bias technique is used. Also, a new PVT compensator is suggested to reduce sensitivity of different circuit's parameters to PVT changes. The suggested PVT compensator employs a current reference circuit with constant output regarding temperature and voltage variations. This circuit produces a constant current by subtracting two proportional to absolute temperature currents. At a supply voltage of 0.35 V, the total power consumption is 585 μW. In different process corners, in the proposed LNA with PVT compensator, gain and noise figure (NF) variations are reduced 10.3 and 4.6 times, respectively, compared to a conventional LNA with constant bias. With a 20% deviation in the supply voltage, the gain and noise NF variations decrease 6.5 and 34 times, respectively.