A novel analog switch for high‐precision switched‐capacitor applications

The performance of a switched‐capacitor circuit strongly depends on its analog switches. This paper introduces a new technique to design a high‐precision analog metal‐oxide‐semiconductor switch for switched‐capacitor applications. The accuracy of analog switches is a critical parameter to determine overall performance of the discrete‐time analog systems. To satisfy the accuracy requirements of the switch, a novel technique to minimize the charge injection and clock feedthrough errors by using a very simple structure is proposed. Moreover, an innovative approach to increase the OFF resistance of the switch and consequently minimizing its leakage current is presented. To evaluate the performance of the proposed switch, simulations are done in TSMC 0.18μm standard complementary metal‐oxide‐semiconductor technology with BSIM3V3 device models. The ON and OFF resistances of the switch are one of the most important factors that should be considered while investigating analog switches. The ON resistance of the proposed switch is less than 560Ω over entire input signal range which completely satisfies the tracking bandwidth requirements. In addition, since the proposed switch provides an ultrahigh OFF resistance in the range of several GΩs, the leakage current of the proposed switch is negligible. Simulation results also show that switch‐induced errors are significantly eliminated by using the proposed cancellation technique. The output error charge due to charge injection and clock feedthrough over a wide range of input signal variation is very low (less than 1.6 fC). Moreover, simulation results show that the proposed switch achieves signal to noise plus distortion ratio of 80.55 dB, effective number of bits of 13.08, total harmonic distortion of ?81.41 dB, and spurious‐free dynamic range of 87.7 dB for a 2.5‐MHz sinusoidal input of 800‐mV peak‐to‐peak amplitude at 200‐MHz sampling rate with a 1.8‐V supply voltage. Consequently, the simulation results verify that the proposed switch can significantly improve the dynamic and static performances of a switched‐capacitor circuit.     

A pseudo‐differential current‐reuse structure for opamp‐sharing pipelined analog‐to‐digital converters

In this paper, a power efficient pseudo‐differential (PD) current‐reuse structure is presented to alleviate the memory effects of opamp‐sharing in pipelined analog‐to‐digital converters. To implement the PD current‐reuse structure, a switched‐capacitor circuit is introduced for multiplying digital‐to‐analog converter, which has a slight modification compared with the conventional switching scheme with no power penalty. In the proposed multiplying digital‐to‐analog converter circuit, the common‐mode offset amplification of the PD structures is eliminated. Moreover, a PD current‐reuse amplifier is developed from the telescopic structure with an inverter‐based gain‐boosting circuit. The effectiveness of the proposed structure is evaluated in comparison with existing current‐reuse techniques. Copyright © 2014 John Wiley & Sons, Ltd.     

A 6‐bit 4 MS/s 26fJ/conversion‐step segmented SAR ADC with reduced switching energy for BLE

This paper presents a 6‐bit 4 MS/s segmented successive approximation register analog‐to‐digital converter for Bluetooth low energy transceiver applications. To improve the linearity and reduce the switching power consumption, a segmented structure with new switching scheme is adopted in the capacitive digital‐to‐analog converter. The proposed switching sequence determines the MSBs according to the thermometer codes and skips some of the unnecessary steps while avoiding bubble errors. To ensure the common mode voltage remains comparatively steady, and to avoid employing power‐hungry common mode reference voltage circuits, each capacitor is divided into 2 identical small capacitors, connecting one of them to “high” and the other one to “low”. The switching sequence is straightforward, and a split capacitor with an integer value is applied, which almost halves the total number of capacitors while retaining the unit capacitor value intact. The prototype analog‐to‐digital converter is fabricated and measured in a 55‐nm (shrinked 65 nm) complementary metal‐oxide semiconductor process and achieves 5.48 to 5.92 Effective Number of Bits (ENOB) at a sampling frequency of 4 MS/s. The Signal to Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) for Nyquist input frequency are 34.79 and 40.03 dB, respectively. The current consumption is 4.8 μA from a 1.0‐V supply, which corresponds to the figure of merit of 26 fJ/conversion‐step. The total active area of the analog‐to‐digital converters for the I and Q paths of the receiver is 105 μm × 140 μm.     

FFT‐based calibration method for 1.5 bit/stage pipelined ADCs

A fast Fourier transform (FFT)‐based digital calibration method for 1.5 bit/stage pipeline analog‐to‐digital converter (ADC) is proposed in this paper. Capacitor mismatch and finite gain of the operational amplifier (OPAMP) can be overcome by the proposed calibration method. Given that the capacitor mismatch and the finite OPAMP gain cause the radix of all the stages of 1.5 bit/stage pipeline ADC to become unequal to 2, the FFT processor can be adopted to evaluate the actual radixes of all the stages and then generate new digital output to compensate for error caused by these non‐ideal effects. Moreover, as capacitor mismatch and the finite gain of OPAMP can be compensated, low‐gain OPAMP can be used in high‐performance ADC to reduce power dissipation; a small capacitor can then be adopted to save on space. An example of a 10 bit 1.5 bit/stage pipelined ADC with only an 8 bit circuit performance is implemented in 0.18 µm TSMC CMOS process. Circuit measurement result reveals that the signal‐to‐noise‐and‐distortion ratio of 51.03 dB with 11 dB improvement after calibration can be achieved at the sample rate of 1 MHz. Copyright © 2013 John Wiley & Sons, Ltd.     

An active‐passive capacitor‐commutated converter for HVDC systems with a three‐phase voltage‐source PWM converter

This paper introduces a new approach to the capacitor‐commutated converters (CCCs) for HVDC systems. A small‐rated three‐phase voltage‐source PWM converter is connected between a series commutation capacitor and thyristor converter through matching transformers. The PWM converter acts as auxiliary commutation‐capacitor for the thyristor converter while the series passive capacitor acts as the main commutation capacitor. The capacitance, which is the sum of the small‐rated active and series passive capacitors, is variable, so that stable commutation is obtained. In CCCs, commutation failure occurs when the AC bus voltage is recovered whereas the proposed combined commutation‐capacitor can achieve successful commutation for both rapidly decreasing and increasing AC bus voltages. The basic principle of the proposed active–passive capacitor‐commutated converter is discussed in detail. Then, constant margin angle control with a constant firing angle of the thyristor converter is proposed using a function generator block. Digital simulation demonstrates the novelty and effectiveness of the proposed active–passive capacitor‐commutated converter. © 2005 Wiley Periodicals, Inc. Electr Eng Jpn, 151(1): 66–75, 2005; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20030     

Three‐stage multiphase‐switched‐capacitor boost DC‐AC inverter

A closed‐loop scheme of a three‐stage multiphase‐switched‐capacitor boost DC‐AC inverter (MPSCI) is proposed by combining the multiphase operation and sinusoidal‐pulse‐width‐modulation (SPWM) control for low‐power step‐up DC‐AC conversion and regulation. In this MPSCI, the power unit contains two parts: MPSC booster (front) and H‐bridge (rear). The MPSC booster is suggested for an inductor‐less step‐up DC‐DC conversion, where three voltage doublers in series are controlled with multiphase operation for boosting voltage gain up to 2³ = 8 at most. The H‐bridge is employed for DC‐AC inversion, where four solid‐state switches in H‐connection are controlled with SPWM to obtain a sinusoidal AC output. In addition, SPWM is adopted for enhancing output regulation not only to compensate the dynamic error, but also to reinforce robustness to source/loading variation. The relevant theoretical analysis and design include: MPSCI model, steady‐state/dynamic analysis, voltage conversion ratio, power efficiency, stability, capacitance selection, total harmonic distortion (THD), output filter, and closed‐loop control design. Finally, the closed‐loop MPSCI is simulated, and the hardware circuit is implemented and tested. All the results are illustrated to show the efficacy of the proposed scheme. Copyright © 2011 John Wiley & Sons, Ltd.     

A new control method of a resonant switched‐capacitor converter and the application for balancing of the split DC voltages in a multilevel inverter

This paper proposes a new voltage‐balancing circuit for the split DC voltages in a diode‐clamped five‐level inverter. The proposed circuit is based on a resonant switched‐capacitor converter (RSCC), which consists of two half‐bridge inverters, a resonant inductor, and a resonant capacitor. A new phase‐shift control of the RSCC is proposed to improve voltage balancing performance. Theoretical analysis reveals the rating of the RSCC and stored energy in the resonant inductor. Experimental results confirm the reduction of the inductor to one‐tenth in volume compared to a conventional voltage‐balancing circuit based on buck‐boost topology. Moreover, the proposed phase‐shift control has demonstrated that it is possible to eliminate the voltage deviation between the DC capacitors. © 2009 Wiley Periodicals, Inc. Electr Eng Jpn, 168(2): 69–79, 2009; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20719     

A systematic approach to designing a wide‐current range,MOS capacitor‐based switched‐capacitor DC‐DC converter with an augmenting LDO

Switched‐capacitor DC‐DC converters (SC DC‐DC) are analyzed for loss sources, voltage regulation integrity, start‐up latency, and ripple size, while the trade‐offs between these metrics are derived. These analyses are used to design a SC DC‐DC that achieves high efficiency in a wide load current range. Four‐way interleaving was employed to reduce the output ripple and efficiency loss due to this ripple. The design can be reconfigured to achieve gains of 1/3 and 2/5 for inputs ranging between 1.4 and 3.6 V to generate output voltage range of 0.4 to 1.27 V and can supply peak load current of 22 mA. It uses thin‐oxide MOS capacitors for their high density and achieves 75.4% peak efficiency with an input frequency of 100 MHz and a load capacitor of 10 nF. An augmenting LDO that only regulates during sudden load transients helps the converter respond fast to these transients. The chip was implemented using a 65‐nm standard CMOS process.     

Impact of parasitics on even symmetric split‐capacitor arrays

This paper analyzes the impact of parasitic capacitances in the performance of split capacitive‐based digital‐to‐analog converter arrays and presents a procedure for the optimal sizing of these structures for given linearity specifications. It also demonstrates that parasitics are often the main responsible for the nonlinear behavior of these arrays, particularly for low‐to‐medium resolution converters. In order to validate the analysis, two versions of a complete low‐power, low‐voltage successive‐approximation register analog‐to‐digital converter (ADC), intended for a disposable multi‐channel bio‐medical monitoring system, have been fabricated in a 0.35 µm standard complementary metal‐oxide‐semiconductor technology. The only difference between these two prototypes is that in one of them, the capacitive array is surrounded by dummy capacitors, while in the other prototype is not. Hence, the former achieves better mismatch performance at the expense of increased parasitics. The experimental results demonstrate that the version without dummy capacitors obtains higher effective resolution than the ADC with dummies, the power consumption being essentially the same for both prototypes, namely: 130nW at 2kS/s from a 1‐V supply. These results are in full agreement with the analysis reported in the paper and confirm the proposed sizing procedure. Copyright © 2012 John Wiley & Sons, Ltd.     

Design and analysis of power‐CMOS‐gate‐based switched‐capacitor DC–DC converter with step‐down and step‐up modes

A unified multi‐stage power‐CMOS‐transmission‐gate‐based quasi‐switched‐capacitor (QSC) DC–DC converter is proposed to integrate both step‐down and step‐up modes all in one circuit configuration for low‐power applications. In this paper, by using power‐CMOS‐transmission‐gate as a bi‐directional switch, the various topologies for step‐down and step‐up modes can be integrated in the same circuit configuration, and the configuration does not require any inductive elements, so the IC fabrication is promising for realization. In addition, both large‐signal state‐space equation and small‐signal transfer function are derived by state‐space averaging technique, and expressed all in one unified formulation for both modes. Based on the unified model, it is all presented for control design and theoretical analysis, including steady‐state output and power, power efficiency, maximum voltage conversion ratio, maximum power efficiency, maximum output power, output voltage ripple percentage, capacitance selection, closed‐loop control and stability, etc. Finally, a multi‐stage QSC DC–DC converter with step‐down and step‐up modes is made in circuit layout by PSPICE tool, and some topics are discussed, including (1) voltage conversion, output ripple percentage, and power efficiency, (2) output robustness against source noises and (3) regulation capability of converter with loading variation. The simulated results are illustrated to show the efficacy of the unified configuration proposed. Copyright © 2003 John Wiley & Sons, Ltd.     

Modelling cross‐regulation in a single switched capacitor DC‐DC converter

The letter proposes to model cross‐regulation in a dual‐output switched capacitor converter (SCC) by three equivalent resistances connected in delta circuit. It is shown that as opposed to linear equivalent (output) resistance of single‐output SCCs, these resistances are voltage‐controlled. The obtained analytical expressions have been verified by simulations and give correct results even if the output voltages change in wide range. The proposed analysis paves the way for modelling cross‐regulation in complex SCCs with multiple topologies and can be useful in studies of crosstalk through parasitic capacitances on chip.     

A 1‐Gbps reference‐less burst‐mode CDR with embedded TDC in a 65‐nm CMOS process

A reference‐less all‐digital burst‐mode clock and data recovery circuit (CDR) is proposed in the paper. The burst‐mode CDR includes a coarse and a fine time‐to‐digital converter (TDC) with embedded phase generator. A low‐power current‐starved inverter is employed as the delay unit of the fine TDC to acquire the high measurement resolution. A calibration method to diminish the inherent delay is used to reduce the quantization error of the recovery clock. The proposed CDR is fabricated in a 65‐nm CMOS process. Experiment results show that the CDR operates from 0.9 to 1.1 Gbps and have a 13‐bit consecutive identical digits (CIDs) tolerance.     

A 0.5‐V 5.9‐fJ/conversion‐step SAR ADC in 0.18‐μm CMOS

In this paper, we present a 434‐nW 8‐bit successive approximation register analog‐to‐digital converter (SAR ADC). We mainly consider the optimization of power consumption. A modified split‐capacitor array involving a novel switching scheme is proposed, which reduces the switching power consumption to just 13.8 for the single‐ended scheme without any losses in performance. Based on the SMIC CMOS 0.1 μm EEPROM 2P4M process, the simulation results show that at 0.5 V supply voltage, 300 kS/s sample frequency, and 4.98 kHz input frequency, the ADC achieves an signal‐to‐noise‐plus‐distortion ratio (SNDR) of 49.58 dB and effective number of bits (ENOB) of 7.94, and consumes 434 nW, resulting in a figure of merit of 5.9 fJ/conversion step. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Transfer function‐matched capacitor‐current sensing and its circuit implementation for high‐frequency power converters

It would effectively achieve a fast load transient response in switching‐mode power converters when introducing capacitor current into the feedback control loop. In these schemes, an accurate and rapid sensing of capacitor current is crucial in the control circuit design. On this issue, a paralleled nonintrusive sensing scheme for capacitor current is proposed in this paper, which is implemented by matching the transfer functions of the sensing circuit and the sensed capacitor branch. With the proposed transfer function matching approach, 4 possible circuit topologies are derived in theory, and on this basis, a parameter design flow chart is given for 2 of candidate topologies. With the application of the proposed capacitor‐current sensing circuit to a constant‐frequency hysteresis controlled Buck converter, a fast and accurate sensing of capacitor current is achieved in experiment, as well as a fast load transient response.     

A wideband time‐based continuous‐time sigma‐delta modulator with 2nd order noise‐coupling based on passive elements

Embedding the time encoding approach inside the loop of the sigma‐delta modulators has been shown as a promising alternative to overcome the resolution problems of analog‐to‐digital converters in low‐voltage complementary metal‐oxide semiconductor (CMOS) circuits. In this paper, a wideband noise‐transfer‐function (NTF)‐enhanced time‐based continuous‐time sigma‐delta modulator (TCSDM) with a second‐order noise‐coupling is presented. The proposed structure benefits from the combination of an asynchronous pulse width modulator as the voltage‐to‐time converter and a time‐to‐digital converter as the sampler to realize the time quantization. By using a novel implementation of the analog‐based noise‐coupling technique, the modulator's noise‐shaping order is improved by two. The concept is elaborated for an NTF‐enhanced second‐order TCSDM, and the comparative analytical calculations and behavioral simulation results are presented to verify the performance of the proposed structure. To further confirm the effectiveness of the presented structure, the circuit‐level implementation of the modulator is provided in Taiwan Semiconductor Manufacturing Company (TSMC) 90 nm CMOS technology. The simulation results show that the proposed modulator achieves a dynamic range of 84 dB over 30 MHz bandwidth while consuming less than 25 mW power from a single 1 V power supply. With the proposed time‐based noise‐coupling structure, both the order and bandwidth requirements of the loop filter are relaxed, and as a result, the analog complexity of the modulator is significantly reduced. Copyright © 2015 John Wiley & Sons, Ltd.     

Multistage multiphase switched‐capacitor DC–DC converter with variable‐phase and PWM control

A closed‐loop multistage multiphase switched‐capacitor converter (n‐stage p‐phase MPSC) is proposed with a variable‐phase control (VPC) and a pulse‐width‐modulation (PWM) technique for low‐power step‐up conversion and high‐efficiency regulation. In this n‐stage MPSC, n voltage doublers are connected in series for boosting the voltage gain up to 2ⁿ at most. Here, VPC is suggested to realize a variable multiphase operation by changing the phase number p and topological path for the more suitable level of voltage gain so as to improve the power efficiency, especially for the lower output voltage Besides, PWM is adopted not only to enhance output regulation for different desired outputs, but also to reinforce output robustness to source/loading variation. Further, some theoretical analyses and designs include: n‐stage p‐phase MPSC model, steady‐state analysis, conversion ratio, power efficiency, output ripple, stability, capacitance selection, and control design. Finally, the closed‐loop MPSC is simulated, and the hardware is implemented and tested. All the results are illustrated to show the efficacy of the proposed scheme. Copyright © 2011 John Wiley & Sons, Ltd.     

Transient characteristics of a tapped‐winding capacitor motor

Tapped‐winding capacitor motors are widely used for fans in air conditioners as speed adjusting motors. In tapped‐winding capacitor motors, the burnout accidents of phase‐shifting capacitors have been seen on occasion. The cause of such accidents is considered to be the transient capacitor current. In this paper, equations for calculating transient characteristics are derived for three types of tapped‐winding capacitor motors. Based on these equations, transient characteristics are clarified in high‐ and low‐speed winding connections. Further, from the design viewpoint, the effects of the turn ratio and capacitance of the capacitor on the transient characteristics are examined and a procedure for choosing the winding ratio and capacitance of the capacitor is suggested. Using this method, the transient current is shown to decrease by about 40%. © 2002 Wiley Periodicals, Inc. Electr Eng Jpn, 141(4): 69–77, 2002; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.10063     

Output current ripple reduction of LED driver using ceramic‐capacitor‐input circuit and buck‐boost converter

This article proposes an LED driver that consists of a ceramic‐capacitor‐input rectifier and a buck‐boost converter. The LED driver has an advantage of long life because it does not contain any electrolytic capacitors. However, the issue with electrolytic capacitor‐less LED driver is that the ripple of the smoothed voltage becomes large due to insufficient capacitance of the smoothing capacitor. The proposed method, which uses the discontinuous current mode of a buck‐boost converter, reduces the output current ripple under such conditions. Experimental results using a 5.7 W LED driver prototype demonstrate that the proposed method reduces the output current ripple and that the percent flicker becomes 4.4%, which is smaller than the recommended upper limit of 8%.     

A 7.5‐μW 0.08‐mm2 single‐ended SC delta‐sigma ADC for acoustic sensor applications

This study presents an ultra‐low‐power, small‐size, 1‐bit, single‐ended, and switched‐capacitor (SC) delta‐sigma analog‐to‐digital converter (ADC) for wireless acoustic sensor nodes. This wireless sensor node has a delta‐sigma ADC that converts the sensed signal to a digital signal for convenient data processing and emphasizes the features of small size and low‐power consumption. The chip area of the delta‐sigma ADC is dominated by the capacitor; therefore, a novel common‐mode (CM) controlling technique with only transistors is proposed. This ADC achieves an extremely small size of 0.08 mm² in a 130‐nm CMOS process. The conventional operational transconductance amplifiers (OTAs) are replaced by inverters in the weak inversion region to achieve high power efficiency. At 4‐MHz sampling frequency and 0.7‐V power supply voltage, the delta‐sigma ADC achieves a 55.8‐dB signal‐to‐noise‐plus‐distortion ratio (SNDR) and a 298‐fJ/step figure‐of‐merit (FOM) in a signal bandwidth of 25 kHz, while consuming only 7.5 μW of power. Copyright © 2015 John Wiley & Sons, Ltd.     

A universal‐input high‐power‐factor power supply without electrolytic capacitor for multiple lighting LED lamps

The AC–DC power supply for LED lighting application requires a long lifetime while maintaining high‐efficiency, high power factor and low cost. However, a typical design uses electrolytic capacitor as storage capacitor, which is not only bulky but also with short life span, thus hampering performance improvement of the entire LED lighting system. In this article, a SEPIC‐derived power factor correction topology is proposed as the first stage for driving multiple lighting LED lamps. Along with a relatively large voltage ripple allowable in a two‐stage design, the proposal of LED lamp driver is able to eliminate the electrolytic capacitor while maintaining high power factor and high efficiency. To further increase the efficiency of LED driver, we introduced and used the twin‐bus buck converter as the second‐stage current regulator with Pulse Width Modulation (PWM) dimming function. The basic operating principle and the deign consideration are discussed in detail. A 50‐W prototype has been built and tested to verify the proposal. Copyright © 2011 John Wiley & Sons, Ltd.