Nonlinear dynamics of divide‐by‐two injection‐locked frequency dividers in locked operation mode

A method for analyzing the nonlinear dynamics of the injection‐locked frequency dividers in synchronized operation mode is presented, including the stability analysis of locked states. We use a specific divide‐by‐two circuit, namely a differential LC CMOS divider with a complementary topology, as a guideline for presentation, showing that the sizing of the devices significantly affects the synchronization mechanism of the divider, which exhibits a very rich dynamical behavior. We provide closed‐form expressions to determine the amplitude and the phase in the locked state, as well as the locking range, leading to accurate results, which are validated by numerical simulations. The presented analysis of the frequency divider dynamics enables us to establish that stable locked oscillations occur on the whole locking range predicted by the well‐known Adler's equation and that these are possible also beyond that range. Copyright © 2013 John Wiley & Sons, Ltd.     

Wide‐band dual‐resonance capacitive cross‐coupled divide‐by‐5 injection‐locked frequency divider

A wide locking range divide‐by‐5 injection‐locked frequency divider (ILFD) is proposed and was implemented in the TSMC 0.18‐μm 1P6M CMOS process. Conventional divide‐by‐5 ILFD has limited locking range. The proposed divide‐by‐5 ILFD is based on a capacitive cross‐coupled voltage‐controlled oscillator (VCO) with a dual‐resonance resonator, which is implemented in the divide‐by‐5 ILFD to obtain a wide overlapped locking range. At the drain‐source bias V_DD of 0.9 V and at the incident power of 0 dBm, the measured locking range of the divide‐by‐5 ILFD is 3.2 GHz, from the incident frequency 9.4 to 12.6 GHz, the percentage is 29.09%. The core power consumption is 2.98 mW. The die area is 0.987 × 1.096 mm².     

Wide‐locking range divide‐by‐4 injection‐locked frequency divider using injection MOSFET DC‐biased above threshold region

A novel wide locking range divide‐by‐4 injection‐locked frequency divider (ILFD) is proposed in the paper and was implemented in the TSMC 0.18 µm 1P6M CMOS process. The divide‐by‐4 ILFD uses two injection transistors in series and DC‐biased above threshold voltage and a frequency doubler to enhance the function of linear mixers. At the drain‐source bias of 0.9 V and at the incident power of 0 dBm, the locking range of the divide‐by‐4 is 2.6 GHz; from the incident frequency 12.2 to 14.8 GHz, the percentage is 19.26%. The core power consumption is 10.35 mW. The die area of ILFD is 1.026 × 0.943 mm². Copyright © 2015 John Wiley & Sons, Ltd.     

Wide‐band divide‐by‐2 injection‐locked frequency divider using MOSFET mixers DC‐biased in subthreshold region

A novel wide locking range divide‐by‐2 injection‐locked frequency divider (ILFD) is proposed in the paper and was implemented in the TSMC 0.18‐µm 1P6M CMOS process. The divide‐by‐2 ILFD is based on a cross‐coupled voltage‐controlled oscillator (VCO) with an LC resonator and injection MOSFETs with source voltage coupled from ILFD output, and the injection MOSFET mixer is biased in subthreshold region. At the drain–source bias of 0.9 V, and at the incident power of 0 dBm the locking range of the divide‐by‐2 ILFD is 6.4 GHz; from the incident frequency 3.7 GHz to 10.1 GHz, the percentage is 92.75%. The core power consumption is 16.56 mW. The die area is 0.839 × 0.566 mm². Copyright © 2015 John Wiley & Sons, Ltd.     

Design and analysis of a millimeter‐wave injection locked frequency divider with transconductance boosting technique

This paper presents a degenerated injector (mixer) with transconductance boosted by biasing the mixer transistor in the knee region of its I‐V curve, without increasing the transistor size and its parasitics. This mixer can enhance the locking range of millimeter‐wave injection‐locked frequency dividers. To compensate the degradation of mixer transconductance (conversion‐gain) due to the degeneration effect, a neutralization technique is employed. Analyses are given for locking‐range and induced phase‐noise of the proposed divider for arbitrary injection strength. It is shown that the locking‐range, as a function of injection strength, is improved by increasing the fundamental component of transconductance. Using 180‐nm CMOS technology, a 1.78‐mW divider‐by‐two is designed with free‐running frequency of 27.92 GHz, locking‐range of 51 to 59.6 GHz, and figure‐of‐merit of 4.83 (GHz/mW). EM simulation results of the proposed and conventional structure are compared, which illustrates 56% improvement in locking‐range.     

A study of superharmonic injection locking in multiband frequency dividers

A superharmonic voltage‐controlled injection‐locked frequency divider, implemented using a modified Colpitts oscillator operating at 2.5, 5 and 10 GHz and a cross‐coupled LC oscillator operating at 1.25, 2.5 and 5 GHz, is demonstrated. The proposed triple‐band operation is achieved by employing a novel technique that uses pin‐diodes and negative power supply. The discrete dividers, built with low noise hetero‐junction FETs and high‐frequency SiGe BJTs, are described theoretically while their functionality is proven experimentally. Additionally, a short phase noise analysis, which is missing in the literature, is given. Phase noise, frequency range of operation, and locking range measurement results are presented. Finally, post‐layout simulation results of a 5 GHz fully differential injection‐locked frequency divider, implemented in a 0.25µm SiGe process are provided. Copyright © 2010 John Wiley & Sons, Ltd.     

Divide‐by‐2 LC injection‐locked frequency divider with wide locking range at low and high injection powers

A wide locking range nMOS divide‐by‐2 RLC injection‐locked frequency divider (ILFD) was designed and implemented in the TSMC 0.18‐µm BiCMOS process. The ILFD is based on a cross‐coupled oscillator with one direct injection MOSFET and a RLC resonator. The RLC resonator is used to extend the locking range so that dual‐band locking ranges can be merged in one locking range at both low and high injection powers. At the drain‐source bias of 0.9 V for switching transistors, and at the incident power of 0 dBm the locking range of the divide‐by‐2 ILFD is 7.24 GHz, from the incident frequency 2.65 to 9.89 GHz, the locking range percentage is 115.47%. The power consumption of ILFD core is 8.685 mW. The die area is 0.726 × 0.930 mm². Copyright © 2016 John Wiley & Sons, Ltd.     

A configurable 2‐Gbps LVDS transceiver in 150‐nm CMOS with pre‐emphasis,equalization, and slew rate control

A configurable full‐duplex low‐voltage differential signaling transceiver is presented, which can be configured to operate either for smaller differential channels (a few inches of striplines) or for longer channels (10 m of twisted pair cables). The configurability is embedded in the form of functionalities like pre‐emphasis, equalization, and slew rate control within the transceiver. The transmitter employs a hybrid voltage–current‐mode driver, which due to replica action, achieves a high‐impedance current‐mode signal dispatch and at the same time provides a matched impedance at the near end for improved intersymbol interference. The transmitter achieves slew rate control through a band‐limited pre‐driver, while the pre‐emphasis is achieved through a capacitive feed‐forward. The receiver employs a large‐input common‐mode first stage enclosed in a common‐mode control loop that enables its first stage to also act like a domain shifter (VDDIO‐to‐VDDCORE) reducing the overall power consumption. The equalization in the receiver is implemented by using carefully sized active inductive loads inside the receiver. The transceiver is designed and fabricated in 150‐nm complementary metal–oxide–semiconductor, sharing the space with a larger die, occupying an area of 400 × 400μm. The measurement results demonstrate that the transceiver is operating at 2 Gbps both for a 4‐in microstrip and a 10‐m twisted pair CAT6 cable with 30 and 180 ps of total jitter, respectively. The built‐in impedance calibrator minimizes the spread in the on‐die termination at the near end provided by the transmitter‐minimizing bit error rate across process, voltage, and temperature corners. The transmitter consumes a total power of 17 mW operating at 2 Gbps, that is, 8.5 pJ/bit of energy consumption; the receiver consumes a total power of 3.5 mW while driving a load of 5 pF at 2 Gbps. Copyright © 2016 John Wiley & Sons, Ltd.     

Optimal analog‐to‐digital transformation of fractional‐order Butterworth filter using binomial series expansion with Al‐Alaoui operator

This paper deals with the optimal analog‐to‐digital transformation of fractional‐order Butterworth filter (FOBF) in terms of infinite impulse response templates. The fractional‐order transfer function of the analog FOBF is transformed into its digital counterpart by employing the Binomial series expansion of different truncation orders, based on the Al‐Alaoui operator. This nonoptimal solution is then treated as an initial point for a local search optimizer such as the Nelder–Mead simplex (NMS) algorithm and also injected as a super‐fit individual in the initial population of a global search constrained evolutionary optimization algorithm (CEOA). Design stability and minimum‐phase response constraints are formulated for the super‐fit scheme. Both the techniques demonstrate good modeling performance; however, the super‐fit CEOA can markedly outperform the NMS method as the problem dimensionality increases.     

A fully‐integrated CMOS UWB transceiver for ultra‐low‐power short‐range application

In short‐range UWB communication systems, the low‐power design is the most important issue to make UWB technology attractive. A novel trigger receiving algorithm for UWB signals is proposed, which can reduce the system power significantly at the cost of slight performance degrade. A UWB transceiver based on the trigger receiving algorithm is designed and fabricated in HJTC 0.18 µm CMOS process with a total size of 0.45 mm². The experimental results show that the total power consumption of the transceiver is only 12 mW at 100 Mb/s data rate from a 1.8 V supply, making it suitable for low‐power short‐range communication. Copyright © 2010 John Wiley & Sons, Ltd.     

A Five‐Element Multiplex Resonant Full‐Bridge DC‐DC Converter with a Variable Inductive Reactance

A five‐element multiplex resonant (LLCLC) full‐bridge DC‐DC converter controlled by pulse frequency modulation (PFM) is proposed in this paper. The high frequency (HF)‐link resonant DC‐DC converter proposed herein can perform wide‐range output power and voltage regulation with a narrow frequency range due to an antiresonant tank that works effectively as a wide‐range variable inductor. The advantageous characteristics of the antiresonant tank provide overcurrent protection in the case of the short‐circuited load condition as well as in the startup interval. Thus, the technical challenges of a conventional LLC DC‐DC converter can be overcome, and the reliability of the relevant switch‐mode power supplies can be improved. The operating principle of the LLCLC DC‐DC converter is described, after which its performance is evaluated in an experimental setup based on the 2.5 kW prototype. Finally, the feasibility of the proposed DC‐DC converter is discussed from a practical point of view.     

A true single‐phase clock dual‐modulus prescaler with enhanced robustness against leakage currents

A new leakage‐tolerant true single‐phase clock dual‐modulus prescaler based on a stage‐merged scheme is presented. Leakage‐restricting transistors are used to reduce the leakage currents at critical nodes, and leakage‐related malfunctions are eliminated at minimal cost in terms of speed, power, and area overheads. An HSPICE simulation in a 40‐nm process shows that the proposed divide‐by‐2/3 divider can effectively enhance robustness against leakage currents to extend the low frequency limit of the circuit over wide temperature and threshold voltage ranges. Additionally, the proposed design shows speed and power performance that is comparable with the performance levels of referenced designs. Copyright © 2016 John Wiley & Sons, Ltd.     

Low‐power quadrature generators for body area network applications

This paper presents different alternatives for the implementation of low‐power monolithic oscillators for wireless body area networks and describes the design of two quadrature generators operating in the 2.4‐GHz frequency range. Both implementations have been designed in a 90‐nm Complementary Metal‐Oxide Semiconductor (CMOS) technology and operate at 1 V of supply voltage. The first architecture uses a voltage‐controlled oscillator (VCO) running at twice the desired output frequency followed by a divider‐by‐2 circuit. It experimentally consumes 335 μW and achieves a phase noise of ?110.2 dBc/Hz at 1 MHz. The second architecture is a quadrature VCO that uses reinforced concrete phase shifters in the coupling path for phase noise improvement. Its power consumption is only 210 μW, and it obtains a phase noise of ?111.9 dBc/Hz at 1 MHz. Copyright © 2011 John Wiley & Sons, Ltd.     

Multivariate theory‐based passivity criteria for linear fractional networks

In traditional linear network theory, the positive‐real (PR) criteria are widely used to judge the passivity of elements and networks in the light of the fact that there exists an equivalent relationship between the passivity and the PR property of their immittance functions (matrices). However, the equivalence will no longer hold when the fractional elements are introduced into the network, and the PR criteria are not suitable in complex frequency domain anymore. On the other hand, the rapid development of fractional‐order circuits and systems and the corresponding study in fractional circuit analysis and designs put forward an urgent requirement for the passivity criterion, which can tackle linear fractional networks. Hence, in this paper, we propose new passivity criteria for linear fractional networks by aid of generalized Tellegen's theorem and multivariable PR theory. By using the proposed criteria, the passivity of linear fractional networks can be judged, and the steps of the proposed criterion are illustrated by examples.     

Analysis of a dual‐resonant multiple split‐ring patch antenna

The design and analysis of a new 0.06λ × 0.09λ compact circular polarized square‐shaped dual‐resonant multiple split‐ring patch antenna on a 1.905‐mm‐thick high‐dielectric ceramic–polytetrafluoroethylene composite is presented. The proposed antenna was designed and analyzed by using a high‐frequency electromagnetic simulator based on the finite element method and was fabricated on a printed circuit board. The measured ?10 dB return loss bandwidths were 44.44% (0.7–1.1 GHz) and 34% (2.25–3.1 GHz) at 0.9 and 2.5 GHz center frequencies, respectively. The measured radiation patterns with 5.9 and 4.0 dBi maximum gains were symmetric and steady, making the proposed antenna suitable for radio frequency identification, wireless local area network, wireless body area network, Low Rate‐Wireless Personal Area Network (LR‐WPAN), and so on. The effects of linewidth, dielectric property of the substrate materials, and number of split rings on the return loss were investigated. The surface current distribution over the radiating patch and the characteristics of the Resistance, Inductance, Capacitance (RLC) equivalent circuit of the proposed antenna were also analyzed. Copyright © 2013 John Wiley & Sons, Ltd.     

Application of step‐response test for evaluation of uncertainty of standard measuring system for lightning‐impulse high voltage

In evaluating the uncertainty of the standard measuring system for lightning‐impulse high voltages, which is composed of a standard voltage divider, a digital recorder, and calibrators, step‐response tests of the standard voltage divider may be useful. In this paper, a convolution algorithm is employed to calculate the output impulse voltage waveforms from measured step‐response waveforms. The uncertainties of peak‐value measurement due to the influence of the nominal epoch, uncertainty of the peak‐value measurement due to dispersion of the AC scale factor, and uncertainty of the virtual front‐time measurement due to long‐term stability are evaluated. Furthermore, the error of the virtual front time of the output waveforms is discussed. The front part of the step‐response waveform, t≤ T₃₀%, does not influence the error of the virtual front time. Therefore, for the standard voltage divider, the step‐response parameters, that is, the experimental response time, partial response time, settling time, and overshoot, have almost nothing to do with the error of the virtual front time. © 2012 Wiley Periodicals, Inc. Electr Eng Jpn, 180(2): 24–32, 2012; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.21279     

Low‐frequency noise analysis and minimization in Gilbert‐cell‐based mixers for direct‐conversion (zero‐IF) low‐power front‐ends

Low‐frequency (flicker) noise is one of the most important issues in the design of direct‐conversion zero‐IF front‐ends. Within the front‐end building blocks, the direct‐conversion mixer is critical in terms of flicker noise, since it performs the signal down‐conversion to baseband. This paper analyzes the main sources of low‐frequency noise in Gilbert‐cell‐based direct‐conversion mixers, and several issues for minimizing the flicker noise while keeping a good mixer performance in terms of gain, noise figure and power consumption are introduced in a quantitative manner. In order to verify these issues, a CMOS Gilbert‐cell‐based zero‐IF mixer has been fabricated and measured. A flicker noise as low as 10.4 dB is achieved (NF at 10 kHz) with a power consumption of only 2 mA from a 2.7 V power supply. More than 14.6 dB conversion gain and noise figure lower than 9 dB (DSB) are obtained from DC to 2.5 GHz with an LO power of ?10 dBm, which makes this mixer suitable for a multi‐standard low‐power zero‐IF front‐end. Copyright © 2008 John Wiley & Sons, Ltd.     

New Package Scheme of a 2.5-Gb/s Plastic Transceiver Module Employing Multiwall Nanotubes for Low Electromagnetic Interference

A novel polymer-based multiwall carbon nanotube (MWCNT) with high shielding effectiveness (SE) for use in packaging a 2.5-Gb/s plastic transceiver module is demonstrated. The MWCNT composites are tested to evaluate the electromagnetic (EM) shielding against emitted radiation from the optical transceiver modules. The results show that the SE of MWCNT composite packages exhibit 38–45 dB in the far-field source and 28–40 dB in the near-field source at a frequency range of 1–3 GHz, and an average of 14 dB for the optical transceiver modules at a frequency of 2.5 GHz. The MWCNT composites with their high SE are potentially suitable for packaging low-cost and low-EM-interference optical transceiver modules used in Gigabit Ethernet or fiber-to-the-home lightwave transmission systems.     

A 6‐bit 4 MS/s 26fJ/conversion‐step segmented SAR ADC with reduced switching energy for BLE

This paper presents a 6‐bit 4 MS/s segmented successive approximation register analog‐to‐digital converter for Bluetooth low energy transceiver applications. To improve the linearity and reduce the switching power consumption, a segmented structure with new switching scheme is adopted in the capacitive digital‐to‐analog converter. The proposed switching sequence determines the MSBs according to the thermometer codes and skips some of the unnecessary steps while avoiding bubble errors. To ensure the common mode voltage remains comparatively steady, and to avoid employing power‐hungry common mode reference voltage circuits, each capacitor is divided into 2 identical small capacitors, connecting one of them to “high” and the other one to “low”. The switching sequence is straightforward, and a split capacitor with an integer value is applied, which almost halves the total number of capacitors while retaining the unit capacitor value intact. The prototype analog‐to‐digital converter is fabricated and measured in a 55‐nm (shrinked 65 nm) complementary metal‐oxide semiconductor process and achieves 5.48 to 5.92 Effective Number of Bits (ENOB) at a sampling frequency of 4 MS/s. The Signal to Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) for Nyquist input frequency are 34.79 and 40.03 dB, respectively. The current consumption is 4.8 μA from a 1.0‐V supply, which corresponds to the figure of merit of 26 fJ/conversion‐step. The total active area of the analog‐to‐digital converters for the I and Q paths of the receiver is 105 μm × 140 μm.     

Design equations for fractional‐order sinusoidal oscillators: Four practical circuit examples

Four practical sinusoidal oscillators are studied in the general form where fractional‐order energy storage elements are considered. A fractional‐order element is one whose complex impedance is given by Z = a(jω)^±α, where a is a constant and α is not necessarily an integer. As a result, these oscillators are described by sets of fractional‐order differential equations. The integer‐order oscillation condition and oscillation frequency formulae are verified as special cases. Numerical and PSpice simulation results are given. Experimental results are also reported for a selected Wien‐bridge oscillator. Copyright © 2007 John Wiley & Sons, Ltd.