G-band (140-220 GHz) and W-band (75-110 GHz) InP DHBT medium power amplifiers

We report common-base medium power amplifiers designed for G-band (140-220 GHz) and W-band (75-110 GHz) in InP mesa double HBT technology. The common-base topology is preferred over common-emitter and common-collector topologies due to its superior high-frequency maximum stable gain (MSG). Base feed inductance and collector emitter overlap capacitance, however, reduce the common-base MSG. A single-sided collector contact reduces C_ce and, hence, improves the MSG. A single-stage common-base tuned amplifier exhibited 7-dB small-signal gain at 176 GHz. This amplifier demonstrated 8.7-dBm output power with 5-dB associated power gain at 172 GHz. A two-stage common-base amplifier exhibited 8.1-dBm output power with 6.3-dB associated power gain at 176 GHz and demonstrated 9.1-dBm saturated output power. Another two-stage common-base amplifier exhibited 11.6-dBm output power with an associated power gain of 4.5 dB at 148 GHz. In the W-band, different designs of single-stage common-base power amplifiers demonstrated saturated output power of 15.1 dBm at 84 GHz and 13.7 dBm at 93 GHz     

A fully integrated 5.3-GHz 2.4-V 0.3-W SiGe bipolar power amplifier with 50-/spl Omega/ output

A radio frequency power amplifier for 4.8-5.7 GHz has been realized in a 0.35-/spl mu/m SiGe bipolar technology. The balanced two-stage push-pull power amplifier uses two on-chip transformers as input-balun and for interstage matching. Further, it uses three coils for the integrated LC-output balun and the RF choke. Thus, the power amplifier does not require any external components. At 1.0-V, 1.5-V, and 2.4-V supply voltages, output powers of 17.7 dBm, 21.6 dBm, and 25 dBm are achieved at 5.3 GHz. The respective power-added efficiencies (PAE) are 15%, 22%, and 24%. The small-signal gain is 26 dB. The output 1-dB compression point at 2.4 V is 22 dBm with a PAE of 14%.     

A 20 dBm Linear RF Power Amplifier Using Stacked Silicon-on-Sapphire MOSFETs

In this letter, a fully integrated 20-dBm RF power amplifier (PA) is presented using 0.25-mum-gate silicon-on-sapphire metal-oxide-semiconductor field-effect transistors (MOSFETs). To overcome the low breakdown voltage limit of MOSFETs, a stacked FET structure is employed, where transistors are connected in series so that each output voltage swing is added in phase. By using triple-stacked FETs, the optimum load impedance for a 20-dBm PA increases to 50Omega, which is nine times higher than that of parallel FET topology for the same output power. Measurement of a single-stage linear PA shows small-signal gain of 17.1 dB and saturated output power of 21.0dBm with power added efficiency (PAE) of 44.0% at 1.88 GHz. With an IS-95 code division multiple access modulated signal, the PA shows an average output power of 16.3 dBm and PAE of 18.7% with adjacent channel power ratio below -42dBc     

A 2.4-GHz 0.18-/spl mu/m CMOS self-biased cascode power amplifier

A two-stage self-biased cascode power amplifier in 0.18-/spl mu/m CMOS process for Class-1 Bluetooth application is presented. The power amplifier provides 23-dBm output power with a power-added efficiency (PAE) of 42% at 2.4 GHz. It has a small signal gain of 38 dB and a large signal gain of 31 dB at saturation. This is the highest gain reported for a two-stage design in CMOS at the 0.8-2.4-GHz frequency range. A novel self-biasing and bootstrapping technique is presented that relaxes the restriction due to hot carrier degradation in power amplifiers and alleviates the need to use thick-oxide transistors that have poor RF performance compared with the standard transistors available in the same process. The power amplifier shows no performance degradation after ten days of continuous operation under maximum output power at 2.4-V supply. It is demonstrated that a sliding bias technique can be used to both significantly improve the PAE at mid-power range and linearize the power amplifier. By using the sliding bias technique, the PAE at 16 dBm is increased from 6% to 19%, and the gain variation over the entire power range is reduced from 7 to 0.6 dB.     

A 21-26-GHz SiGe bipolar power amplifier MMIC

A three-stage 21-26-GHz medium-power amplifier fabricated in f/sub T/=120 GHz 0.2 /spl mu/m SiGe HBT technology has 19 dB small-signal gain and 15 dB gain at maximum output power. It delivers 23 dBm, 19.75% PAE at 22 GHz, and 21 dBm, 13% PAE at 24 GHz. The differential common-base topology extends the supply to BV/sub CEO/ of the transistors (1.8 V). New on-chip components, such as onchip interconnects with floating differential shields, and self-shielding four-way power combining/dividing baluns provide inter-stage coupling and single-ended I/O interfaces at the input and output. The 2.45/spl times/2.45 mm/sup 2/ MMIC was mounted as a flipchip and tested without a heatsink.     

A Single Supply, High Linearity 2-W PA MMIC for WLAN Applications Using Quasi-Enhancement Mode PHEMTs

A fully matched, 2-W high linearity amplifier monolithic microwave integrated circuit, by using quasi-enhancement mode technology of AlGaAs/InGaAs/ GaAs pseudomorphic high electron mobility transistors, is demonstrated for wireless local area network applications. At Vgs= 0 V, V_ds= 5 V, this power amplifier has achieved 14-dB small-signal gain, 33-dBm output power at 1-dB gain compression point, and 34.5-dBm saturated output power with 35% power added efficiency at 5.8 GHz. Moreover, high-linearity with 45.2-dBm third-order intercept point is also achieved     

Ka波段5W GaAs PHMET功率MMIC

报道了一款采用0.15μm GaAs功率MMIC工艺研制的Ka波段功率放大器芯片。芯片采用四级放大拓扑结构,在29～32GHz频带范围内6V工作条件下线性增益25dB,线性增益平坦度小于±0.75dB;饱和输出功率大于5W,饱和效率大于20%,功率增益大于22dB;1dB压缩点输出功率大于36.5dBm,效率大于18%。     

A 24-GHz, +14.5-dBm fully integrated power amplifier in 0.18-/spl mu/m CMOS

A 24-GHz +14.5-dBm fully integrated power amplifier with on-chip 50-/spl Omega/ input and output matching is demonstrated in 0.18-/spl mu/m CMOS. The use of substrate-shielded coplanar waveguide structures for matching networks results in low passive loss and small die size. Simple circuit techniques based on stability criteria derived result in an unconditionally stable amplifier. The power amplifier achieves a power gain of 7 dB and a maximum single-ended output power of +14.5-dBm with a 3-dB bandwidth of 3.1 GHz, while drawing 100 mA from a 2.8-V supply. The chip area is 1.26 mm/sup 2/.     

一种24 GHz CMOS功率放大器设计

基于130 nm互补金属氧化物半导体(CMOS)工艺,设计了一种高增益和高输出功率的24 GHz功率放大器。通过片上变压器耦合实现阻抗匹配和功率合成,有效改善放大器的匹配特性和提高输出功率。放大器电路仿真结果表明,在1.5 V供电电压下,功率增益为27.2 dB,输入输出端回波损耗均大于10 dB,输出功率1 dB压缩点13.2 dBm,饱和输出功率17.2 dBm,峰值功率附加效率13.5%。     

Application of enhancement mode FET technology for wirelesssubscriber transmit/receive circuits

Single-supply power amplifiers have become the new paradigm in portable phone handsets due to the recent availability of heterojunction bipolar transistor (HBT) and pseudo enhancement mode PHEMT technology. We have developed a true enhancement mode heterostructure insulated-gate FET device (HIGFET) which is suitable for use in both saturated and linear power amplifiers. A three-stage power amplifier designed for 1900-MHz NADC application delivered +30-dBm output power and 41.7% power-added efficiency with an adjacent channel power of -29.8 dBc and alternate adjacent channel power of -48.4 dBc. In addition to this, we have demonstrated excellent noise figure and linearity performance for small-signal applications. At 900 MHz and bias conditions V_DS=1.0 V and I_DSQ=1 mA, a single-stage amplifier achieved a noise figure of 1.17 dB with an associated gain of 18.5 dB. These results make the technology an ideal candidate for application in both transmitter and receiver circuits     

基于GaN 的3. 4~ 3. 6 GHz 高增益Doherty 功率放大器

基于两级功率放大器架构,设计了一款平均输出功率为37 dBm(5 W)的高增益Doherty 功率放大器。 该器件通过增加前级驱动功率放大器提高Doherty 功率放大器的增益,采用反向Doherty 功率放大器架构,将λ/4 波 长传输线放置在辅助功放后端,相位补偿线放置在主功放前端,并使主功放输出匹配网络采用双阻抗匹配技术实现 阻抗变换,如此可扩宽功率放大器的工作带宽。连续波测试结果显示:3. 4~3. 6 GHz 工作频段内,饱和输出功率在 44. 5 dBm 以上,功率饱和工作点PAE 在43. 9%以上;在平均输出功率(37 dBm,5 W)工作点,回退量大于7. 5 dB,功 率附加效率PAE 为36. 8%以上,功率增益在31 dB 以上。     

A fully integrated 24-dBm CMOS power amplifier for 802.11a WLAN applications

A fully integrated 24-dBm complementary metal oxide semiconductor (CMOS) power amplifier (PA) for 5-GHz WLAN applications is implemented using 0.18-/spl mu/m CMOS foundry process. It consists of differential three-stage amplifiers and fully integrated input/output matching circuits. The amplifier shows a P/sub 1/ of 21.8 dBm, power added efficiency of 13%, and gain of 21 dB, respectively. The saturated output power is above 24.1 dBm. This shows the highest output power among the reported 5-GHz CMOS PAs as well as completely satisfying IEEE 802.11a transmitter back off requirement.     

A VSWR-protected silicon bipolar RF power amplifier with soft-slope power control

This paper presents the design and measured performance of a 1.8-GHz power amplifier featuring load mismatch protection and soft-slope power control. Load-mismatch-induced breakdown can be avoided by attenuating the RF power to the final stage during overvoltage conditions. This was accomplished by means of a feedback control system, which detects the peak voltage at the output collector node and clamps its value to a given threshold by varying the circuit gain. The issue of output power control has been addressed as well. To this end, a temperature-compensated bias network is proposed, which allows a moderate power control slope (dB/V) to be achieved by varying the circuit quiescent current according to an exponential law. The nonlinear power amplifier was fabricated using a low-cost silicon bipolar process with a 6.4-V breakdown voltage. It delivers a 33.5-dBm saturated output power with 46% maximum power-added efficiency and 36-dB gain at a nominal 3.5-V supply voltage. The device is able to tolerate a 10:1 load standing-wave ratio up to a 5.1-V supply voltage. Power control slope is lower than 80 dB/V between -15 dBm and the saturated output power level.     

19WC-波段MMIC多芯片合成功率放大器

报告了一个两级 C-波段功率单片电路的设计、制作和性能 ,该单片电路包括完全的输入端和级间匹配 ,输出端的匹配在芯片外实现 ,该放大器在 5.2～ 5.8GHz带内连续波工作 ,输出功率大于 36.6d Bm,功率增益大于 18.6d B,功率附加效率 34 % ,4芯片合成的功率放大器在 4 .7～ 5.3GHz带内 ,输出功率大于 4 2 .8d Bm( 19.0 W) ,功率增益大于 18.8d B,典型的功率附加效率为 34 %。     

60 GHz CMOS Amplifiers Using Transformer-Coupling and Artificial Dielectric Differential Transmission Lines for Compact Design

57–65 GHz differential and transformer-coupled power and variable-gain amplifiers using a commercial 90 nm digital CMOS process are presented. On-chip transformers combine bias, stability and input/interstage matching networks to enable compact designs. Balanced transmission lines with artificial dielectric strips provide substrate shielding and increase the effective dielectric constant up to 54 for further size reduction. Consequently, the designed three-stage power amplifier occupies only an area of only 0.15 mm $^{2}$. Under a 1.2 V supply, it consumes 70 mA and obtains small-signal gains exceeding 15 dB, saturated output power over 12 dBm and associated peak power-added efficiency (PAE) over 14% across the band. The variable-gain amplifier, based on the same principle, achieved a peak gain of 25$~$ dB with 8 dB of gain variation.      

An X-Band High-Power and High-PAE PHEMT MMIC Power Amplifier for Pulse and CW Operation

An X-band high-power and high power added efficiency (PAE), two-stage AlGaAs/InGaAs/GaAs psuedomorphic high electronic mobility transistor (PHEMT) monolithic microwave integrated circuit (MMIC) power amplifier is presented. The amplifier is designed to fully match a 50 Omega input and output impedance. Based on a 0.35 mum gate-length power PHEMT technology, the MMIC is fabricated on a 3 mil thick wafer. Under an 8 V DC bias condition, the characteristics of 17.5 dB small-signal gain, 10 W continuous wave mode saturation output power of 42% PAE, and 12.6 W pulse saturation output power of 52.6% PAE at 9.4 GHz can be achieved.     

A 900-MHz fully integrated SOI power amplifier for single-chipwireless transceiver applications

This paper presents a silicon-on-insulator (SOI) fully integrated RF power amplifier for single-chip wireless transceiver applications. The integrated power amplifier (IPA) operates at 900 MHz, and is designed and fabricated using a 1.5-μm SOI LDMOS/CMOS/BJT technology. This technology is suitable for the complete integration of the front-end circuits with the baseband circuits for low-cost low-power high-volume production of single-chip transceivers. The IPA is a two-stage Class E power amplifier. It is fabricated along with the on-chip input and output matching networks. Thus, no external components are needed. At 900 MHz and with a 5-V supply, the power amplifier delivers 23-dBm output power to a 50-Ω load with 16-dB gain and 49% power-added efficiency     

一种65 nm CMOS 60 GHz高增益功率放大器

设计了一种基于65 nm CMOS工艺的60 GHz功率放大器。采用共源共栅结构与电容中和共源级结构相结合的方式来提高功率放大器的增益,并采用两路差分结构来提高输出功率。采用片上变压器作为输入/输出匹配及级间匹配,以减小芯片的面积,从而降低成本。采用Cadence、ADS和Momentum等软件进行联合仿真。后仿真结果表明,在工作频段为60 GHz时,最大小信号增益为26 dB,最大功率附加效率为18.6%,饱和输出功率为15.2 dBm。该功率放大器具有高增益、高效率、低成本等优点。     

SiGe bipolar transceiver circuits operating at 60 GHz

A low-noise amplifier, direct-conversion quadrature mixer, power amplifier, and voltage-controlled oscillators have been implemented in a 0.12-/spl mu/m, 200-GHz f/sub T/290-GHz f/sub MAX/ SiGe bipolar technology for operation at 60 GHz. At 61.5 GHz, the two-stage LNA achieves 4.5-dB NF, 15-dB gain, consuming 6 mA from 1.8 V. This is the first known demonstration of a silicon LNA at V-band. The downconverter consists of a preamplifier, I/Q double-balanced mixers, a frequency tripler, and a quadrature generator, and is again the first known demonstration of silicon active mixers at V-band. At 60 GHz, the downconverter gain is 18.6 dB and the NF is 13.3 dB, and the circuit consumes 55 mA from 2.7 V, while the output buffers consume an additional 52 mA. The balanced class-AB PA provides 10.8-dB gain, +11.2-dBm 1-dB compression point, 4.3% maximum PAE, and 16-dBm saturated output power. Finally, fully differential Colpitts VCOs have been implemented at 22 and 67 GHz. The 67-GHz VCO has a phase noise better than -98 dBc/Hz at 1-MHz offset, and provides a 3.1% tuning range for 8-mA current consumption from a 3-V supply.     

5~6GHz自适应线性化偏置的InGaP/GaAs HBT功率放大器

针对高质量无线局域网的传输需求,设计了一款工作在5~6 GHz的宽带磷化镓铟/砷化镓异质结双极型晶体管(InGaP/GaAs HBT)功率放大器芯片。针对HBT晶体管自热效应产生的非线性和电流不稳定现象,采用自适应线性化偏置技术,有效地解决了上述问题。针对射频系统的功耗问题,设计了改进的射频功率检测电路,以实现射频系统的自动增益控制,降低功耗。通过InGaP/GaAs HBT单片微波集成电路(MMIC)技术实现该功率放大器芯片。仿真结果表明,功放芯片的小信号增益达到32 dB;1 dB压缩点功率为28.5 dBm@5.5 GHz,功率附加效率PAE超过32%@5.5 GHz;输出功率为20 dBm时,IMD3低于-32 dBc。