Simulation and Experimental Study on the Junction Termination Structure for High-Voltage 4H-SiC PiN Diodes

Designing and fabrication of 10-kV 4H-SiC PiN diodes with an improved junction termination structure have been investigated. An improved bevel mesa structure and a single-zonejunction termination extension (JTE) have been employed to achieve a high breakdown voltage $(geq!hbox{10} hbox{kV})$ . The improved bevel mesa structure, nearly a vertical sidewall at the edge of the p-n junction and a gradual slope at the mesa bottom, has been fabricated by reactive ion etching. The effectiveness of the improved bevel mesa structure has been experimentally demonstrated. The JTE region has been optimized by device simulation, and the JTE dose dependence of the breakdown voltage has been compared with experimental results. A 4H-SiC PiN diode with a JTE dose of $hbox{1.1} times hbox{10}^{13} hbox{cm}^{-2}$ has exhibited a high blocking voltage of 10.2 kV. The locations of electric field crowding and breakdown are also discussed.      

Increase of Breakdown Voltage on AlGaN/GaN HEMTs by Employing Proton Implantation

The breakdown voltage of new AlGaN/GaN high electron mobility transistors (HEMTs) was increased considerably without sacrificing any other electrical characteristics by proton implantation. The breakdown voltage of proton-implanted AlGaN/GaN HEMTs with 150 KeV $hbox{1}times hbox{10}^{14} hbox{-}hbox{cm}^{-2}$ fluence after thermal annealing at 400 $^{circ}hbox{C}$ for 5 min under $hbox{N}_{2}$ ambient was 719 V, while that of conventional device was 416 V. The increase of the breakdown voltage is attributed to the expansion of the depletion region under the 2-D electron gas (2-DEG) channel. The depletion region expanded downward into the GaN buffer layer because implanted protons acted as positive ions and attracted electrons in the 2-DEG channel.      

A 10-kV Monolithic Darlington Transistor With $beta_{ rm forced}$ of 336 in 4H-SiC

4H-SiC bipolar Darlington transistors with a record-high current gain have been demonstrated. The dc forced current gain was measured up to 336 at 200 $hbox{W/cm}^{2}$ ( $J_{C} = hbox{35} hbox{A/cm}^{2}$ at $V_{rm CE} = hbox{5.7} hbox{V}$) at room temperature. The current gain exhibits a negative temperature coefficient and remains as high as 135 at 200 $^{circ}hbox{C}$. The specific on-resistance is 140 $hbox{m}Omegacdothbox{cm}^{2}$ at room temperature and increases at elevated temperatures. An open-emitter breakdown voltage $(BV_{rm CBO})$ of 10 kV was achieved at a leakage current density of $≪hbox{1} hbox{mA/cm}^{2}$. The device exhibits an open-base breakdown voltage $(BV_{rm CEO})$ of 9.5 kV. The high current gain of SiC Darlington transistors can significantly reduce the gate-drive power consumption with the same forward-voltage drop as that of 10-kV SiC bipolar junction transistors, thus making the device attractive for high-power high-temperature applications.      

1580-V–40-$hbox{m}Omegacdot hbox{cm}^{2}$ Double-RESURF MOSFETs on 4H-SiC $(hbox{000}bar{hbox{1}})$

Double-reduced-surface-field (RESURF) MOSFETs with $hbox{N}_{2}hbox{O}$ -grown oxides have been fabricated on the 4H-SiC $(hbox{000} bar{hbox{1}})$ face. The double-RESURF structure is effective in reducing the drift resistance, as well as in increasing the breakdown voltage. In addition, by utilizing the 4H-SiC $(hbox{000}bar{hbox{1}})$ face, the channel mobility can be increased to over 30 $hbox{cm}^{2}/hbox{V}cdothbox{s}$, and hence, the channel resistance is decreased. As a result, the fabricated MOSFETs on 4H-SiC $( hbox{000}bar{hbox{1}})$ have demonstrated a high breakdown voltage $(V_{B})$ of 1580 V and a low on-resistance $(R_{rm ON})$ of 40 $hbox{m}Omega cdothbox{cm}^{2}$. The figure-of-merit $(V_{B}^{2}/R_{rm ON})$ of the fabricated device has reached 62 $hbox{MW/cm}^{2}$, which is the highest value among any lateral MOSFETs and is more than ten times higher than the “Si limit.”      

High-Current-Gain SiC BJTs With Regrown Extrinsic Base and Etched JTE

This paper describes successful fabrication of 4H-SiC bipolar junction transistors (BJTs) with a regrown extrinsic base layer and an etched junction termination extension (JTE). Large-area 4H-SiC BJTs measuring 1.8 $times$ 1.8 mm (with an active area of 3.24 $hbox{mm}^{2}$) showed a common emitter current gain $beta$ of 42, specific on-resistance $R_{{rm SP}_{rm ON}}$ of 9 $hbox{m}Omegacdothbox{cm}^{2}$, and open-base breakdown voltage $hbox{BV}_{rm CEO}$ of 1.75 kV at room temperature. The key to successful fabrication of high-current-gain SiC BJTs with a regrown extrinsic base is efficient removal of the $hbox{p}^{+}$ regrown layer from the surface of the emitter–base junction. The BJT with $hbox{p}^{+}$ regrown layer has the advantage of lower base contact resistivity and current gain that is less sensitive to the distance between the emitter edge and the base contact, compared to a BJT with ion-implanted base. Fabrication of BJTs without ion implantation means less lifetime-reducing defects, and in addition, the surface morphology is improved since high-temperature annealing becomes unnecessary. BJTs with flat-surface junction termination that combine etched regrown layers show about 250 V higher breakdown voltage than BJTs with only etched flat-surface JTE.      

High-Voltage SOI SJ-LDMOS With a Nondepletion Compensation Layer

A new superjunction LDMOS on silicon-on-insulator (SOI) with a nondepletion compensation layer (NDCL) is proposed. The NDCL can be self-adaptive to provide additional charges for compensating the charge imbalance while eliminating the substrate-assisted depletion effect. In addition, the high-density oxide interface charges at the top surface of the buried oxide layer (BOX) enhance the electric field in the BOX and improve the vertical breakdown voltage (BV). Numerical simulation results indicate that a uniform surface electric field profile is obtained and that the vertical electric field in BOX is increased to $hbox{6} times hbox{10}^{6} hbox{V/cm}$, which results in a high BV of 300 V for the proposed device with the BOX thickness of 0.5 $muhbox{m}$ and drift length of 15 $muhbox{m}$ on a thin SOI substrate.      

Performance and Stability of Large-Area 4H-SiC 10-kV Junction Barrier Schottky Rectifiers

The forward and reverse bias dc characteristics, the long-term stability under forward and reverse bias, and the reverse recovery performance of 4H-SiC junction barrier Schottky (JBS) diodes that are capable of blocking in excess of 10 kV with forward conduction of up to 10 A at a forward voltage of less than 3.5 V (at 25 $^{circ}hbox{C}$) are described. The diodes show a positive temperature coefficient of resistance and a stable Schottky barrier height of up to 200 $^{circ}hbox{C}$. The diodes show stable operation under continuous forward current injection at 20 $hbox{A/cm}^{2}$ and under continuous reverse bias of 8 kV at 125 $^{circ}hbox{C}$. When switched from a 10-A forward current to a blocking voltage of 3 kV at a current rate-of-fall of 30 $hbox{A}/muhbox{s}$, the reverse recovery time and the reverse recovery charge are nearly constant at 300 ns and 425 nC, respectively, over the entire temperature range of 25 $^{circ}hbox{C}$–175 $^{circ}hbox{C}$.      

First Insight Into the Lifetime Acceleration Model of High-$k$ $hbox{ZrO}_{2}/hbox{SiO}_{2}/hbox{ZrO}_{2}$ Stacks for Advanced DRAM Technology Nodes

Long-term reliability results over six orders of magnitude in time are presented showing that the voltage acceleration model for $hbox{ZrO}_{2}/hbox{SiO}_{2}/hbox{ZrO}_{2}$ exhibits an exponential dependence with voltage, down to 2 V. The voltage acceleration parameter $gamma$ is between 10 and 15 $hbox{V}^{-1}$, depending on the biasing polarity. Soft-breakdown behavior (SILC) is evident prior to the onset of hard breakdown as a result of barrier lowering or charge accumulation in the high- $k$ film. Under ac stress conditions, this SILC branch is lowered in magnitude, translating to a gain in lifetime to breakdown.      

12-kV p-Channel IGBTs With Low On-Resistance in 4H-SiC

SiC bipolar devices are favored over SiC unipolar devices for applications requiring breakdown voltage in excess of 10 kV. We have designed and fabricated p-channel insulated-gate bipolar transistors (IGBTs) in 4H-SiC with 12-kV blocking voltage for high-power applications. A differential on-resistance of 18.6 $hbox{m}Omegacdothbox{cm}^{2}$ was achieved with a gate bias of 16 V, corresponding to a forward voltage drop of 5.3 V at 100 $ hbox{A/cm}^{2}$, indicating strong conductivity modulation in the p-type drift region. A moderately doped current enhancement layer grown on the lightly doped drift layer effectively reduces the JFET resistance while maintaining a high carrier lifetime for conductivity modulation. The p-channel IGBT (p-IGBT) exhibits a transconductance that is $hbox{3}times$ higher than that of the 12-kV n-channel SiC IGBTs. An inductive switching test was done at 1.5 kV and 0.55 A $(sim !!hbox{140} hbox{A/cm}^{2})$ for the p-IGBTs, and a turn-on time of 40 ns and a turn-off time of $sim !!hbox{2.8} muhbox{s}$ were measured.      

3510-V 390-$hbox{m}Omegacdothbox{cm}^{2}$ 4H-SiC Lateral JFET on a Semi-Insulating Substrate

The performance of high-voltage 4H-SiC lateral JFETs on a semi-insulating substrate is reported in this letter. The design of the voltage-supporting layers is based on the charge compensation of p- and n-type epilayers. The best measured breakdown voltage is 3510 V, which, to the authors' knowledge, is the highest value ever reported for SiC lateral switching devices. The $R_{rm on}$ of this device is 390 $hbox{m}Omegacdot hbox{cm}^{2}$, in which 61% is due to the drift-region resistance. The $BV^{2}/R_{rm on}$ is 32 $hbox{MW}/hbox{cm}^{2}$, which is typical among other reported SiC lateral devices.      

Extraction of Density of States in Amorphous GaInZnO Thin-Film Transistors by Combining an Optical Charge Pumping and Capacitance–Voltage Characteristics

A technique for extracting the acceptorlike density of states (DOS) of $n$ -channel amorphous GaInZnO (a-GIZO) thin-film transistors based on the combination of subbandgap optical charge pumping and $C$– $V$ characteristics is proposed. While the energy level is scanned by the photon energy and the gate voltage sweep, its density is extracted from the optical response of $C$–$V$ characteristics. The extracted DOS shows the superposition of the exponential tail states and the Gaussian deep states ($N_{rm TA} = hbox{2} times hbox{10}^{18} hbox{eV}^{-1} cdot hbox{cm}^{-3}$, $N_{rm DA} = hbox{4} times hbox{10}^{15} hbox{eV}^{-1} cdot hbox{cm}^{-3}$, $kT_{rm TA} = hbox{0.085} hbox{eV}$, $kT_{rm DA} = hbox{0.5} hbox{eV}$ , $E_{O} = hbox{1} hbox{eV}$). The TCAD simulation results incorporated by the extracted DOS show good agreements with the measured transfer and output characteristics of a-GIZO thin-film transistors with a single set of process-controlled parameters.      

Fabrication and Characterization of High-Current-Gain 4H-SiC Bipolar Junction Transistors

This paper reports on newly developed high-performance 4H-SiC bipolar junction transistors (BJT) with improved current gain and power handling capabilities based on an intentionally designed continuously grown 4H-SiC BJT wafer. The measured dc common-emitter current gain is as high as 70, the specific on -state resistance $(R_{{rm SP}hbox{-}{rm ON}})$ is as low as 3.0 $hbox{m}Omegacdothbox{cm}^{2}$, and the open-base breakdown voltage $(V_{rm CEO})$ reaches 1750 V. Large-area 4H-SiC BJTs with a footprint of 4.1 $times$ 4.1 mm have been successfully packaged into a high-gain $(beta = hbox{50.8})$ high-power (80 A $times$ 700 V) all-SiC copack and evaluated at high temperature up to 250 $^{circ}hbox{C}$. Small 4H-SiC BJTs have been stress tested under a continuous collector current density of 100 $hbox{A}/hbox{cm}^{2}$ for 24 h and, for the first time, have shown no obvious forward voltage drift and no current gain degradation. Numerical simulations and experimental results have confirmed that simultaneous high current gain and high open-base breakdown voltage could be achieved in 4H-SiC BJTs.      

Low-Voltage Organic Field-Effect Transistor With PMMA/$ hbox{ZrO}_{2}$ Bilayer Dielectric

This paper reports on the application of a bilayer polymethylmethacrylate (PMMA)/ $hbox{ZrO}_{2}$ dielectric in copper phthalocyanine (CuPc) organic field-effect transistors (OFETs). By depositing a PMMA layer on $hbox{ZrO}_{2}$, the leakage of the dielectric is reduced by one order of magnitude compared to single-layer $hbox{ZrO}_{2}$. A high-quality interface is obtained between the organic semiconductor and the combined insulators. By integrating the advantages of polymer and high- $k$ dielectrics, the device achieves both high mobility and low threshold voltage. The typical field-effect mobility, threshold voltage, on/off current ratio, and subthreshold slope of OFETs with bilayer dielectric are $hbox{5.6}timeshbox{10}^{-2} hbox{cm}^{2}/hbox{V} cdot hbox{s}$, 0.8 V, $hbox{1.2} times hbox{10}^{3}$, and 2.1 V/dec, respectively. By using the bilayer dielectrics, the hysteresis observed in the devices with single-layer $hbox{ZrO}_{2}$ is no longer present.      

High-Voltage LDMOS With Charge-Balanced Surface Low On-Resistance Path Layer

A high-voltage lateral double-diffusion MOSFET (LDMOS) with a charge-balanced surface low on-resistance path (CBSLOP) layer is proposed and experimentally demonstrated using a modified CMOS process. The CBSLOP layer can not only provide a low on-resistance path in the on-state but also keep the charge balance between the N and P pillars of a surface low on-resistance path in the off-state, which results in improved breakdown voltage (BV). The experimental results show that the CBSLOP-LDMOS with a drift length of 35 $mu hbox{m}$ exhibits a BV of 500 V and specific on-resistance $(R_{{rm on}, {rm sp}}!)$ of 96 $hbox{m}Omega cdot hbox{cm}^{2}$, yielding to a power figure of merit $(BV^{2}!!/ !R_{{rm on}, {rm sp}})$ of 2.6 $hbox{MW}/hbox{cm}^{2}$ . The excellent device performances, coupled with a CMOS-compatible fabrication process, make the proposed CBSLOP-LDMOS a promising candidate for smart power integrated circuit.      

Operation of Pt/AlGaN/GaN-Heterojunction Field-Effect-Transistor Hydrogen Sensors With Low Detection Limit and High Sensitivity

To enhance the device sensitivity and detection limit, a gate bias is applied to the catalytic metal of AlGaN/GaN-heterojunction field-effect-transistor (HFET) hydrogen sensors to control the carrier concentration in the channel at operation. The sensors exhibit a good sensitivity at temperatures up to 800 $^{circ}hbox{C}$ and a detection limit of 10-ppb $ hbox{H}_{2}$ in $hbox{N}_{2}$. The dependence of the device sensitivity on gate and drain biases has been investigated. The sensitivity peaks at the gate bias of threshold voltage and the drain bias of knee voltage in sensing gas. At high temperatures and $hbox{H}_{2}$ concentrations, specifically from 300 $^{circ}hbox{C}$ and 1000-ppm $hbox{H}_{2}/hbox{N}_{2}$, respectively, the sensitivity of HFETs at $V_{rm gs} = -hbox{3.5} hbox{V}$ and $V_{rm ds} = hbox{1} hbox{V}$ is more than three orders higher than their sensitivity at $V_{rm gs} = hbox{0} hbox{V}$ and the sensitivity of Schottky diodes.      

Effect of Oxygen Pressure on the Electrical Properties of $hbox{Bi}_{5} hbox{Nb}_{3}hbox{O}_{15}$ Films Grown by RF Magnetron Sputtering

$hbox{Bi}_{5}hbox{Nb}_{3}hbox{O}_{15} (hbox{B}_{5}hbox{N}_{3})$ films grown under a low oxygen partial pressure (OP) of 1.7 mtorr showed a high leakage current density of 0.1 $hbox{A/cm}^{2}$ at 1.0 MV/cm. However, the leakage current density decreased with increasing OP to a minimum of $hbox{5.8} times hbox{10}^{-9} hbox{A/cm}^{2}$ for the film grown under 5.1 mtorr due to the decreased number of oxygen vacancies. This film also showed an improved breakdown field of 2.2 MV/cm and a large capacitance density of 24.9 $hbox{fF}/muhbox{m}^{2}$. The electrical properties of the film, however, deteriorated with a further increase in OP, which is probably due to the formation of oxygen interstitial ions. Therefore, superior electrical properties for the $ hbox{B}_{5}hbox{N}_{3}$ film can be obtained by careful control of OP.      

Power Trench MOSFET Devices on Metal Substrates

Power trench MOSFET devices have been accomplished on Cu substrates using a novel silicon-on-metal (SOM) technology. This technology transfers silicon trench MOSFET device layers from SOI wafers to metal substrates. The prototype 30-V (drain-to-source voltage) n-channel SOM device with a pitch of 2.5 $muhbox{m}$ comprises a 5-$muhbox{m}$ device layer and an electroplated Cu substrate. These devices are the first of their kind exhibiting a negligible substrate drain contribution to their specific Rdson and have a specific Rdson of 0.198 $ hbox{m} Omega cdot hbox{cm}^{2}$ at a gate voltage of 10 V. This specific Rdson is 38% smaller than that of the same device on the silicon substrate. The dc–dc converter with SOM devices shows 11% reduction in device power loss and an energy efficiency of about 2% higher than with the same Si-based devices. The operating temperature of the SOM die in the converter is also 9 $^{circ} hbox{C}$ lower than the Si-based die. The “cooler” SOM device is due to primarily improved energy efficiency. The transient thermal resistance of the SOM device is 20 $^{circ}hbox{C/W}$, which is less than half of 57.5 $^{ circ}hbox{C/W}$ for the Si-based device at a pulse duration of 10 s.      

Innovative Voltage Driving Pixel Circuit Using Organic Thin-Film Transistor for AMOLEDs

In this work, we propose a novel active-matrix organic light-emitting diode displays (AMOLED) pixel circuit based on organic thin-film transistor (OTFT) architecture, which consisted of four switches, one driving transistor, and a capacitor. The pentacene-based OTFT device possesses a field-effect mobility of 0.1 ${hbox{cm}}^{2} /{hbox{V}}cdot{hbox{s}}$, a threshold voltage of $-{hbox{1.5}}~{hbox{V}}$ , subthreshold slope of 1.8 V/decade and an on/off current ratio ${hbox{10}} ^{6}$. The resultant voltage-driving pixel circuit, named “Complementary Voltage-Induced Coupling Driving” (CVICD), is different from the current-driving scheme and can appropriately operate at low gray level for the low-mobility OTFT circuitry. The current non-uniformity less than 2.9% is achieved for data voltage ranging from 1 to 17 V by SPICE simulation work. In addition, the new external driving method can effectively reduce the complexity of OLED pixel circuitry.      

AlGaN/GaN MOSHEMTs With Liquid-Phase-Deposited $ hbox{TiO}_{2}$ as Gate Dielectric

$hbox{TiO}_{2}$ films deposited on GaN layers at room temperature through a simple and low-cost liquid-phase deposition (LPD) method are investigated and served as gate dielectrics in AlGaN/GaN MOSHEMTs. The electrical characteristics of the MOS structure on n-doped GaN show that the leakage current is about $hbox{1.01} times hbox{10}^{-7} hbox{A/cm}^{2}$ at 1 MV/cm and that the breakdown field is more than 6.5 MV/cm. The maximum drain current density of MOSHEMTs is higher than that of conventional HEMTs, and a wider gate voltage swing can also be observed. The maximum transconductance and threshold voltage almost maintain the same characteristics, even after inserting a dielectric layer between the gate metal and the 2DEG channel by using $ hbox{TiO}_{2}$ as a gate dielectric. The gate leakage current density is significantly improved, and the bias stress measurement shows that current collapse is much suppressed for MOSHEMTs.      

Bandgap-Engineered Ga-Rich GaZnO Thin Films for UV Transparent Electronics

Ga-rich GaZnO thin films were prepared by metal–organic chemical vapor deposition. The optical bandgap of GaZnO films can be engineered from 3.3 to 4.9 eV by varying the Ga content. The film is amorphortized and the resistivity increases with an increase of Ga content. The Ga-rich GaZnO alloy with lower resistivity is investigated as a UV transparent conductor, while the semi-insulating Ga-rich GaZnO film with high transparency at 280–900 nm is employed as the channel layer to fabricate deep UV transparent thin-film transistor. The transistor shows a typical n-channel field-effect characteristic with a current on/off ratio of $hbox{10}^{4}$–$ hbox{10}^{5}$, a threshold voltage of $sim$42 V, a saturated field-effect mobility of $sim!hbox{0.06} hbox{cm}^{2} cdot hbox{V}^{-1} cdot hbox{s}^{-1}$, and a subthreshold swing of $ sim!hbox{7.7} hbox{V} cdot hbox{decade}^{-1}$.