Lateral resurfed COMFET

A lateral resurfed COMFET structure is proposed. The conductivity of the drift region of the device is modulated as in the case of vertical COMFET. However, the maximum operating current and switching speed are expected to be several times that of the vertical structure because of the collection of excess minority carriers by the p?-substrate and the narrow width of the n? epitaxial layer.     

Linear composite MOSFETs (COMFETs)

MOS linear circuit design remains a challenging task due to the nonlinear characteristics of the MOSFET. A generalised method of designing MOS linear circuits making use of linear composite MOSFET (COMFET) circuit structures as versatile basic circuit building blocks is described. The COMFET is linear in its composite-rain current and in its composite-source current with respect to its composite-gate-source voltage, assuming the square-law saturated drain current characteristic of the MOSFET.<>     

A novel method for extraction of VDMOSFET model parameters using neural networks

A novel method for extraction of model parameters based on neural networks is presented and exemplified through its application to extraction of ON-state model parameters of power VDMOSFETs. The method can be widely and efficiently used for parameter extraction of ON-state and transient analytical models for a large class of microelectronic devices.     

The Design of an Intelligent High-Speed Loom Industry Interconnection Remote Monitoring System

This work proposed the design of low power Si_0.7Ge_0.3 pocket Junction-less TFET (JLTFET) on bulk silicon using below 5 nm technology. The inclusion of junction-less regions improves ON-state current with lesser effect on OFF-state current. The p-type pocket regions added to improve device performance in subthreshold region showing reduction in OFF-state leakage current leading to good value of ON/OFF current ratio as compared to other similar TFET structures. A high-value I_ON/I_OFF ratio and good subthreshold behavior are observed for pocket JLTFET with 2 nm gate length and body thickness 0.5 nm. The proposed JLTFET is further optimized for different gate contact and oxide materials. The temperature analysis plays major role in deciding a reliable ON-state and OFF-state performance of transistors. So, the proposed pocket JLTFETis investigated for harsh temperature conditions to characterize the performance for DC and AC parameters. The sensitivity of proposed JLTFET is analyzed under different temperature conditions in range of (200–400) K to observe subthreshold performance such as transfer characteristics, Output characteristics and I_ON/I_OFF ratio. The proposed designs for JLTFETs have been simulated using TCAD 2D/3D device simulator.

     

Measurements of failure phenomena in inductively loadedmulti-cathode GTO thyristors

The free-carrier absorption (FCA) technique is used for mapping of the carrier content in a dual-cathode gate turn-off thyristor (GTO) at different stages of the turn-off cycle. The FCA technique outputs 3-D maps based on 2-D measurements of local carrier concentration. The measurements are time resolved, thus making a transient response converted into a corresponding sequence of carrier maps. The dual-cathode device is shown to be sufficient for determining the transient behavior in a multicathode structure. The destruction mechanism and reasons for turn-off failure are investigated. The GTO device is inductively loaded and asymmetrically gate contacted in order to emulate a realistic mode of operation. The gate-driving conditions are altered, and the importance of the turn-off gain for turn-off failure is established. The case of equal ON-state cathode currents in both segments is particularly highlighted. The influence of snubber circuits is also discussed     

A new metal-to-metal antifuse with amorphous carbon

We report the development of a new metal-to-metal antifuse with amorphous carbon as the dielectric. Amorphous carbon antifuses have several characteristics making them superior to amorphous silicon antifuses, including lower values of OFF-state leakage current, ON-state resistance, dielectric constant, and breakdown voltage. Most importantly, amorphous carbon antifuses do not show ON-OFF switching, which is observed in amorphous silicon antifuses. A new model is proposed to explain the breakdown mechanism and ON-state reliability of amorphous carbon antifuses     

Memory effect in the current-voltage characteristic of 8-hydroquinoline aluminum salt films

This letter investigated the reproducible bistable resistance switching characteristics of a single-layer organic device based on 8-hydroquinoline aluminum (Alq3) fabricated by spin coating. By controlling the ON-state current through the Alq3 films, it has been possible to achieve various resistance states of the films. In addition, the resistance of the ON-state Alq3 films also affects the threshold current and voltage to switch off the device. The independence of the current-injected direction to erase the ON state implies that the filament theory could elucidate the observed phenomenon. The ratio between low- and high-resistance states can reach five orders of magnitude, which will be a potential material for nonvolatile memory application.     

Nonpolar Nonvolatile Resistive Switching in Cu Doped $hbox{ZrO}_{2}$

In this letter, the unique reproducible nonpolar resistive switching behavior is reported in the Cu-doped ZrO₂ memory devices. The devices are with the sandwiched structure of Cu/ZrO₂:Cu/Pt. The switching between high resistance state (OFF-state) and low resistance state (ON-state) does not depend on the polarity of the applied voltage bias and can be achieved under both voltage sweeping and voltage pulse. The ratio between the high and low resistance is on the order of 10⁶. Set and Reset operation in voltage pulse mode can be as fast as 50 and 100 ns, respectively. No data loss is found upon continuous readout for more than 10⁴ s. Multilevel storage is considered feasible due to the dependence of ON-state resistance on Set compliance current. The switching mechanism is believed to be related with the formation and rupture of conducting filamentary paths.     

High-Voltage Self-Aligned p-Channel DMOS-IGBTs in 4H-SiC

SiC power MOSFETs designed for blocking voltages of 10 kV and higher face the problem of high drift layer resistance that gives rise to a high internal power dissipation in the ON -state. For this reason, the ON-state current density must be severely restricted to keep the power dissipation below the package limit. We have designed, optimized, and fabricated high-voltage SiC p-channel doubly-implanted metal-oxide-semiconductor insulated gate bipolar transistors (IGBTs) on 20-kV blocking layers for use as the next generation of power switches. These IGBTs exhibit significant conductivity modulation in the drift layer, which reduces the ON-state resistance. Assuming a 300 W/cm² power package limit, the maximum currents of the experimental IGBTs are 1.2x and 2.1x higher than the theoretical maximum current of a 20-kV MOSFET at room temperature and 177 degC, respectively.     

Current Collapse and High-Electric-Field Reliability of Unpassivated GaN/AlGaN/GaN HEMTs

Long-term ON-state and OFF-state high-electric-field stress results are presented for unpassivated GaN/AlGaN/GaN high-electron-mobility transistors on SiC substrates. Because of the thin GaN cap layer, devices show minimal current-collapse effects prior to high-electric-field stress, despite the fact that they are not passivated. This comes at the price of a relatively high gate-leakage current. Under the assumption that donor-like electron traps are present within the GaN cap, two-dimensional numerical device simulations provide an explanation for the influence of the GaN cap layer on current collapse and for the correlation between the latter and the gate-leakage current. Both ON-state and OFF-state stresses produce simultaneous current-collapse increase and gate-leakage-current decrease, which can be interpreted to be the result of gate-drain surface degradation and reduced gate electron injection. This study shows that although the thin GaN cap layer is effective in suppressing surface-related dispersion effects in virgin devices, it does not, per se, protect the device from high-electric-field degradation, and it should, to this aim, be adopted in conjunction with other technological solutions like surface passivation, prepassivation surface treatments, and/or field-plate gate     

The impact of static and dynamic degradation on SOI “smart-cut” floating body MOSFETs

The impact of static (DC) and dynamic (AC) degradation on SOI “smart-cut” floating body MOSFETs, was investigated by means of deep level transient spectroscopy (DLTS). The study was based on drain current signal recording, immediately after the transistor transition from OFF- to ON-state. In order to isolate the activity of capture/emission carrier mechanisms, undesirable parasitic effects such as drain current overshoot were suppressed by appropriately biasing the transistor substrates. Under DC degradation regime, DLTS spectra disclosed that carrier capture/emission process occurred through discrete traps governed by thermally activated mechanisms. Furthermore, polarization phenomena emerged. Under AC degradation regime, although the existence of interface states in Si-SiO2 interface was dominant, the revelation of shallow traps in low temperature domain was also monitored.     

具有光纤自定位保持结构的2×2扭转微镜光开关阵列的制作和机电特性

应用基于表面硅、体硅微电子工艺的混合微加工技术,制作了新型2×2扭转微镜光开关阵列,并研究了其在外加静电场和交变电场中的机电特性.当该光开关中悬挂多晶硅微镜的弹性扭转梁的厚度约为1μm时,驱动微镜以实现其"开"状态的拐点静电电压为270～290V,而维持微镜"开"状态的最低保持电压在55V左右.理论分析表明,在关于该光开关结构的一系列设计参数中,拐点静电电压对于弹性扭转梁的厚度最敏感.该光开关的开关寿命超过108次,而其开关时间预计小于2ms.对单片集成制造在该光开关阵列芯片上的两种新型光纤自定位保持结构的力学分析表明,它们具有光纤自固定、自对准的性质.     

Double-interdigitated (TIL) bipolar power transistors with lightlydoped collectors

The results of an investigation concerning the implementation of the two-interdigitation-level (TIL) concept in TO-3-packaged, triple-diffused bipolar power n-p-n transistors with lightly doped collector are discussed. It is demonstrated that the TIL concept, which offers a fair balance between manufacturability ease/cost effectiveness and overall electrical performances, allows for an increase of both the DC and small-signal current gains and the voltage ratings of bipolar transistors. The peculiarities of the ON-state current carrying mechanism in TIL-type transistors was investigated and its impact on device behavior was also assessed     

具有光纤自定位保持结构的2×2扭转微镜光开关阵列的制作和机电特性

应用基于表面硅、体硅微电子工艺的混合微加工技术,制作了新型2×2扭转微镜光开关阵列,并研究了其在外加静电场和交变电场中的机电特性.当该光开关中悬挂多晶硅微镜的弹性扭转梁的厚度约为1μm时,驱动微镜以实现其"开"状态的拐点静电电压为270～290V,而维持微镜"开"状态的最低保持电压在55V左右.理论分析表明,在关于该光开关结构的一系列设计参数中,拐点静电电压对于弹性扭转梁的厚度最敏感.该光开关的开关寿命超过108次,而其开关时间预计小于2ms.对单片集成制造在该光开关阵列芯片上的两种新型光纤自定位保持结构的力学分析表明,它们具有光纤自固定、自对准的性质.     

Current balancing in TIL GTO thyristors

Based on the advanced three-transistor model of the two interdigitation levels (TIL) GTO thyristor structure, the theory underlying the device behavior in the ON-state is developed and experimentally validated. The mechanisms underlying the current balancing between the two p-n-p-n sections (standard and quasi-nonregenerative) constituting the TIL GTO structure are disclosed. It is shown that thanks to the current balancing, the effective cathode emitter area increases with the anode current level and that the current density along the standard p-n-p-n sections lags behind the level of load current iT. The broad implications of reported theoretical/experimental results for the physics of the novel device are outlined in the communication. It is shown, e.g., that current balancing is responsible for the drastic boost of the peak interruptable anode current IATOreported for the recently developed TIL GTO thyristors.     

An analytical model for the power bipolar-MOS transistor

This paper presents an analytical model for the I–V characteristics of the bipolar-MOS power transistor, also known as IGT or COMFET. Good agreement between this model and experiments is found over a wide range of carrier lifetime and current density. The predicted trade-off between the forward voltage drop and device turn-off time (0.4–10 μsec) has been verified by experiment. For even shorter switching time, the model predicts only a moderate increase in V_F. Adding a more heavily doped buffer epitaxial layer is shown to only slightly increase V_F but offers several important benefits. The comparison between n-channel and p-channel devices is discussed using the model and the forward voltage drops for the two types of devices are shown to differ by only a small percentage in spite of the large difference in electron and hole mobilities.     

The role of tunnel barriers in phase-state low electron-numberdrive transistors (PLEDTRs)

This paper presents a numerical analysis of the role of tunnel barriers in explaining the experimental I-V characteristics of a new vertical tunnel transistor called phase-state low electron-number drive transistor (PLEDTR), used for constructing a high-speed and high-capacity gain cell. Introducing the characteristic features of tunneling current through ultrathin barriers into a standard two-dimensional (2-D) drift-diffusion (DD) device simulator by way of calibrating it with a self-consistent one-dimensional (1-D) Poisson/Schrodinger equation solver, it is shown that the transistor characteristics at the ON-state are substantially affected by the thickness of the source barrier. Current saturation observed at low source-drain voltages is found to result from tunnelling injection via the source barrier. Asymmetric source and drain barrier (SDBs) structures are found to be responsible for the large asymmetry of the I-V characteristics at large source-drain voltages found experimentally. It is also shown that the central shutter barriers (CSBs) reduce the overall drain current in the subthreshold regime, leading to superior OFF current characteristics     

Analysis and synthesis of pHEMT class-E amplifiers with shunt inductor including ON-state active-device resistance effects

In this theoretical paper, the analysis of the effect that ON-state active-device resistance has on the performance of a Class-E tuned power amplifier using a shunt inductor topology is presented. The work is focused on the relatively unexplored area of design facilitation of Class-E tuned amplifiers where intrinsically low-output-capacitance monolithic microwave integrated circuit switching devices such as pseudomorphic high electron mobility transistors are used. In the paper, the switching voltage and current waveforms in the presence of ON-resistance are analyzed in order to provide insight into circuit properties such as RF output power, drain efficiency, and power-output capability. For a given amplifier specification, a design procedure is illustrated whereby it is possible to compute optimal circuit component values which account for prescribed switch resistance loss. Furthermore, insight into how ON-resistance affects transistor selection in terms of peak switch voltage and current requirements is described. Finally, a design example is given in order to validate the theoretical analysis against numerical simulation.     

Floating base thyristor

The floating base thyristor (FBT) is a new thyristor structure in which its p-base region, containing a p⁺ region is not shorted to the n⁺ emitter. Using the DMOS process, an n-channel and a p-channel MOSFET are integrated with the thyristor structure. The device operates in the thyristor mode with a low ON-state voltage drop at even high current densities when a positive bias is applied to, both gates. When a negative bias is applied to the OFF gate, the device operates in the IGBT mode with the saturated current controlled by the positive bias applied to the ON gate