Massively parallel systolic‐array architectures for 2d IIR polyphase space–time plane‐wave beam digital filters

A systolic architecture has recently been proposed for implementing two‐dimensional infinite impulse response (IIR) space–time beam plane‐wave filters at a throughput of one‐frame‐per‐clock–cycle for such applications as real‐time broadband smart antennas. A novel polyphase systolic architecture is proposed here that further increases the throughput of these IIR beam filters, by a factor of M, to M‐frames‐per‐clock‐cycle, where M is the number of polyphases. The proposed method combines the polyphase approach, along with pipelining and look‐ahead optimization methods, to achieve frame sample frequencies that are several times higher than the clock‐cycle limit of the very large‐scale integration (VLSI) technology, thereby potentially allowing multi‐GHz frame sample frequencies using current custom VLSI circuits. The implementation of a field programmable gate array‐based real‐time prototype is described, tested and verified for the two‐phase case (M = 2) at a technology‐limited clock frequency of 50 MHz which corresponds to a throughput of 100 million‐frames‐per‐clock–cycle. Copyright © 2010 John Wiley & Sons, Ltd.     

直流电机的高频电磁噪声及其防护

传统的DC电机只关心窄带滤波,如AM和FM频带。然而更多提供的消费类电子产品,诸如汽车现在需要滤除的频带从kHz到GHz。传统用于滤除窄带的电容﹑电感和铁氧体性能由于受限于他们的尺寸、寄生参数以及在许多电机应用中的费效比问题,难于实现宽带特性。本文的目的是研究提供宽带滤波性能的有效途径。对于滤除直流电机的宽带噪声,本文试验使用镜像理论并提出以X2Y~滤波器为核心的防护技术。     

Systolic digital filters with reduced latency—serial implementation

Schemes that implement finite impulse response (FIR) and infinite impulse response (IIR) digital filters when bit-serial or digit-serial arithmetic is used are proposed in this paper. The main objective is to obtain reduced latency (minimal latency at the word level) of the filter outputs while maintaining the word rate. Existing schemes (systolic or not) for filters are transferred down to the digit level and regular structures systolic at the bit or digit level are proposed. First a modified representation of a digital filter signal flow-graph appropriate for bit-serial or digit-serial arithmetic is presented. Next we show how the resulting flow-graph can be transformed to lead directly to a systolic implementation at the bit or word level. We aim towards minimizing the latency of the filter response. For this reason we work with bidirectional signal flow-graphs that lead to systolic arrays where data and partial results move in opposite directions, otherwise called two-way pipeline systolic arrays. The multipliers that are used in the implementation of the filters must have low latency themselves. For this reason they have the same two-way pipeline structure. In order to maintain the data word rate, the full-bit output of a multiplier must be rounded by a number of bits equal to the length of the data words. We propose a composite bit-serial multiplier that performs this rounding while preserving low latency and incorporate it in schemes for direct implementation of low-latency high-throughput systolic arrays for FIR and IIR digital filters. These schemes for bit-serial multipliers and filters are also extended to digit-serial arithmetic.     

基于FPGA的APF控制器的硬件结构优化

提出一种基于现场可编程门阵列（FPGA）的并联型有源电力滤波器（SAPF）的控制器方案。通过简化算法,使用运算强度简化、折叠结构和流水线等方式优化了控制器的硬件结构和工作频率,并详细讨论了基于同步旋转坐标变换、无限冲击响应（IIR）低通滤波器、三相锁相环和滞环电流跟踪控制的结构设计与优化。全部控制算法在单片FPGA中用硬件描述语言VerilogHDL实现。样机实验结果表明系统的动静态性能都较好,满足高性能SAPF对控制器实时性和准确性的要求。     

单一测量元件故障导致直流测量系统切换后保护误动的反措

2014年3月4日云广直流发生了直流过压保护（59/37DC II）动作跳闸事件,暴露出直流测量系统切换不能避免单一测量元件故障导致的保护误动问题。对该事件的分析发现,59/37DC II保护和基于IIR2滤波功能模块的行波保护（WFPDL）、电压突变量保护（27du/dt）、接地极母线保护（87EB）在测量系统切换后都存在着数据不能及时跟随问题。通过引入TDM总线的切换信号,并取消59/37DC II段保护的保护差值平均值处理的方法解决了59/37DC II保护的问题,采用IIR2S滤波功能模块替换IIR2滤波功能模块,并利用TDM总线切换信号进行处理,解决了WFPDL、27du/dt、87EB保护的问题。仿真和现场运行情况证实了所提措施的正确性。     

Adaptive IIR filtering algorithms for system identification: ageneral framework

Adaptive IIR (infinite impulse response) filters are particularly beneficial in modeling real systems because they require lower computational complexity and can model sharp resonances more efficiently as compared to the FIR (finite impulse response) counterparts. Unfortunately, a number of drawbacks are associated with adaptive IIR filtering algorithms that have prevented their widespread use, such as: convergence to biased or local minimum solutions; requirement of stability monitoring; and slow convergence. Most of the recent research effort on this field is aimed at overcoming some of the above mentioned drawbacks. In this paper, a number of known adaptive IIR filtering algorithms are presented using a unifying framework that is useful to interrelate the algorithms and to derive their properties. Special attention is given to issues such as the motivation to derive each algorithm and the properties of the solution after convergence. Several computer simulations are included in order to verify the predicted performance of the algorithms     

IIR filter scaling for real-time signal processing

Students generally have difficulty implementing infinite impulse response filters (IIR) using fixed-point arithmetic. Most of the trouble is with amplitude scaling the filter and representing the coefficients in the fixed-point format. The authors present a systematic procedure for scaling a second-order IIR filter which is used as the basic building block of higher-order filters. A simple simulation program is used to estimate the size of the signals at the summing nodes of the filter section. Once the estimates are known, the filter section can he reliably scaled. The procedure is clarified by implementing a second-order resonant filter on a digital signal processor: the TMS320C25     

基于FPGA的宽带噪声发生器的设计

随着宽带雷达信号的不断发展,需要宽带的噪声干扰信号.提出了一种宽带数字高斯白噪声产生的方法,通过FPGA并行产生4路m序列,并使用多相滤波技术进行滤波,然后将4路信号合成2路信号输入到DAC,最后进行放大滤波得到模拟的宽带白噪声.设计的核心是多路m序列发生和FIR多相滤波器,详细分析了多路m序列发生算法和FIR多相滤波算法.应用Verilog HDL语言实现模块功能性设计,该系统采用Stratix Ⅳ芯片EP4SGX230和双输入高速数模转换器AD9739,可实现宽带噪声的输出.     

MATLAB环境下IIR滤波器设计、仿真与验证

介绍了IIR数字滤波器的特点及模型.在MATLAB环境下用fdatool工具以及程序2种方法设计lIR滤波器系数,并编写IIR.m程序实现IIR滤波器功能.以实际混频信号为例实现IIR滤波器的仿真,最后利用MATLAB工具系统函数验证了自行设计的IIR.m程序的正确性.研究结果表明,自行设计的IIR.m程序能达到与MA...     

FIR and IIR digital filters

A digital filter is a basic building block in any digital signal processing (DSP) system. The simulation results presented show how finite bit precisions can affect the performance of a digital filter. IIR filters are shown to be even more susceptible to finite bit precision effects than FIR filters. However, these effects can be reduced using the IIR filter with a cascaded structure     

音频多段均衡处理算法研究与DSP实现

针对音频不同播放设备的频率响应不同的特点,设计了一种用于音频频率均衡调节与噪声消除的Equalizer算法并在DSP上进行实现。基于数字信号处理时域滤波原理,设计了不同频段可通的IIR低通及高通滤波器,不同频带设置不同的增益,输入音频经过IIR滤波器后的输出信号进行叠加,实现音频 在不同频率处能量改变的调节效果;同时设计了单独且可控的噪声抑制器,其由50阶的FIR带阻滤波器组成,用于指定频率的噪声衰减。测试表明,该算法最高可处理16KHz的16Bit数字音频信号,实现了对特定频段噪声的滤除。     

A new three‐input/output characteristic‐varying filter in the D‐module for direct processing of three‐phase signals

This paper proposes a new three‐input and three‐output characteristic‐varying filter in the D‐module for direct processing of three‐phase signals, which are becoming indispensable for effective active compensation of three‐phase power such as harmonics current, negative phase current, reactive power, and varying voltage compensations. The filter in the D‐module can show different filtering characteristics to positive, negative, and zero phase components of three‐phase signals and can allow direct processing of the signals based on frequency polarities. The filter in the D‐module can also change dynamically its filtering characteristics by simply injecting a shift‐signal to itself. These filtering effects are obtained in a very simple manner using the D‐module. A new unified analysis of attractive general characteristics of the proposed filter in the D‐module is given for its easy designs and realizations as well. Effectiveness of the analysis and usefulness of the filter in the D‐module are newly examined and confirmed through experiments. The newly proposed filter in the D‐module has potential regarding a variety of three‐phase signal filtering applications. © 2003 Wiley Periodicals, Inc. Electr Eng Jpn, 145(1): 28–38, 2003; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.10170     

预防性安全约束最优潮流的主导故障过滤技术

运用适当的故障过滤方法筛选有效的预想故障,可以提高预防性的静态安全约束最优潮流的计算效率。提出一种新的应用于预防性静态安全约束最优潮流的故障过滤方法,该方法根据故障引起的约束条件越限的程度,将故障区分为主导故障和非主导故障两类。迭代过程中,只将主导故障引入到安全约束最优潮流中计算,经过几次迭代即可求出结果。在IEEE-4、IEEE-14和IEEE-30节点系统上测试本文过滤技术,测试结果表明:应用主导故障过滤技术减小了每次计算的安全约束最优潮流的规模,有效的提高了预防性静态安全约束最优潮流的计算效率。     

引入IIR滤波器对换流变增量差动暂态性能的影响分析

通过分析比较特高压直流工程与传统直流工程中换流变保护配置的异同,指出特高压直流工程中换流变保护引入了IIR数字滤波器进行数据预处理。分别从数字滤波器型式及阶数两个角度,利用滤波器辅助设计工具进行了滤波器参数设计,对引入IIR数字滤波器进行数据预处理对换流变及引线大差增量差动保护暂态性能影响进行了仿真分析,仿真结果表明在满足继电保护系统对低通滤波频率特性的要求下,采用4阶巴特沃斯低通滤波器为最优,满足相关规范对其暂态性能要求。     

基于SVG控制应用的数字滤波器实用设计

IIR型数字滤波器凭借其优良的衰减特性在利用软件处理信号的场合应用广泛。针对无功发生器(svg)控制保护装置应用程序开发过程中所使用的IIR数字滤波器,利用MATLAB中的FDAtool工具获得阶数和传递函数系数,并通过微调零极点位置获得较为理想的幅频曲线,并输出系数写入控制程序的函数中;分析采样周期对滤波器零极点位置的影响,在不同采样周期下,数字滤波器零极点位置发生改变,产生新的传递函数系数。经过在实际装置中的测试,获得了良好的滤波效果。     

雷电冲击电压波形K因子零相位数字滤波器设计

针对最新版IEC60060-1《高电压试验技术,第一部分:一般定义及试验要求》中叠加过冲和振荡的标准雷电冲击波形的数字处理程序,其引入与频率相关的试验电压因数k(f),介绍一种设计等价于k(f)对应转移函数的K因子零相位IIR数字滤波器的方法。对零相位数字滤波原理进行了分析与仿真实验。基于IEC60060-1中定义的试验电压因数k(f),给出了设计K因子零相位IIR数字滤波器的推导过程,以及可用于开发冲击电压测量软件的时域滤波差分方程。最后对最新版IEC61083-2《高压冲击试验测量用仪器和软件,第二部分:对软件的要求》附带的TDG 2.04中几种典型雷电冲击电压波形进行了滤波处理与参数提取,验证了该方法的可行性和准确性。为研制冲击电压测量系统提供了一种实用的数字滤波技术。     

基于自适应陷波器的科氏流量计信号频率跟踪新方法

为提高对科氏流量计信号频率随机缓慢变化的持续跟踪能力,以对格型ANF、简化格型ANF和基于SMM的新式ANF三种典型自适应陷波器的性能比较分析为基础,提出了一种科氏流量计信号频率跟踪新方法。该方法对频率、幅值和相位均随机游动变化的科氏流量计信号,首先采用新式ANF快速检测信号频率并作短时频率跟踪,待其收敛后简化格型ANF开始并行工作,在简化格型ANF收敛后取代新式ANF持续跟踪信号频率的变化。仿真结果表明,本文方法比格型ANF方法收敛速度更快、频率跟踪精度更高,比单一采用新式ANF方法计算更为简便,是一种科氏流量计信号处理的有效方法。     

基于有源滤波器的电力系统间谐波抑制研究

目前电力系统中间谐波的污染日趋严重,必须对间谐波引起高度的重视.从实际应用的角度出发,阐述了有源滤波器有限长冲激响应滤波器和无限长冲激响应滤波器的原理,通过Matlab软件对等波纹线性相位FIR带通滤波器、加卡塞尔窗的FIR带通滤波器和巴特沃斯IIR型带通滤波器的滤波仿真,得出巴特沃斯ⅡR型带通滤波器对间谐波的抑制作用...     

IIR滤波器在DTMF信号检测与识别中的研究

根据戈泽尔算法的推导DTF可以看作是一个二阶IIR滤波器的零状态响应。利用IIR滤波器与戈泽尔算法相结合的方法来提高双音多频信号检测的准确性和稳定性,以期解决信号检测对专用解码芯片的依赖。研究中使戈泽尔序列分别通过IIR滤波器和通用滤波器,对比二者的输出结果。结果表明,IIR滤波器与戈泽尔算法相结合有助于提高双音多频信号检测的准确性和稳定性。通过DTMF信号检测的MATLAB的仿真,证明了将带有IIR滤波器的戈泽尔算法移植到DSP硬件上能够解决对专用解码芯片的依赖。     

基于进化硬件的自适应形态滤波器设计

针对电力信号监测中可能遇到的各种干扰,提出了一种基于进化硬件的自适应电力系统形态滤波器的设计方法。不仅滤波算法可自适应调节,而且结构元素形状和尺寸也可自动调整。以遗传算法作为优化工具,在Xilinx XCV2000-E 现场可编程门阵列上对滤波器结构和参数进行在线优化。对典型噪声的在线滤波结果表明,该滤波器能够根据噪声的不同自适应调整结构和参数,因而鲁棒性好,适用范围广,滤波性能比均值滤波器和中值滤波器更好,且该滤波器是采用硬件实时实现的,便于在嵌入式系统中应用。