多制式音频解码系统中IMDCT算法优化与硬件实现

逆改良型离散余弦变换(IMDCT)是高质量音频解码器的基本处理单元,其运算中大量的乘法是实现高效IMDCT的一个瓶颈.通过优化IMDCT的算法,实现了一个高效的IMDCT硬件加速器,具有很好的可配置功能,可支持12点,36点及2的幂次点数的IMDCT.通过蝶形拆分运算加快了解码速度,同时通过一个乘法器的复用,大大地降低了解码器的面积.     

高清电视音频解码算法研究与实现

针对DVB的高清电视音频解码中的子带综合滤波算法进行了改进,使得运算量和存储量都下降了一半以上,采用改进算法的解码器在完成C语言仿真的基础上,进行了浮点程序的定点化改造,以实现基于定点DSP的实时解码,此解码器对高清电视信源解码等众多方面有着广泛的应用.     

一种新的MPEG音频解码方案及算法优化

设计了一种新的MPEG音频解码框架.输入音频数据不需经过串行化,通过桶型移位器组织数据读取,提高了解码效率.解码器针对硬件处理特性设计了专用比特流输入单元和解组处理单元.对运算瓶颈子带滤波器设计了优化算法,使运算量降低为标准算法的1/4左右,存储空间降低为原来的1/2.该方案可用于DVB和DAB信源解码芯片中.     

MPEG-4和MPEG-2标准的比较（下）

视频和音频编码完成后，需要通过传送部分把数据送给解码器。MPEG-2和MPEG-4在数据传送方面有些相似性：     

MPEG-2视频解码及硬件实现

本文简明介绍了MPEG-2的系统结构及系统流的解码，着重分析了视频解码器的功能原理及其实现方案，并就视频解码芯片CL9100的功能作一些介绍。     

变换域音频数字水印研究

为了更好地对数字媒体产品进行版权保护,尤其是发展迅速的音频信息,文章主要研究了音频数字水印分类,变频域音频数字水印技术中离散余弦变换算法,离散小波变换算法的特点和实现过程,音频水印的评价指标及常见攻击方式。     

MPEG-2视频DCT量化模块FPGA高速实现

提出了一种全硬件实现高速MPEG-2视频DCT量化模块的新方法,并研究了DCT量化算法及其基于FPGA的实现方法.仿真、验证与测试结果均表明,通过使用FPGA实现DCT量化模块,可以有效地简化软硬件设计的复杂程度,并以全硬件的实现方式大幅提高DCT量化模块的处理速度,其实现成果对于解决广播电视系统对译码芯片的需求有一定价值.     

MPEG-4视频解码器一致性测试

一个特定的profile&level的解码器需要通过MPEG-4标准第四部分中定义的测试过程才能被认为是一个一致性的解码器。对这个测试过程作了较为详细的介绍,给出了MPEG-4Advancedsimpleprofile1ASP@level5的解码器的测试方法和测试过程。     

应用于SoC的低功耗MPEG-1／2音频解码IP

文章设计了一个低功耗、可复用、MPEG-1／2 LayI／Ⅱ／Ⅲ音频解码IP核。该IP核主要应用于包含一个CPU的嵌入式多媒体处理系统。该IP核包含了一个Software-Core和一个Hardware-Core,在两者的配合下,可以在非常低的时钟频率下高精度解码MPEG-1／2 LayI／Ⅱ／Ⅲ音频码流。在实时解码128kbps／44．1kHz MPEG-1／2LayerⅡ码流时,Hardware-Core工作在5．6448MHz,Software-Core工作在8MHz。文章最后给出另一个该IP在典型SoC系统中的应用。Hardware-Core在CMOS0.18μm工艺下,芯片面积为1520μm×1280μm。     

MPEG-2到H.264下采样转码快速算法

提出了一种从MPEG-2中的DCT系数到H.264中的HT系数转换并同时进行下采样的算法.提出的方法可同时进行DCT-HT系数转换和下采样两个过程,并根据变换矩阵的稀疏性和初始MPEG-2系数矩阵的特征,引入了快速算法,可减少大约82%甚者99%的运算量,而对于图像质量几乎没有降低.     

一种基于DWT-DCT-SVD的鲁棒性音频水印算法

针对在基于DWT-DCT进行数字音频水印嵌入,在已嵌入水印的音频受到噪声干扰、低通滤波、重采样等常见的攻击时,其鲁棒性差以及安全性弱的情况.提出了一种新的的盲水印嵌入算法.该算法对原始音频信号完成分帧预处理后,对每帧信号应用离散小波变换(DWT),选取三级低频分量进行离散余弦变换(DCT),先把得到的一维信号平均分解为...     

一种低功耗2D DCT/IDCT处理器设计

设计了一种低功耗的2D DCT/IDCT处理器。为了降低功耗,设计基于行列分解的结构,采用了Loeffler的DCT/IDCT快速算法,并使用了零输入旁路、门控时钟、截断处理等技术,在满足设计需求的基础上降低了系统的功耗。常系数乘法器是该处理器的一个重要部件,文中基于并行乘法器结构设计了一种新型的低功耗常系数乘法器,它采用了CSD编码、Wallace Tree乘法算法,结合采用了截断处理、变数校正的优化技术,使得2D DCT/IDCT处理器整体性能有较大提高。设计的时钟频率为100 MHz,可以满足MPEG2 MP@HL实时解码的应用。采用SMIC0.18μm工艺进行综合,该2D DCT/IDCT处理器的面积为341 212μm2,功耗为14.971 mW。通过与其他结构的2DDCT/IDCT处理器设计分析与比较,在满足MPEG2 MP@HL实时解码应用的同时,实现了较低的功耗。     

High Throughput Parallel-Pipeline 2-D DCT/IDCT Processor Chip

This paper presents a 2-D DCT/IDCT processor chip for high data rate image processing and video coding. It uses a fully pipelined row–column decomposition method based on two 1-D DCT processors and a transpose buffer based on D-type flip-flops with a double serial input/output data-flow. The proposed architecture allows the main processing elements and arithmetic units to operate in parallel at half the frequency of the data input rate. The main characteristics are: high throughput, parallel processing, reduced internal storage, and maximum efficiency in computational elements. The processor has been implemented using standard cell design methodology in 0.35 μm CMOS technology. It measures 6.25 mm² (the core is 3 mm²) and contains a total of 11.7 k gates. The maximum frequency is 300 MHz with a latency of 172 cycles for 2-D DCT and 178 cycles for 2-D IDCT. The computing time of a block is close to 580 ns. It has been designed to meets the demands of IEEE Std. 1,180–1,990 used in different video codecs. The good performance in the computing speed and hardware cost indicate that this processor is suitable for HDTV applications. This work was supported by the Spanish Ministry of Science and Technology (TIC2000-1289).

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基于改进DA算法的2—D IDCT系统设计

离散余弦变换已成为图像压缩中一标准技术,本文给出了基于DA算法的二维离散余弦逆变换（2－DIDCT）系统的设计。在设计过程中根据实际情况提出了一种改进算法,通过采用此改进DA算法,整个2－DIDCT系统在提高速度的同时可大大减少面积。设计采用自顶向下设计方法,用VHDL进行描述,整个系统在SYMOPSYS工具上进行设计及仿真,最终综合到门级电路。     

An Efficient IDCT Processor Design for HDTV Applications

This paper proposes a high performance and low cost inverse discrete cosine transform (IDCT) processor for high definition Television (HDTV) applications by using cyclic convolution and hardwired multipliers. By properly arranging the input sequence, we formulate the one-dimensional (1-D) IDCT into cyclic convolution that is regular and suitable for VLSI implementation. The hardwired multiplier that implements multiplication with IDCT coefficients are first scaled and optimized by using the common sub-expression techniques. Based on these techniques, the data-path in the proposed two-dimensional (2-D) IDCT design costs 7504 gates plus 1024 bits of memory with 100 M pixels/sec throughput according to the cost estimation based on the cell library of COMPASS 0.6 m SPDM CMOS technology. Also, we have verified that the precision analysis of the proposed 2-D 8 × 8 IDCT meets the demands of IEEE Std. 1180-1990. Due to the good performance in the computing speed as well as the hardware cost, the proposed design is compact and suitable for HDTV applications. This design methodology can be applied to forward DCT as well as other transforms like discrete sine transform (DST), discrete Fourier transform (DFT), and discrete Hartley transform (DHT).     

DTS音频文件软件解码的实现

介绍了DTS音频文件的解码标准，给出了软件解码需要的开发环境和解码流程，对3个DTS音频文件的软件解码结果进行了分析，最后列举了在编写DTS音频文件解码软件过程中需要注意的一些问题。     

基于FPGA的AVS反变换的设计与实现

根据AVS音视频编码标准中提出的反变换算法设计了一个基于FPGA的高效的反变换实现框架和方案.提出了一种新颖的一维反变换方法,不仅可以大大节约硬件资源,而且速度非常快.该反变换实现方案经过仿真验证,可以被用于1 920×1 080高清图像的AVS解码芯片中.     

A survey of efficient MDCT implementations in MP3 audio coding standard: Retrospective and state-of-the-art

This tutorial paper describes various efficient implementations (published and new unpublished) of the forward and backward modified discrete cosine transform (MDCT) in the MPEG layer III (MP3) audio coding standard developed in the time period 1990-2010, including the efficient implementation of polyphase filter banks for completeness. The efficient MDCT implementations are discussed in the context of (fast) complete analysis/synthesis MDCT filter banks in the MP3 encoder and decoder. In general, for each efficient forward/backward MDCT block transforms implementation are presented: complete formulas or sparse matrix factorizations of the algorithm, the corresponding signal flow graph for the short audio block and the total arithmetic complexity as well as the useful comments related to improving the arithmetic complexity and a possible structural simplification of the algorithm. Finally, all efficient forward/backward MDCT implementations are compared both in terms of the arithmetic complexity and structural simplicity. It is important to note that almost all presented algorithms can be also used for the 2ⁿ-length data blocks in others MPEG audio coding standards and proprietary audio compression algorithms.     

New fast computational structures for an efficient implementation of the forward/backward MDCT in MP3 audio coding standard

New fast computational structures identical for an efficient implementation of both the forward and backward modified discrete cosine transform (MDCT) in MPEG-1/2 Layer III (MP3) audio coding standard are described. They are based on a new proposed universal fast rotation-based MDCT computational structure [V. Britanak, New universal rotation-based fast computational structures for an efficient implementation of the DCT-IV/DST-IV and analysis/synthesis MDCT/MDST filter banks, Signal Processing 89 (11) (November 2009) 2213–2232]. New fast computational structures are derived in the form of a linear code and they are particularly suitable for high-performance programmable DSP processors. For the short audio block it is shown that our efficient MDCT implementation in MP3 can be modified to achieve the same minimal multiplicative complexity compared to that of Dai and Wagh [An MDCT hardware accelerator for MP3 audio, in: Proceedings of the IEEE Symposium on Application Specific Processors (SASP’2008), Anaheim, CA, June 2008, pp. 121–125].     

Generalized fast mixed-radix algorithm for the computation of forward and inverse MDCTs

This paper presents a generalized mixed-radix decimation-in-time (DIT) fast algorithm for computing the modified discrete cosine transform (MDCT) of the composite lengths N=2×q^m, m≥2, where q is an odd positive integer. The proposed algorithm not only has the merits of parallelism and numerical stability, but also needs less multiplications than that of type-IV discrete cosine transform (DCT-IV) and type-II discrete cosine transform (DCT-II) based MDCT algorithms due to the optimized efficient length-(N/q) modules. The computation of MDCT for composite lengths N=q^m×2ⁿ, m≥2, n≥2, can then be realized by combining the proposed algorithm with fast radix-2 MDCT algorithm developed for N=2ⁿ. The combined algorithm can be used for the computation of length-12/36 MDCT used in MPEG-1/-2 layer III audio coding as well as the recently established wideband speech and audio coding standards such as G.729.1, where length-640 MDCT is used. The realization of the inverse MDCT (IMDCT) can be obtained by transposing the signal flow graph of the MDCT.