Buck quasi-resonant converter operating at constant frequency:analysis, design, and experimentation

A buck pulsewidth modulated zero-current switching quasi-resonant converter (buck PWM ZCS QRC) operating at constant frequency is discussed. Operating principle and design-oriented analysis are presented with normalized design curves, design procedure, design example, simulations, and experimental results. The new topology, which can be considered as a particular one, is compared with the well-established buck frequency-modulated zero-current switching quasi-resonant converter (buck FM ZCS QRC) proposed by Fred C. Lee (1988)     

A quadratic buck converter with lossless commutation

High switching frequency associated with soft commutation techniques is a new trend in switching converters. Following this trend, the authors present a buck pulsewidth modulation converter, where the DC voltage conversion ratio has a quadratic dependence on duty cycle, providing a large step-down. By introducing two resonant networks, soft switching is attained, providing highly efficient operating conditions for a wide load range at high switching frequency. Contrary to most of the converters that apply soft-switching techniques, the switches presented are not subjected to high switch voltage or current stresses and, consequently, present low conduction losses. The authors present, for this converter, the principle of operation, theoretical analysis, relevant equations and simulation and experimental results     

Interpreting small signal behavior of the synchronous buck converter at light load

The pulse-width-modulation (PWM) buck converter with synchronous rectifiers operating at light load is usually modeled by its continuous conduction mode (CCM) model. However, the actual power-stage small-signal control-to-output response shows a different behavior from what the traditional CCM model predicts, specifically, more damping around the double-pole frequency, instead of more resonance. This paper presents a modified small-signal light-load model for a synchronous buck converter. The developed model accurately predicts the actual small-signal behavior of a PWM converter at light load. The derived averaged switch model for light load can also be used for the small-signal models of the other basic PWM converters operating in CCM at light load.     

An improved sampled-data current-mode-control model which explainsthe effects of control delay

A new sampled-data model for the current-mode controlled buck converter includes for the first time the effects of delay in the pulse-width-modulator (PWM). Modified z-transforms are used in this new model for constant frequency trailing-edge modulation. Realistic amounts of delay are found to be particularly significant when the buck converter is operating in the continuous conduction mode near the discontinuous conduction mode boundary. The new model is used to predict the loop gain measurements obtained with the “digital modulator” and with conventional measurement techniques. It is shown that conventional loop gain measurement techniques are insufficient to measure the loop gain in this region of operation. It is also shown that the digital modulator can add a significant amount of delay, thereby altering the loop gain of the circuit being measured. Unlike the case of a continuous system, PWM delay is found to significantly alter the low-frequency loop gain magnitude of this sampled-data system. The new model predicts the boundary condition for sub-harmonic instability, and reduces to Ridley's current-mode control model for the case of zero delay. Experimental corroboration is presented     

A monolithic buck DC–DC converter with on-chip PWM circuit

A monolithic CMOS voltage-mode, buck DC–DC converter with integrated power switches and new on-chip pulse-width modulation (PWM) technique of switching control is presented in this paper. The PWM scheme is constructed by a CMOS ring oscillator, which duty is compensated by a pseudo hyperbola curve current generator to achieve almost constant frequency operation. The minimum operating voltage of this voltage-mode buck DC–DC converter is 1.2 V. The proposed buck DC–DC converter with a chip area of 0.82 mm² is fabricated with a standard 0.35-μm CMOS process. The experimental results show that the converter is well regulated over an output range from 0.3 to 1.2 V, with an input voltage of 1.5 V. The maximum efficiency of the converter is 88%, and its efficiency is kept above 80% over an output power ranging from 30 to 300 mW.     

An ultra-low power CMOS DC–DC buck converter with double-chain digital PWM technique

In present-day integrated digital circuits are become attractive choice for the DC–DC buck converters. This paper proposes a novel approach of CMOS DC–DC buck converter with double-chain digital pulse width modulation (PWM) for ultra-low power applications. The proposed digital PWM architecture consists of double delay lines which is to reduce power consumption and improves ripple voltage with the resolution. An algorithm is proposed that describes the operation of digital PWM. The double chain digital PWM is implemented and analyzed in cadence platform using commercial 180 nm TSMC design kit. The promising results reveals that the power consumption is reduces up to 1.16 µW with occupies less area under the operating frequency of 100 kHz. The DC–DC buck converter with proposed PWM achieves peak efficiency of 92.6% including a load current range of 4–10 mA. This proposed digital PWM method demonstrates its ability to minimize the ripple voltage by 49% and enables to DC–DC converter for compose in a compact chip area as compared to conventional converters. Measured and Simulated power efficiency are made good agreement with each other.     

A continuously variable hydraulic pressure converter based on high-speed on–off valves

A continuously variable hydraulic pressure converter utilizing high-speed on–off valves is studied in this paper. The hydraulic pressure converter is analogous to a switchmode buck converter in power electronics. Substituting the electronic components in the buck converter with their hydraulic counterparts, a hydraulic pressure converter is built. The steady state and fluctuation characteristics of the hydraulic pressure converter are studied in both the theoretical analysis and the simulation. The hydraulic pressure converter was built and tested. Experimental results show that the system output pressure can be continuously adjusted by changing the duty ratio of the PWM signal supplied to the high-speed on–off valve. Although there is fluctuation on the output pressure, the system output pressure has a quasi-linear relationship with the PWM signal duty ratio. Results also show that the output pressure fluctuation is greatly influenced by the PWM signal frequency and the flywheel inertia. The hydraulic pressure converter based on high-speed on–off valves brings a new way to transform system pressure continuously.     

Family of Soft-Switching PWM Converters With Current Sharing in Switches

In this paper, a new family of soft-switching pulsewidth modulation (PWM) converters is introduced. In this family of converters, two switches operate out of phase and share the output current while providing soft-switching condition for each other. A buck converter, from this family of converters, is analyzed and its operating modes are discussed. The adoption of regular PWM control circuit to the proposed converters is presented. A prototype converter is implemented and its experimental results are illustrated.     

A high-power high-frequency ZCS-ZVS-PWM buck converter using afeedback resonant circuit

This paper presents a buck DC-to-DC power converter using a novel lossless commutation cell for high switching frequency and high power operation. The proposed cell consists of a main and auxiliary switches, with ZVS and ZCS switching characteristics, respectively. The power converter control using this cell is realized by the PWM technique, with constant switching frequency operation. The complete operation principles, theoretical analysis, relevant equations, state-space phase, simulation and experimental results for the buck converter are presented     

Novel topologies for DC-DC converter with PWM control

Two topologies for the buck converter are presented. The first converter consists of two active switches whereas the second converter, derived from the parent twoswitch converter, consists of only one active switch. The main feature of this new converter is the ability to operate at a constant switching frequency using a simple PWM control. The design of the gate circuit is simplified as there is only one switch. The converter has a good efficiency, as is proved by the experimental results. The operation of the parent two-switch converter, from which the new single-switch converter is derived, is also presented to gain insight into the design of the new converter.     

An improved ZCT-PWM DC-DC converter for high-power and frequency applications

In this paper, an improved active resonant snubber cell that overcomes most of the drawbacks of the normal zero-current transition (ZCT) pulsewidth-modulation (PWM) dc-dc converter is proposed. This snubber cell is especially suitable for an insulated gate bipolar transistor (IGBT) PWM converter at high power and frequency levels. The converter with the proposed snubber cell can operate successfully with soft switching under light-load conditions and at considerably high frequencies. The operation principles, a detailed steady-state analysis, and a snubber design procedure of a ZCT-PWM buck converter implemented with the proposed snubber cell are presented. Theoretical analysis is verified with a prototype of a 5-kW and 50-kHz IGBT-PWM buck converter. Additionally, at 90% output power, the overall efficiency of the proposed soft switching converter increases to about 98% from the value of 91% in the hard-switching case.     

Single-phase Z-source PWM AC-AC converters

The letter proposes a new family of simple topologies of single-phase PWM ac-ac converters with a minimal number of switches: voltage-fed Z-source converter and current-fed Z-source converter. By PWM duty-ratio control, they become "solid-state transformers" with a continuously variable turns ratio. All the proposed ac-ac converters in this paper employ only two switches. Compared to the existing PWM ac-ac converter circuits, they have unique features: providing a larger range of output ac voltage with buck-boost, reversing or maintaining phase angle, reducing in-rush and harmonic current, and improving reliability. The operating principle and control method of the proposed topologies are presented. Analysis, simulation, and experimental results are given using the voltage-fed Z-source ac-ac converter as an example. The analysis can be easily extended to other converters of the proposed family. The proposed converters could be used in voltage regulation, power regulation, and so on.     

Buck型变换器的线性化小信号补偿前馈控制

为减小由输入电源扰动引起的输出电压工频纹波,改善DC/DC变换器动态性能,根据平均变量建模思想,为电压型PWM控制的Buck型变换器建立连续导电工作模式（CCM）下统一的平均变量等效电路。分析等效电路并根据前馈控制的不变性原理提出Buck型变换器针对输入电压扰动的线性化小信号补偿前馈控制原理及实现方法,采用该方法的Buck型变换器可快速补偿输入电压扰动,加快变换器在输入电压扰动时的动态调节过程,显著减小输出电压中包括工频在内的低频纹波,改善变换器的动态性能。仿真研究结果验证了文中线性化小信号补偿前馈控制原理、方法及其分析的正确性。     

Modeling PWM DC/DC converters out of basic converter units

An alternative approach to modeling pulsewidth-modulated (PWM) DC/DC converters out of basic converter units (BCUs) is presented in this paper. Typical PWM DC/DC converters include the well-known buck, boost, buck-boost, Cuk, Zeta, and Sepic. With proper reconfiguration, these converters can be represented in terms of either buck or boost converter and linear devices, thus, the buck and boost converters are named BCUs. The PWM converters are, consequently, categorized into buck and boost families. With this categorization, the small-signal models of these converters are readily derived in terms of h parameter (for buck family) and g parameter (for boost family). Using the proposed approach, not only can one find a general configuration for converters in a family, but one can yield the same small-signal models as those derived from the direct state-space averaging method. Additionally, modeling of quasi-resonant converters and multiresonant converters can be simplified when adopting the proposed approach     

A high-efficiency,low-noise power solution for a dual-channel GNSS RF receiver

A high-efficiency low-noise power solution for a dual-channel GNSS RF receiver is presented.The power solution involves a DC-DC buck converter and a followed low-dropout regulator(LDO).The pulsewidth -modulation(PWM) control method is adopted for better noise performance.An improved low-power highfrequency PWM control circuit is proposed,which halves the average quiescent current of the buck converter to 80μA by periodically shutting down the OTA.The size of the output stage has also been optimized to achieve high efficiency under a light load condition.In addition,a novel soft-start circuit based on a current limiter has been implemented to avoid inrush current.Fabricated with commercial 180-nm CMOS technology,the DC-DC converter achieves a peak efficiency of 93.1%under a 2 MHz working frequency.The whole receiver consumes only 20.2 mA from a 3.3 V power supply and has a noise figure of 2.5 dB.     

Spectral characteristics of randomly switched PWM DC/DC convertersoperating in discontinuous conduction mode

This paper addresses a comparative study of the spectral characteristics of four random-switching schemes that apply to the basic pulsewidth-modulation (PWM) DC/DC converters operating in discontinuous conduction mode (DCM). They include randomized pulse position modulation, randomized pulsewidth modulation, and randomized carrier frequency modulation with fixed duty cycle and with fixed duty time, respectively. Mathematical models that characterize the input current and output voltage of the three basic PWM converters operating in DCM are derived. In particular, the effectiveness of spreading the dominant switching harmonics in the input current that normally exist in the standard PWM scheme and the introduction of low-frequency harmonics in the output voltage with respect to the randomness level are investigated. The validity of the models and analyses are confirmed experimentally by using a DC/DC buck converter     

峰值电流模式控制的非理想Buck变换器的建模

在 Ridley 峰值电流模式控制的 Buck 变换器模型的基础上,提出一个包含传导损耗的修正模型.运用平均开关建模法,建立非理想PWM开关的非线性大信号平均模型.包含全部寄生电阻和二极管的正向压降.围绕某一稳态工作点,扰动并线性化平均模型,导出非理想Buck变换器的功率级在连续工作模式下的直流模型和线性小信号模型.在此基础上.修正峰值电流模式控制部分的小信号模型参数.最终建立整个峰值电流模式控制的非理想Buck变换器的线性小信号模型.推导小信号动态的解析结果.给出修正的补偿斜坡信号斜率.在Simetrix/simplis开关电源软件包中进行了仿真分析,结果显示新模型能更准确地预测系统性能.     

Wireless PWM control of a parallel DC-DC buck converter

We demonstrate a new concept for wireless pulse-width modulation (PWM) control of a parallel dc-dc buck converter. It eliminates the need for multiple physical connections of gating/PWM signals among the distributed converter modules. The new scheme relies on radio-frequency (RF) based communication of the PWM control signals from a master to the slave modules. We analyze the system stability and demonstrate the experimental effectiveness of the wireless control scheme for a two-module parallel buck converter for 10-kHz and 20-kHz switching frequencies and for channel lengths of 1.5 and 15ft, respectively. The proposed control concept may lead to easier distributed control implementation of parallel dc-dc converters and distributed power systems, and may lead to redundancy that is achievable using droop method. It may also be used as a backup for wire-based control of parallel converters to provide fault tolerance.     

一种基于自适应峰值电流检测的模式切换电路北大核心

在降压转换器中，为了在不同的负载情况下获得高效率，常采用的方法是在重载时使用脉冲宽度调制(PWM),在轻载时使用脉冲频率调制(PFM),因此需要模式切换信号去控制整个降压转换器的工作状态，同时模式切换信号也可以用于自适应改变功率级电路中的功率管栅宽，减小功率管的栅极电容，提高整体电路的效率。文章设计了一个自适应峰值电流模式切换电路，用于产生模式切换信号，其原理是监控峰值电流的变化，产生峰值电压，将峰值电压与参考电压进行比较，得到模式切换信号，以决定降压转换器是采用PFM模式还是PWM模式。仿真结果表明，在负载电流0.5～500 mA范围内，该电路可以在两种调制模式之间平稳切换，其峰值效率可提升到94%以上。     

Current-fed three-phase and voltage-fed three-phase activeconverters with optimum PWM pattern scheme and their performanceevaluations

This paper describes a new approach to select the optimum sinewave pulsewidth modulation (PWM) patterns suitable for a large-capacity current-fed active PWM power converter and a practical design procedure to determine circuit constants of a low-pass filter connected to suppress higher line current harmonics flowing into the utility-grid AC power source. A feasible test is implemented by building a prototype 500 kW three-phase current-fed PWM power converter which is designed and controlled on the basis of the proposed considerations. It is verified from a practical point of view that these new conceptual considerations are more effective and acceptable to minimize higher harmonic current components flowing into the utility-grid AC power source. This experimental setup provides highly efficient steady-state characteristics of the current-fed three-phase PWM power converter under the operating condition of a unity power factor correction and sinewave line current shaping schemes. Furthermore, this unique optimum PWM pattern derived from the theoretical method proposed here is conveniently applicable to a voltage-fed three-phase PWM converter. It is verified that this optimum PWM pattern provides excellent switching performance with a lower switching frequency mode than the conventional carrier-based PWM scheme