一种全速率线性25Gb/s时钟数据恢复电路

面向高速光通信系统的应用,提出了一种全速率线性25Gb/s时钟数据恢复电路(Clock and Data Recovery Circuit,CDRC)。CDRC采用了混频器型线性鉴相器和自动锁频技术来实现全速率时钟提取和数据恢复。在设计中没有使用外部参考时钟。基于45nm CMOS工艺,该CDR电路从版图后仿真结果得到:恢复25Gb/s数据眼图的差分电压峰峰值V_pp和抖动峰峰值分别为1.3V和2.93ps;输出25GHz时钟的差分电压峰峰值V_pp和抖动峰峰值分别为1V和2.51ps,相位噪声为-93.6dBc/Hz@1MHz。该芯片面积为1.18×1.07mm²,在1V的电源电压下功耗为51.36mW。     

面向电荷泵的占空比可调四相时钟发生电路北大核心

针对传统四相时钟发生电路产生的时钟波形信号易发生交叠、驱动电荷泵易发生漏电等问题，提出了一种占空比可调四相时钟发生电路。电路在每两相可能出现交叠的时钟信号之间都增加了延时单元模块，通过控制延时时间对输出时钟信号的占空比进行调节，避免了时钟相位的交叠。对延时单元进行了改进，在外接偏置电压条件下，实现了延时可控。基于55 nm CMOS工艺的仿真结果表明，在10～50 MHz时钟输入频率范围内，该四相时钟发生电路可以稳定输出四相不交叠时钟信号，并能在1.2 V电压下驱动十级电荷泵高效泵入11.2 V。流片测试结果表明，该四相时钟发生电路能够产生不相交叠的四相时钟波形，时钟输出相位满足电荷泵驱动需求。     

适用于10/100Base-T以太网的低抖动频率综合器

设计了一种用于10/100Base-T以太网收发器的频率综合器电路.该电路自适应工作在10和100Mbps两种模式下,并能自由切换.电路采用cascode电流源、差分对称负载延迟单元等优化结构,使时钟输出具有良好特性,且能兼具DLL功能,同时满足发送电路上升下降斜率控制和时钟恢复电路对于多相时钟的需要,避免额外的功耗和面积.在一定测试环境下,晶振的cycle-cycle抖动σ约为25ps,输出时钟分频后的25MHz测试时钟信号的σ仅为22ps.测试结果表明,时钟发生电路具有良好的工艺稳定性和较强的抑制噪声能力,满足发送和接收电路对于时钟性能的要求.芯片采用SMIC 0.35μm的标准CMOS工艺,电源电压为3.3V.     

基于0.18μm CMOS工艺的低温漂低功耗延时电路

基于0.18μm CMOS工艺设计了一款低温漂延时电路,适用于不能使用锁相环电路又对信号传输精度有要求的低功耗传感检测应用。采用正温度系数的偏置电压,通过电流镜为延时电路提供一个正温度系数的偏置电流,利用偏置电流约束电路的延时温漂,实现温漂粗调。采用数字时间转换器,通过外部输入配置,对粗调后的延时进行动态细调,使得延时电路具有更高的动态稳定性和更低的温漂特性。电路测试结果表明,在3.3 V的电源电压下,-55～125℃内延时电路的温度系数为125×10^-6/℃,静态功耗仅为0.72 mW。     

适用于10/100Base-T以太网的低抖动频率综合器

计了一种用于10/100BaseT以太网收发器的频率综合器电路．该电路自适应工作在10和100Mbps两种模式下,并能自由切换．电路采用cascode电流源、差分对称负载延迟单元等优化结构,使时钟输出具有良好特性,且能兼具DLL功能,同时满足发送电路上升下降斜率控制和时钟恢复电路对于多相时钟的需要,避免额外的功耗和面积．在一定测试环境下,晶振的cycle-cycle抖动σ约为25ps,输出时钟分频后的25MHz测试时钟信号的σ仅为22ps．测试结果表明,时钟发生电路具有良好的工艺稳定性和较强的抑制噪声能力,满足发送和接收电路对于时钟性能的要求．芯片采用SMIC 0.35μm的标准CMOS工艺,电源电压为3.3V．     

应用于高速串行接口的低噪声时钟发生器

设计了一种应用于28 Gbit/s高速串行接口的低噪声时钟发生器,包括全差分电荷泵、差分环路滤波器、差分压控振荡器。为了降低相位噪声,采用全差分结构来降低共模噪声和电流失配。为了进一步降低小数分频器引入的噪声,提出一种基于计数器的分频器。为了保证时钟发生器在各种工艺和温度偏差下均能自动锁定,设计了自适应调谐电容电路。采用65 nm CMOS工艺进行设计,芯片面积为0.36 mm²,整体功耗为36 mW。后仿真结果表明,该时钟发生器在14 GHz 锁定后的相位噪声是-113 dBc@1 MHz,压控振荡器的调谐范围是12.8~15.0 GHz,自动锁定电路能在全调谐范围内对电路进行自动调整和锁定。     

一种适用于相变存储器锁相环时钟的新型电荷泵

设计了一款低噪声、低功耗的电荷泵,适用于相变存储器驱动电路中的锁相环时钟。与其它结构的电荷泵相比较,此款电路对时钟馈通与电荷注入等干扰免疫力强。根据相变存储器对驱动电路低噪声的性能要求,本电路具有低的热噪声和1/f噪声。仿真结果表明输出电压在0℃~80℃温度范围内最大仅有11mV的偏差,其与PFD所产生的相位噪声在1MHz频率下为-102dB。电路采用40nm CMOS工艺设计,电源电压2.5V,功耗0.125mW,芯片面积60 m×55 m。     

一种高速低噪声时钟扇出器的设计

面向多通道超高速数据采集设备对高性能分配器的需求,提出了一种低抖动、低延迟、高稳定性的射频时钟扇出器结构。两组输入时钟端口可供选择,内部采用无运放结构的带隙基准电路,提供精确偏置电压,最高支持10路LVPECL电平输出。端口采用优化的斜边叉指型二极管ESD保护结构,提升电路的ESD保护性能。该时钟扇出器电路基于180nm SiGe工艺设计流片。经测试,3.3V电源电压条件下,最高工作频率5GHz;在122.08MHz载频下,测得附加相位噪声为-128.09dBc/Hz@10Hz、-160.75dBc/Hz@1MHz,从10kHz到20MHz积分,附加抖动为21fs RMS;常温25℃下测得,最大输出通道间偏斜为30ps,传输延迟80ps;ESD保护电压为4500V。     

一种基于65 nm CMOS工艺的3抽头前馈均衡器

高速串行接口技术是当前高速数据传输的关键技术之一,而前馈均衡器(FFE)是高速串行接口中的重要模块电路。设计了一款工作在40 Gb/s、用于高速串口发送端的前馈均衡器;分析了FFE求和模块、延时模块对均衡效果的影响;采用LC网络作为延时单元,并通过设计闭环反馈控制来控制延时时间,解决了高速均衡电路的延时实现问题。电路采用TSMC 65 nm CMOS工艺进行设计和仿真,后仿真结果表明,在40 Gb/s数据传输时,该3抽头FFE电路具有20 dB的均衡能力;在TT_27 ℃工艺角、1.0 V电源电压下,电路功耗为51.52 mW。     

一种基于注入锁定环形振荡器的时钟产生电路

提出了一种基于谐波注入锁定数控环形振荡器的时钟产生电路。采用注入锁定技术,极大地抑制了环形振荡器的相位噪声。在频率调谐环路关断的情况下,数控式振荡器可以正常工作,与需要一直工作的锁相环相比,大大节省了功耗。分析了电路的参考杂散性能。在65 nm CMOS工艺下进行流片测试,芯片的面积约为0.2 mm²。测试结果表明,设计的时钟产生电路工作在600 MHz时,1 MHz频偏处的相位噪声为-132 dBc/Hz,在1 V的电源电压下仅消耗了5 mA的电流。     

Low‐Power Direct Conversion Transceiver for 915 MHz Band IEEE 802.15.4b Standard Based on 0.18 μm CMOS Technology

This paper presents the experimental results of a low‐power low‐cost RF transceiver for the 915 MHz band IEEE 802.15.4b standard. Low power and low cost are achieved by optimizing the transceiver architecture and circuit design techniques. The proposed transceiver shares the analog baseband section for both receive and transmit modes to reduce the silicon area. The RF transceiver consumes 11.2 mA in receive mode and 22.5 mA in transmit mode under a supply voltage of 1.8 V, in which 5 mA of quadrature voltage controlled oscillator is included. The proposed transceiver is implemented in a 0.18 μm CMOS process and occupies 10 mm² of silicon area.     

一种适用于内嵌时钟串行链路的5Gbps小面积CDR

本文提出了一种支持多标准的具有系数可调的均衡器和宽跟踪能力的时钟数据恢复电路。基于对系统参数和一阶 bang-bang 时钟数据恢复电路的环路特性分析,推导出电路设计参数。考虑到抖动性能,追踪能力以及芯片面积,文中采用了一阶数字滤波器和6-bit DAC以及高线性度的相位插值器实现了高相位调整精度和小面积的时钟恢复电路,同时该结构实现了±2200ppm的频偏跟踪能力,使得该结构适用于不同源的高速串行传输系统,尤其是内嵌时钟结构。该设计已经在55nm CMOS工艺上流片验证,测试结果显示符合误码率的要求以及抖动容忍规范。该测试芯片整体面积是0.19mm2,其中时钟恢复电路只占0.0486mm2 而且该电路工作在5Gbps,供电电压为1.2V时,只消耗30mW。     

A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS

This paper describes a 6.25-Gb/s 14-mW transceiver in 90-nm CMOS for chip-to-chip applications. The transceiver employs a number of features for reducing power consumption, including a shared LC-PLL clock multiplier, an inductor-loaded resonant clock distribution network, a low- and programmable-swing voltage-mode transmitter, software-controlled clock and data recovery (CDR) and adaptive equalization within the receiver, and a novel PLL-based phase rotator for the CDR. The design can operate with channel attenuation of -15 dB or greater at a bit-error rate of 10^-15 or less, while consuming less than 2.25 mW/Gb/s per transceiver.     

A 6 Gbps/pin Low‐Power Half‐Duplex Active Cross‐Coupled LVDS Transceiver with Switched Termination

A novel linear switched termination active cross‐coupled low‐voltage differential signaling (LVDS) transceiver operating at 1.5 GHz clock frequency is presented. On the transmitter side, an active cross‐coupled linear output driver and a switched termination scheme are applied to achieve high speed with low current. On the receiver side, a shared preamplifier scheme is employed to reduce power consumption. The proposed LVDS transceiver implemented in an 80 nm CMOS process is successfully demonstrated to provide a data rate of 6 Gbps/pin, an output data window of 147 ps peak‐to‐peak, and a data swing of 196 mV. The power consumption is measured to be 4.2 mW/pin at 1.2 V.     

Fabrication and performance analysis of a high-coupling- efficiency and convenient-integration optical transceiver

An optical transceiver with a novel optical subassembly structure is proposed in this paper, which achieves high coupling efficiency and low assembly difficulty. The proposed optical transceiver consumes 0.9 W power and retains a small size of 28 mm×16 mm×3 mm. The fabrication process of the silicon substrate and the assembly process of the optical transceiver are demonstrated in details. Moreover, the optical transceiver is measured in order to verify its transmission performance. The clear eye diagrams and the low bit error rate (BER) less than 10-13 at 10 Gbit/s per channel show good transmission characteristics of the designed optical transceiver.     

A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link

A 1 Tb/s 3 W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1 GHz and data rate of 1 Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30 mum in a layout area of 1 mm². The total layout area including 16 clock transceivers is 2 mm² in 0.18 mum CMOS and the chip thickness is reduced to 10 mum. Bi-phase modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. Four-phase time division multiple access (TDMA) reduces crosstalk and the bit-error rate (BER) is lower than 10^-13     

110-GB/s simultaneous bidirectional transceiver logic synchronizedwith a system clock

A simultaneous bidirectional transceiver logic (SBTL), for a 0.25 μm CMOS embedded array, has a low-voltage-swing input flip-flop circuit and an output flip-flop with a boundary scan to enable a 1.1-Gb/s data transfer per LSI pin with a 550-MHz system clock. Clock skew and jitter minimization enables high bandwidth in a phase-locked system. Measured latency time for transmission is less than 3.0 ns during simultaneous switching mode when the cable length is 18 cm. Average power consumption is 12 mW per pin at 550 MHz. A low-noise output buffer and a controlled collapse chip connection (C4)-based 1595-pin package with on-package capacitors achieve 100-byte data bus. The maximum data bandwidth per LSI is 110 GB/s     

Highly birefringent photonic crystal fibers with flattened dispersion and low confinement loss

A highly birefringent index-guiding photonic crystal fiber (PCF) with flattened dispersion and low confinement loss is proposed by introducing two small air holes with the same diameter in the core area. The fundamental mode field, birefringence, confinement loss, effective mode area and dispersion characteristic of the fibers are studied by the full-vector finite element method (FEM). Simulation results show that a high birefringence with the order of 10 -3 and a low confinement loss of 0.001 dB/km are obtained at 1550 nm. Furthermore, flattened chromatic dispersion from 1450 nm to 1590 nm is obtained.     

High rate UWB CMOS transceiver chipset for WBAN and biomedical applications

This work presents a high rate UWB transceiver chipset implemented in a 130 nm CMOS technology for WBAN and biomedical applications in the 3–5 GHz band. The transmitter architecture is based on a double-filter excitation technique that can generate high magnitude pulses and address bipolar modulations such as BPSK. Measurements show that bipolar pulses with a peak-to-peak voltage of 1.9 Vpp for a power consumption of 139 µW@100 kbps can be generated. The receiver is a non-coherent architecture based on LNA followed by an envelope detector. A BER of 10^?3 is achieved for a 3–5 GHz input peak-to-peak amplitude of 3.4 mVpp which corresponds to a ?89.3 dBm sensitivity at 100 kbps. The energy consumption of the receiver and of the transmitter is respectively 0.144 nJ/bit and 196 pJ/bit at 100 Mbps. To improve the budget link of our non-coherent based transceiver a Randomly Alternate OOK signaling is proposed which leads to an estimated communication range of 2.36 m in a free space propagation channel.