CCGA packages for space applications

Commercial-off-the-shelf (COTS) area array packaging technologies in high reliability versions are now being considered for applications, including use in a number of NASA electronic systems being utilized for both the Space Shuttle and Mars Rover missions. Indeed, recently a ceramic package version specifically tailored for high reliability applications was used to provide the processing power required for the Spirit and Opportunity Mars Rovers built by NASA-JPL. Both Rovers successfully completed their 3-months mission requirements and continued exploring the Martian surface for many more moths, providing amazing new information on previous environmental conditions of Mars and strong evidence that water exists on Mars.Understanding process, reliability, and quality assurance (QA) indicators for reliability are important for low risk insertion of these newly available packages in high reliability applications. In a previous investigation, thermal cycle test results for a non-functional daisy-chained peripheral ceramic column grid array (CCGA) and its plastic ball grid array (PBGA) version, both having 560 I/Os, were gathered and are presented here. Test results included environmental data for three different thermal cycle regimes (−55/125 °C, −55/100 °C, and −50/75 °C). Detailed information on these—especially failure type for assemblies with high and low solder volumes—are presented. The thermal cycle test procedure followed those recommended by IPC-9701 for tin–lead solder joint assemblies. Its revision A covers guideline thermal cycle requirements for Pb-free solder joints. Key points on this specification are also discussed.In a recent investigation a fully populated CCGA with 717 I/Os was considered for assembly reliability evaluation. The functional package is a field-programmable gate array that has much higher processing power than its previous version. This new package is smaller in dimension, has no interposer, and has a thinner column wrapped with copper for reliability improvement. This paper will also present thermal cycle test results for assemblies of this and its plastic package version with 728 I/Os, both of which were exposed to four different cycle regimes. Two of these cycle profiles are specified by IPC-9701A for tin–lead, namely, −55 to 100 °C and −55 to 125 °C. One is a cycle profile specified by Mil-Std-883, namely, −65/150 °C, generally used for ceramic hybrid packages screening and qualification. The last cycle is in the range of −120 to 85 °C, a representative of electronic systems directly exposed to the Martian environment without use in a thermal control enclosure. Per IPC-9701A, test vehicles were built using daisy chain packages and were continuously monitored and/or manually checked for opens at intervals. The effects of many process and assembly variables—including corner staking commonly used for improving resistance to mechanical loading such as drop and vibration loads—were also considered as part of the test matrix. Optical photomicrographs were taken at various thermal cycle intervals to document damage progress and behavior. Representative samples of these are presented along with cross-sectional photomicrographs at higher magnification taken by scanning electron microscopy (SEM) to determine crack propagation and failure analyses for packages.     

Board level reliability assessment of chip scale packages

A large program had been initiated to study the board level reliability of various types of chip scale package (CSP). The results on six different packages are reported here, which cover flex interposer CSP, rigid interposer CSP, wafer level assembly CSP, and lead frame CSP. The packages were assembled on FR4 PCBs of two different thicknesses. Temperature cycling tests from −40°C to +125°C with 15 min dwell time at the extremes were conducted to failure for all the package types. The failure criteria were established based on the pattern of electrical resistance change. The cycles to failure were analyzed using Weibull distribution function for each type of package. Selected packages were tested in the temperature/humidity chamber under 85°C/85%RH for 1000 h. Some assembled packages were tested in vibration condition as well. In all these tests, the electrical resistance of each package under testing was monitored continuously. Test samples were also cross-sectioned and analyzed under a Scanning Electronic Microscope (SEM). Different failure mechanisms were identified for various packages. It was noted that some packages failed at the solder joints while others failed inside the package, which was packaging design and process related.     

Reliability of 80 μm pitch flip chip attachment on flex

The interest toward flip chip technology has increased rapidly during last decade. Compared to the traditional packages and assembly technologies flip chip has several benefits, like less parasitics, the small package size and the weight. These properties emphasize especially when flip chip component is mounted direct to the flexible printed board. In this paper flip chip components with Kelvin four point probe and daisy chain test structure were bonded to the polyimide flex with two different types of anisotropically conductive adhesive films and one anisotropically conductive adhesive paste. The reliability of small pitch flip chip on flex interconnections (pitch 80 μm) was tested in 85°C/85% RH environmental test and −40↔+125°C thermal shock test. According to the results it is possible to achieve reliable and stable ohmic contact, even in small pitch flip chip on flex applications.     

Temperature profile effects in accelerated thermal cycling of SnPb and Pb-free solder joints

Accelerated thermal cycling (ATC) has been widely used in the microelectronics industry for reliability assessment. ATC testing decreases life cycle test time by one or more of the following means: increasing the heating and cooling rate, decreasing the hold time, or increasing the range of the applied temperature. The relative effect of each of these cycle parameters and the failure mechanisms they induce has been the subject of many studies; however uncertainty remains, particularly regarding the role of the heating and cooling rate. In this research, three conditions with two ramp rates (14 °C/min and 95 °C/min) and two temperature ranges (ΔT = 0–100 °C and −40 to 125 °C) were applied to resistor 2512 and PBGA 256 test vehicles assembled with SnPb and Pb-free solders. The test results showed that the higher ramp rate reduced the testing time while retaining the same failure modes, and that the damage per cycle increased with the temperature difference. For the resistors, the Pb-free solder joints lasted longer than the SnPb joints at the smaller ΔT, but were inferior at the larger ΔT. In contrast, the Pb-free solder joints in the PBGA test vehicles lasted longer than the SnPb solder under both conditions.     

Low temperature delamination of plastic encapsulated microcircuits

Plastic encapsulated microcircuits (PEMs) are increasingly being used in applications requiring operation at temperatures lower than the manufacturer’s recommended minimum temperature, which is 0°C for commercial grade components and −40°C for industrial and automotive grade components. To characterize the susceptibility of PEMs to delamination at these extreme low temperatures, packages with different geometries, encapsulated in both biphenyl and novolac molding compounds, were subjected to up to 500 thermal cycles with minimum temperatures in the range −40 to −65°C in both the moisture saturated and baked conditions. Scanning acoustic microscopy revealed there was a negligible increase in delamination at the die-to-encapsulant interface after thermal cycling for the 84 lead PQFPs encapsulated in novolac and for both 84 lead PQFPs and 14 lead PDIPs encapsulated in biphenyl molding compound. Only the 14 lead novolac PDIPs exhibited increased delamination. Moisture exposure had a significant effect on the creation of additional delamination.     

Qualification approaches and thermal cycle test results for CSP/BGA/FCBGA

Qualification of newly developed multifunctional electronic packages, e.g. system in a package (SIP), are becoming complex at the package level and even more at the assembly and system levels. After many years of data collection, just recently industry agreed to release an industry-wide specification for single die area array package assembly qualification.Probability risk assessment, being implemented by NASA for space flight missions, may be narrowed at the element level for advanced electronic systems and SIP, and further narrowed at the electronic subsystem level. This paper will review the key elements of an industry-wide specification recently published by the IPC (association connecting electronics industries). It will report on a few other unique qualification approaches that are currently being either implemented or developed for risk reduction in high reliability applications. Risk level assessment based 2-P, 3-P, and LogNormal distributions will be compared for plastic ball grid array (PBGA) and flip chip BGA (FCBGA). For this case, risks are compared using cycles-to-failures (CTFs) test results for temperature ranges of −30 to 100 °C and 0 to 100 °C (two profiles).In addition, CTFs up to 1,500 cycles in the range of −55 to 125 °C for a 784 I/O FCBGA (flip chip BGA, a 175 I/O FPBGA (fine pitch BGA)), and a 313 I/O PBGA (plastic BGA) are compared. Inspection results along with scanning electron microscopy and optical cross-sectional photos revealing damage and failure mechanisms are also included.     

Solder joint fatigue life of fine pitch BGAs – impact of design and material choices

The impact of design and material choices on solder joint fatigue life for fine pitch BGA packages is characterized. Package variables included die size, package size, ball count, pitch, mold compound, and substrate material. Test board variables included thickness, pad configuration, and pad size. Three thermal cycle conditions were used.Fatigue life increased by up to 6× as die size was reduced. For a given die size, fatigue life was up to 2× longer for larger packages with more solder balls. Mold compounds with higher filler content reduced fatigue life by up to 2× due to a higher stiffness and lower thermal expansion coefficient. Upilex S tape with punched holes gave 1.15× life improvement over Kapton E tape with etched holes. Once optimized, tape-based packages have equal board level reliability to laminate-based packages.Solder joint fatigue life was 1.2× longer for 0.9 mm thick test boards compared to 1.6 mm thick boards due to a lower assembly stiffness. The optimum PCB pad design depends on failure location. For CSP applications, NSMD test board pads give up to 3.1× life improvement over SMD pads. For a completely fan-out design, there was a 1.6× acceleration factor between −40125°C, 15 min ramps, 15 min dwells and 0100°C, 10 min ramps, 5 min dwells.     

Reliability of wire-bonding and solder joint for high temperature operation of power semiconductor device

Thick Al wires bonded on chips of power semiconductor devices were examined for thermal cycle tests, then the bonded joints were cut using microtome method, after that those were observed by scanning electron microscope and analyzed by electron back scattered diffraction. Some cracks were observed between Al wires and the chips, unexpectedly the crack lengths were almost constant for −40/150 °C, −40/200 °C and −40/250 °C tests. It is considered that re-crystallization has been progressed during the high temperature side of the thermal cycle tests.Furthermore, joint samples were prepared using high temperature solders such as Zn–Al and Bi with CuAlMn, Direct Bonded Copper insulated substrates and Mo heatsinks. The fabricated samples were evaluated by scanning acoustic microscope before and after thermal cycle tests. Consequently, almost neither serious damages nor delaminations were observed for −40/200 °C and −40/250 °C tests.     

Effect of different temperature cycling profiles on the crack initiation and propagation of Sn–3.5Ag wave soldered solder joints

Temperature cycling of a test board with different electronic components was carried out at two different temperature profiles in a single-chamber climate cabinet. The first temperature profile ranged between −55 and 100 °C and the second between 0 and 100 °C. Hole mounted components and secondary side SMD components were wave soldered with an Sn–3.5Ag alloy. Joints of both dual in line (DIL) packages and ceramic chip capacitors were investigated. Crack initiation and propagation was analysed after every 500 cycles. In total, 6500 cycles were run at both temperature profiles and the observations from each profile were compared.For both kinds of components analysed, cracks were first visible for the temperature profile ranging between −55 and 100 °C. For this temperature profile, and for DIL packages, cracks were visible already after 500 cycles, whereas for the other temperature profile, cracks initiated between 1000 and 1500 cycles. The cracks observed after 1500 cycles were visibly smaller for the temperature profile ranging between 0 and 100 °C, concluding that crack initiation and propagation was slightly slower for this temperature profile. For the chip capacitors, cracks were first visible after 2000 cycles.     

Growth of tin whiskers for lead-free plated leadframe packages in high humid environments and during thermal cycling

Growth behavior of tin whiskers from pure tin and tin–bismuth plated leadframe (LF) packages for elevated temperature and high humidity storages and during thermal cycling was observed. In the storage at 60 °C/93% relative humidity (RH) and 85 °C/85%RH the galvanic corrosion occurred at the outer lead toes and shoulders where the base LF material is exposed, forming tin oxide layers of SnO₂. The corroded layers spread inside the film and formed whiskers around the corroded islands. Many whiskers were observed to grow from grain boundaries for the Fe–42Ni alloy (alloy42) LF packages. It was confirmed that the corrosion tends to occur on the side surfaces of outer leads adjacent to the mold flash. The contribution of ionic contaminants in epoxy mold compound (EMC) to the corrosion was not identified. During thermal cycling between −65 °C and +150 °C whiskers grew out of as-deposited grains for pure tin-plated alloy42 LF packages and they grew linearly with an increase of number of cycle. Growth mechanisms of the whiskers from grain boundaries and as-deposited grains were discussed from the deformation mechanism map for tin and mathematical calculation with a steady-state diffusion model.     

Fatigue analysis of miniaturized lead-free solder contacts based on a novel test concept

The paper presents the method of generating lifetime-prediction-laws on special prepared very stiff specimen. The combination of thin- and thick-film technology allows building up test samples on ceramic very similar to electronic packages including the measurement issues. Influences of pad surface metallurgy, microstructure of solder, ineutectic solder alloys and assembly process parameter are regarded now. The investigation objects provide monitoring of electrical and mechanical damage process of SnAgCu solder bump. Different thermo-mechanical loads will be applied in temperature ranges of 0 to +80 °C, −40 to +125 °C and −50 to +150 °C, where the temperature gradient and cycle frequency also vary. A Variation of four different chip sizes allows the determination of fatigue laws for each temperature profile, to be able to compare in between them. The results of these tests will give universal lifetime-prediction laws for SnAgCu base solder joints. Main goals are to find coefficients for lifetime prediction models such as Coffin–Manson- or Norris–Landzberg-relation, which are transferable in between different electronic packages.     

Growth of tin whiskers for lead-free plated leadframe packages in high humid environments and during thermal cycling

Growth behavior of tin whiskers from pure tin and tin-bismuth plated leadframe (LF) packages for elevated temperature and high humidity storages and during thermal cycling was observed. In the storage at 60 °C/93% relative humidity (RH) and 85 °C/85%RH the galvanic corrosion occurred at the outer lead toes and shoulders where the base LF material is exposed, forming tin oxide layers of SnO₂. The corroded layers spread inside the film and formed whiskers around the corroded islands. Many whiskers were observed to grow from grain boundaries for the Fe–42Ni alloy (alloy42) LF packages. It was confirmed that the corrosion tends to occur on the side surfaces of outer leads adjacent to the mold flash. The contribution of ionic contaminants in epoxy mold compound (EMC) to the corrosion was not identified. During thermal cycling between −65 °C and +150 °C whiskers grew out of as-deposited grains for pure tin plated alloy42 LF packages and they grew linearly with an increase of number of cycle. Growth mechanisms of the whiskers from grain boundaries and as-deposited grains were discussed from the deformation mechanism map for tin and mathematical calculation with a steady-state diffusion model.     

Anisotropic conductive film flip chip joining using thin chips

In this study, flip chip interconnections were made on very flexible polyethylene naphthalate substrates using anisotropic conductive film. Two kinds of chips were used: chips of normal thickness and thin chips. The thin chips were very thin, only 50 μm thick. Due to the thinness of the chips they were flexible and the entire joint was bendable. The reliability properties of the interconnections established with these two different kinds of chips were compared. In addition, the effect of bending of the chip and joint area on the joint reliability was studied. Furthermore, part of the substrates was dried before bonding and the effect of that on the joint performance was investigated.The pitch of the test vehicles was 250 μm and the chips had 25 μm high gold bumps. For resistance analysis there were two four-point measuring positions in each test vehicle. For finding the optimal bonding conditions for the test vehicles, the bonding was done using two different bonding pressures, of which the better one was chosen for the final tests.Furthermore, the test vehicles were subjected to thermal cycling tests between −40 and +125 °C (half-an-hour cycle) and to a humidity test (85%/85 °C). Part of the test vehicles were bent during the tests. Finally, the structures of the joints were studied using scanning electron microscopy.     

Solder joint reliability evaluation of chip scale package using a modified Coffin–Manson equation

Thermal cycle tests were performed for chip scale package (CSP) solder joints with Sn–37mass%Pb under several thermal cycle conditions. Under the conventional thermal cycle conditions, which heat up to approximately 100 °C, microstructure coarsening occurred and solder joints were fractured. The thermal fatigue lives followed the modified Coffin–Manson equation. The exponential factors m and n, and the activation energy Q in that equation were evaluated as 0.33, −1.9 and 15.5 kJ/mol, respectively. When the maximum temperature is room temperature and the temperature range is very narrow, the solder joint fracture occurred without microstructure coarsening, and the thermal fatigue life does not follow the modified Coffin–Manson equation.     

High-temperature reliability of Flip Chip assemblies

Flip Chip technology has been widely accepted within microelectronics as a technology for maximum miniaturization. Typical applications today are mobile products such as cellular phones or GPS devices. For both widening Flip Chip technology’s application range and for addressing the automotive electronics’ volume market, developing assemblies capable of withstanding high temperatures is crucial. A typical scenario for integrating electronics into a car is a control unit within the engine compartment, where ambient temperatures are around 150 °C, package junction temperatures may range from 175 °C to 200 °C and peak temperatures may exceed these values.If Flip Chip technology is used under harsh environment conditions, it is clear that especially the polymeric materials, i.e., underfiller, solder mask or the organic substrate base material, are challenged. Generally, the developmental goal for encapsulants compatible with high-temperature applications are materials with high T_g and low degradation even at temperatures >200 °C.According to these demands, a test group of advanced underfill encapsulants has been used for assembling Flip Chip devices. These test vehicles were built using lead-free and lead-containing solders such as SnAgCu and eutectic PbSn and standard FR4 substrates, for evaluating the reliability potential of state-of-the-art underfillers. Material analysis is performed for studying both material degradation as well as temperature-dependent thermo-mechanical and adhesive properties. For assessing reliability, temperature cycling is performed with different maximum test temperatures ranging from 150 °C to 175 °C. The device status is intermediately analyzed by using electrical measurement for detecting bond integrity and acoustomicroscopy for determining the occurrence and growth of delaminations. Extensive failure analysis is added to investigate device failure mechanisms, especially related to the respective test temperature.In summary, an empirical status of the high-temperature potential of state-of-the-art underfillers and material combinations is attained and an outlook on future demands and developments is provided.     

A simple model for the mode I popcorn effect for IC packages

A simple model for the Mode I popcorn effect is presented here for packages with rectangular die pad (P-DSO). A package “stability parameter”, relating to its moisture sensitivity, is derived from the popcorn model. It describes the critical factors for a robust package - molding compound properties and package, leadframe design for a given preconditioning and soldering process. Furthermore, nomograms generated from the model enable an easy estimation of moisture sensitivity levels (between 1 and 5) of packages with different die pad sizes and molding compound underpad thicknesses and for different soldering temperatures ranging from 220°C to 260°C (Pb-free soldering).     

Lead-free 0201 manufacturing, assembly and reliability test results

The trend towards smaller, faster and cheaper electronic devices has led to an increase in the use of 0201 (L  0.02 in.; W  0.01 in.) and even smaller sized passive components. The size advantages of the 0201 component make it a popular choice among design engineers but not among manufacturing engineers. From a manufacturing perspective, the size of the 0201 package poses significant challenges to the printed circuit board (PCB) assembly process. The many challenges with 0201 assembly can be attributed to the solder paste volume, pad design, aperture design, board finish, type of solder paste, pick-and-place and reflow profile. If these factors are not optimized, they will introduce undesirable manufacturing defects. The small size of 0201 packages and undetected manufacturing defects will also raise concerns about their second level interconnect reliability, especially for lead-free solder alloys and surface finishes, with new processes and higher reflow requirements. To determine the optimum conditions, a design-of-experiment (DOE) study was carried out to investigate the effects of these parameters on assembly defects and solder joint reliability.This paper presents the test results and comparative literature data on the influence of a few key manufacturing parameters and defects associated with the 0201 component using lead-free and tin–lead solder alloys. Data pertaining to component shear strength before and after isothermal aging at 150 °C and intermetallic growth up to 500 h of aging are presented. A number of test vehicles were also subjected to thermal cycling (1500 cycles) in the range of −55/100 °C to determine the solder fatigue behavior. Shear test results for test vehicles subjected to thermal cycling is also presented. In addition, optical microscopy analysis of solder joint behavior during thermal cycling showing the progress of the solder damage and cross-sectional photos taken at 1500 cycles is included.     

Development of the green plastic encapsulation for high density wirebonded leaded packages

The push in the electronics industry toward miniaturization and high density wirebonds is a major driving force in integrated circuit (IC) package design. One problem has been the use of conventional mold compounds to encapsulate the high density wirebonded packages, due to performance issues, such as wire sweep and coplanarity. Additionally, in order to match lead-free solutions in the near future, antimony- and halogen-free molding compound must be developed because antimony (Sb) and halogens in current flame retardant systems pose environmental hazardous. This article, discusses a “green” compound that eliminated these environmentally hazardous elements, resolving moldability and reliability issues for high density wirebonded packages.The reliability assessment was conducted at the maximum reflow peak temperature of 240 °C after moisture soaking at 60 °C/60%RH for 40 h, followed by temperature cycle tests. The study aimed for good package integrity, process, and performance to meet the requirements of high volume production and an acceptable moisture sensitivity (level 3) with a reflow temperature of 240 °C. The study indicates that moldability and reliability involved separate issues and offers a solution for high volume production and field application.     

Reliability and RF performance of BGA solder joints with plastic-core solder balls in LTCC/PWB assemblies

In this paper board-level reliability of low-temperature co-fired ceramic (LTCC) modules with thermo-mechanically enhanced ball-grid-array (BGA) solder joint structure mounted on a printed wiring board (PWB) was experimentally investigated by thermal cycling tests in the 0–100 °C and −40 to 125 °C temperature ranges. The enhanced joint structure comprised solder mask defined (SMD) AgPt pad metallization, eutectic solder and plastic-core solder balls (PCSB). Similar daisy-chained LTCC modules with non-collapsible 90Pb10Sn solder spheres were used for a reference test set. The reliability of the joint structures was analyzed by resistance measurements, X-ray microscopy, scanning acoustic microscopy (SAM) and SEM/EDS investigation. In addition, a full-wave electromagnetic analysis was performed to study effects of the plastic-core material on the RF performance of the LTCC/BGA package transition up to millimeter-wave frequencies. Thermal cycling results of the modules with PCSBs demonstrated excellent fatigue performance over that of the reference. In the harsher cycling test, Weibull’s shape factor β values of 7.9 and 4.8, and characteristic lifetime θ values of 1378 and 783 were attained for the modules with PCSBs and 90Pb10Sn solder spheres, respectively. The primary failure mode in all test assemblies was fatigue cracking in eutectic solder on the ceramic side.     

Wire-bond failure mechanisms in plastic encapsulated microcircuits and ceramic hybrids at high temperatures

Ceramic hybrids are the preferred solution when long-term high-temperature reliability is required, but standard plastic encapsulated microcircuits (PEMs) are an interesting alternative due to low price and high availability. Test vehicles with standard PEMs were subjected to thermal ageing at 150–175 °C. Six of eight vehicles failed after only three weeks at 175 °C, and the cause of failure was found to be microcracking at the interface between gold ball and aluminium bond pad giving rise to resistance increase. The intermetallic region was formed during high-temperature lead soldering and continued to develop during thermal ageing. The high-temperature performance of aluminium wire bonding to a selection of thick film metallizations on ceramic substrate was also investigated. Gold–palladium has previously been reported as a high-temperature solution, but we found that the mechanical strength of aluminium to gold–palladium (AuPd) degraded seriously at temperatures above 200 °C due to intermetallic formation. Aluminium to silver thick film plated with copper and nickel showed good mechanical strength and unaltered electrical resistance after four weeks thermal ageing at 250 °C.