A low-power PLA for a signal processor

A standard fast programmable logic array (PLA) structure is discussed, with emphasis on its power consumption drawbacks. An exploration of alternatives to this structure leads to a presentation of the architecture and design of a low-power PLA structure used in a digital signal processing (DSP) environment. This PLA achieves low power consumption by a combination of pipelining, use of a NAND-OR configuration, and a simplified addressing scheme. Experimental results for the temperature range of 0 to 70°C indicate that the circuit works as expected in a range extending to at least 3.5 V     

A low-voltage low-power instrumentation amplifier based on supply current sensing technique

In this paper a new low-voltage low-power instrumentation amplifier (IA) is presented. The proposed IA is based on supply current sensing technique where Op-Amps in traditional IA based on this technique are replaced with voltage buffers (VBs). This modification results in a very simplified circuit, robust performance against mismatches and high frequency performance. To reduce the required supply voltage, a low-voltage resistor-based current mirror is used to transfer the input current to the load. The input and output signals are of voltage kind and the proposed IA shows ideal infinite input impedance and a very low output one. PSPICE simulation results, using 0.18 μm TSMC CMOS technology and supply voltage of ±0.9 V, show a 71 dB CMRR and a 85 MHz constant −3 dB bandwidth for differential-mode gain (ranging from 0 dB to 18 dB). The output impedance of the proposed circuit is 1.7 Ω and its power consumption is 770 µW. The method introduced in this paper can also be applied to traditional circuits based on Op-Amp supply current sensing technique.     

怎样选择嵌入式媒体处理器

选择一片多媒体应用处理器是一项复杂的工作.为了做出最好的选择,需要先做好以下准备. ●全面地分析每个候选处理器的内核结构以及外围设备. ●扎实地理解视频和音频数据如何流过系统. ●评估在规定功耗条件下可达到的处理水平.     

多处理器DSP:为媒体处理器带来一股清风

DSP的流媒体领域是个新涌现的热门,包括三大类:带宽/连接应用,语音/数据/图像/视频应用,WAN上的多媒体(MOW,Multimedia Over WAN),这块市场的增长速度高达22%,2007年预计可达到360亿美元.     

A low-power direct digital synthesizer using a self-adjustingphase-interpolation technique

A complete direct digital synthesizer (DDS) using a self-adjusting phase-interpolation technique is fabricated using 0.35-μm CMOS process technology. A self-adjusting delay generator reduces the periodic jitter in the most significant bit (MSB) of the accumulator in this DDS. To improve the spectral performance, a method of spurious signal reduction that uses offset current sources (OCSs) is newly adopted in the delay generator. Test results confirm that the delay generator produces highly accurate delay timing without the need to adjust circuit constants. The measured spurious free dynamic range (SFDR) is 62 dBc for a dc to 10-MHz output and the power consumption of the complete DDS is 39.2 mW at a 100-MHz clock rate     

用2.5D TSV实现多处理器SiP功能

本项目由Open-Silicon,GLOBALFOUNDRI ES和Amkor三家公司合作完成。两颗28nm的ARM处理器芯片,通过2.5D硅转接板实现集成。芯片的高性能集成通常由晶体管制程提高来实现,应用2.5D技术的Si P正成为传统芯片系统集成的有效替代。Open-Silicon负责芯片和硅转接板的设计,重点在于性能优化和成本降低。GLOBALFOUNDRI ES采用28nm超低能耗芯片工艺制造处理器芯片,而用65nm技术制造2.5D硅转接板。包括功耗优化和功能界面有效管理等概念得到验证。硅基板的高密度布线提供大量平行I/O,以实现高性能存储,并保持较低功耗。所开发的EDA设计参考流程可以用于优化2.5D设计。本文展示了如何将大颗芯片重新设计成较小的几颗芯片,通过2.5D硅转接板实现Si P系统集成,以降低成本,提高良率,增加设计灵活性和重复使用性,并减少开发风险。     

A 2/spl times/ load/store pipe for a low-power 1-GHz embedded processor

The load/store pipe for a low-power 1-GHz embedded processor is described. For area savings and logic complexity reduction, the load/store pipe is clocked at twice the frequency of the processor core. It can sustain two load or store operations per core clock cycle with zero load to use issue latency. The address generation unit for one of the two load/store pipes takes advantage of the common addressing mode in MIPS 64 ISA to generate the address within a core clock phase. Phase borrowing is employed in the translation lookaside buffer (TLB) design to enable a lookup process within a core clock phase. The data cache design enables the activation of a minimum number of data bank arrays for power savings. Small-swing differential buses are used for multiple address and data buses for improved signal transmission latency. The quadrature clocks used to derive the 2/spl times/ clock are generated with a novel 4-to-1 divider and distributed with matched paths, all to reduce the duty cycle variation of the 2/spl times/ clock phase. The design has been implemented in a 0.13-/spl mu/m CMOS process.     

Nonlinear theory of a free-electron laser exploiting media with aperiodically modulated refractive index

The nonlinear theory of a free-electron laser (FEL) exploiting media with a periodically modulated refractive index is presented. The gain and the saturation parameters are found for different operating regimes of such a FEL. The system discussed could be used for the amplification of light in the optical and ultraviolet regions of the spectrum     

Wide-tuning-range,low-phase-noise quadrature ring oscillator exploiting a novel noise canceling technique

This paper presents a novel noise-canceling technique, which is used to improve the phase noise of a two-stage quadrature ring oscillator. The thermal noise canceling circuitry is used to cancel the channel thermal noise of the output transistors in each stage of the oscillator. Simulations using TSMC 0.13 μm CMOS technology show a wide frequency tuning range of 315 MHz to 6.64 GHz and ?97.5 dBc/Hz at 1 MHz offset from 4.7 GHz for changing supply from 0.5 V to 1.6 V. The power consumption is obtained to be 14.8 mW. The proposed oscillator can be used in applications such as ultra-wideband systems, and multiband and multimode receivers.     

锁相技术在高频开关电源中的应用

本文介绍了锁相技术在电流控制两态调制技术的高频开关电源中的应用。开关电源整个控制环路相当于一个锁相环,这个环路不仅有锁相作用,而且还有调压作用。实验表明,这种高频开关电源有优良的性能。     

Inverse scattering technique applied to remote sensing of layered media

An inverse scattering technique applied to a remote estimation of the dielectric and conductivity profile of an inaccessible layered medium is presented. The inaccessible region is illuminated by plane waves at normal incident, and the data are taken as the reflected power at a fixed remote location for a set of discrete frequencies. The problem of estimating the dielectric and conductivity profile from this set of data is posed as a nonlinear integral equation. This formulation based on reflected power is appealing for practical purpose, in that the phase information of the reflected field is not required. The equation is solved by developing a quasi-Newton iterative scheme in functional space which produces a dielectric and conductivity profile that fits the data. The Backus and Gilbert resolving-power theory is used to assess the reliability of the estimates and the resolving length of the data. Results are given for the numerical reconstruction of various dielectric and conductivity profiles from an artificial data set, together with local averages estimates and resolving kernels.     

A generalized processor sharing approach to flow control inintegrated services networks: the multiple node case

Worst-case bounds on delay and backlog are derived for leaky bucket constrained sessions in arbitrary topology networks of generalized processor sharing (GPS) servers. The inherent flexibility of the service discipline is exploited to analyze broad classes of networks. When only a subset of the sessions are leaky bucket constrained, we give succinct per-session bounds that are independent of the behavior of the other sessions and also of the network topology. However, these bounds are only shown to hold for each session that is guaranteed a backlog clearing rate that exceeds the token arrival rate of its leaky bucket. A much broader class of networks, called consistent relative session treatment (CRST) networks is analyzed for the case in which all of the sessions are leaky bucket constrained. First, an algorithm is presented that characterizes the internal traffic in terms of average rate and burstiness, and it is shown that all CRST networks are stable. Next, a method is presented that yields bounds on session delay and backlog given this internal traffic characterization. The links of a route are treated collectively, yielding tighter bounds than those that result from adding the worst-case delays (backlogs) at each of the links in the route. The bounds on delay and backlog for each session are efficiently computed from a universal service curve, and it is shown that these bounds are achieved by “staggered” greedy regimes when an independent sessions relaxation holds. Propagation delay is also incorporated into the model. Finally, the analysis of arbitrary topology GPS networks is related to Packet GPS networks (PGPS). The PGPS scheme was first proposed by Demers, Shenker and Keshav (1991) under the name of weighted fair queueing. For small packet sizes, the behavior of the two schemes is seen to be virtually identical, and the effectiveness of PGPS in guaranteeing worst-case session delay is demonstrated under certain assignments     

The bang-bang hysteresis current waveshaping control technique used to implement a high power factor power supply

This work reports the operation and development of a high power factor power supply that operates at high switching frequency. An optimum power factor correction is obtained using an ac-dc boost converter associated to a nondissipative snubber as a pre-regulator circuit, which presents reduced commutation losses. The same nondissipative snubber is associated to a Forward converter and then used as a dc-dc stage. The proposed switched mode power supply presents high power factor (0.998), high efficiency (91%), low harmonic content (current and voltage total harmonic distortion rates equal to 2.84% and 2.83%, respectively), and also satisfactory regulation. The converter has been theoretically analyzed, designed, simulated and implemented, where experimental results show that soft commutation in all switches is achieved.     

运用可配置处理器内核的设计

虽然专用集成电路(ASIC)设计者不希望从零开始开发整个系统的每一个部分,但是他们必须确信整个系统和每个部分都按专用特性工作,即使第三方供应商可能提供系统的部件.目前,嵌入式系统是由几组工程师去设计的,因而出现硬件和软件分别开发的倾向,导致最终产品的工作特性偏离原来的指标.根据这种情况,使用第三方的知识产权(IP)只会增加多头开发和延长上市时间的可能性.     

RTD fluxgate: a low-power nonlinear device to sense weak magnetic fields

Fluxgate magnetometers have always been of interest to technical and scientific communities to sense weak magnetic fields (in the range of 10/sup -6/) with a resolution of 100 pT at room temperature. These devices find applicability in fields such as space, geophysical exploration and mapping, nondestructive testing, and assorted military applications. This article discusses the quantities affecting the RTD fluxgate performances, considerations on the design of an RTD fluxgate, and presents an magnetometer experimental prototype.     

如何选择和使用电源

安全性、可靠牲和功率因数校正是首先要考虑的问题     

Small-slope iteration technique for wave scattering from a roughinterface of two media

In this paper, the problem of wave scattering from an uneven interface of two homogeneous media is considered. By means of the surface potentials method, the initial problem is reduced to a system of two integral equations. In the case of mildly sloping roughness with small curvature, an analytical solution of the system is derived in the form of a perturbation series. The terms of this series are calculated in quadratures in a recurrent manner. It is shown that the first term corresponds to the tangent plane approximation. In view of the first two terms, the well-known result of the small perturbation method is obtained for the limiting case of small roughness     

Low-power level converting flip-flop with a conditional clock technique in dual supply systems

Clustered voltage scaling (CVS) is an effective way to reduce power consumption in digital integrated circuits. Level-converting flip-flops are the critical elements in the CVS scheme. In this paper a single edge implicit pulse-triggered level-converting flip-flop with a conditional clock technique (CC-LCFF) is proposed and proved to be suitable for use in low-power non-critical paths with Dual-VDD. CC-LCFF conditionally blocks the clock signal when the input data does not make any transition, so the redundant transitions of internal nodes are eliminated and the total power consumption is reduced. Based on the SMIC 65 nm technology, the post-layout simulation results show that the proposed CC-LCFF shows an improvement of 69.41–72.40% in power consumption and 23.36–47.73% in power-delay product (PDP) as compared with its counterparts.     

A technique to generate feasible tests for communications systems with multiple timers

We present a new model for testing real-time protocols with multiple timers, which captures complex timing dependencies by using simple linear expressions involving timer-related variables. This new modeling technique, combined with the algorithms to eliminate inconsistencies, allows generation of feasible test sequences without compromising their fault coverage. The model is specifically designed for testing to avoid performing full reachability analysis, and to control the growth of the number of test scenarios. Based on extended finite state machines, it is applicable to languages such as SDL, VHDL, and Estelle. The technique models a realistic testing framework in which each I/O exchange takes a certain time to realize and timers can be arbitrarily started or stopped. A software tool implementing this technique is used to generate test cases for the US Army wireless standard MIL-STD 188-220.     

Extended multicasting technique to allow multiple destinations peroutput port in ATM switches

When a multicast cell at an aynchronous transfer mode (ATM) switch requires distribution of its copies to the multiple users and/or outgoing sub-rate links served by one of its output ports, multiple cell copies at that output port are required. The conventional copy approach and broadcast approach of multicasting either cannot handle such situations or handles at the cost of switch performance. In this letter we propose a technique to enhance the ability of the copy and broadcast approaches to multicasting to enable them to handle such situations efficiently and economically