A self-trimming 14-b 100-MS/s CMOS DAC

A 14-b 100-MS/s CMOS digital-analog converter (DAC) designed for high static and dynamic linearity is presented. The DAC is based on a central core of 15 thermometer decoded MSBs, 31 thermometer decoded upper LSBs (ULSBs) and 31 binary decoded lower LSBs (LLSBs). The static linearity corresponding to the 14-b specification is obtained by means of a true background self-trimming circuit which does not use additional current sources to replace the current source being measured during self-trimming. The dynamic linearity of the DAC is enhanced by a special track/attenuate output stage at the DAC output which tracks the DAC current outputs when they have settled but attenuates them for a half-clock cycle after the switching instant. The DAC occupies 3.44 mm×3.44 mm in a 0.35-μm CMOS process, and is functional at up to 200 MS/s, with best dynamic performance obtained at 100 MS/s. At 100 MS/s, power consumption is 180 mW from a 3.3-V power supply, and 210 mW at 200 MS/s     

A cost-effective approach to the design and layout of a 14-b current-steering DAC macrocell

This brief discusses the economical design of a 14-b current-steering digital-to-analog converter (DAC) macrocell for integration with other analog and digital macrocells in a system-on-chip (SOC). The DAC design is targeted for a standard 0.13-/spl mu/m six-metal single-poly CMOS process. A novel algorithm sets the switching order of individual current sources and minimizes systematic mismatch errors. The design approach minimizes total fabrication cost of the SOC without a loss to specified DAC design requirements. Total macrocell design area is 2.9 mm/sup 2/.     

A 100-MHz CMOS DAC for video-graphic systems

A 6-b weighted-current-sink video digital-to-analog converter (DAC) with 10-90% rise/fall time of 4 ns, integrated with a double-metal 3-μm CMOS technology, is described. Current-source matching, glitch reduction, and differential switch driving aspects are considered. A circuit solution and a nonconventional layout technique yield a high conversion rate with a standard CMOS technology. Experimental results show that a conversion rate of 100 MHz is achievable. The power consumption is 150 mW and the active chip area is 0.5×1.0 mm² . The differential of 0.1 LSB demonstrates that 8 b of accuracy can be achieved. The integral linearity is 0.5 LSB     

A 16-b D/A converter with increased spurious free dynamic range

A novel approach to D/A switch design has resulted in improved frequency domain performance for direct digital synthesis for clock rates up to 40 MSPS. Use of the new switch in a BiCMOS 16-b DAC has achieved a spurious free dynamic range of greater than 80 dB     

A design synthesis system for recursive DSP algorithms represented by fully specified flow graphs

This paper describes a design synthesis environment which can generate an efficient VLSI layout from a recursive DSP algorithm specified by a graph. The design synthesis environment is divided into three parts: optimal schedule generation, circuit synthesis, and VLSI layout generation (silicon compilation). The scheduler first computes optimality conditions for a given input algorithm and then finds a schedule which satisfies the optimality conditions. We have employed a cyclo-static optimal multiprocessor compiler as a scheduler. The circuit synthesis component translates the optimal schedule into a structural specification, including the control structures, for an circuit realization. In the final part, a VLSI layout is generated from the structural specification. We have chosen the LAGER system for the silicon compilation. This paper illustrates the design synthesis process with complete details of a simple, complete example, a second order Direct Form II IIR filter.This work was supported in part under the Joint Services Electronics Program Contract # DAAL-03-90-C-0004.     

An Improved Switch Compensation Technique for Inverted R-2R Ladder DACs

Many recent applications are based on DSPs interfaced to analog I/0s with data converters. In this context, high-performance DACs have become crucial building blocks. The current-steering-flash DAC architecture is the most popular architecture for speed demanding applications. Although limited by component mismatches, resolution of these converters is typically enhanced by calibration solutions such as laser trimming or corrective active circuitry. Dynamic performances, on the other hand, are strongly dependent on switch design and operation which can easily spoil even the best static accuracy level at higher speeds. For this reason, much effort is concentrated on the design of clean switching processes to optimize signal to noise ratios delivered at the output of the DAC. In this paper, we present a novel switch sizing and compensation technique for inverted R-2R ladder DACs. While traditional switch compensation in the ladder leads to very large switch devices steering MSBs currents, our method allows current-steering with reduced equally sized switches. Results of 12-b DAC test chips fabricated in a 0.18 $mu{hbox {m}}$ process show that this new technique allows significant area savings, without impairing static accuracy. Other improvements brought by this technique include simplified switch driving circuitry and improved settling time.      

A high-performance CMOS 70-MHz palette/DAC

A VLSI circuit has been developed that combines dual-ported RAMs and three high-speed 8-b digital-to-analog converters (DACs). It is known as a palette/DAC. A 6-2 segmented DAC architecture improves differential linearity and monotonicity. The current-source cell uses a cascode device to improve the DAC's linearity. A reference current, set by an on-chip bandgap reference voltage generator, and its associated distribution scheme eliminate the negative effects of threshold mismatches between current source cells, supply line resistance, and noise. The maximum conversion rate is 70 MHz with typical DC differential nonlinearity of 0.48 LSB (least significant bit). The 253-mil/SUP 2/ is designed on a double-metal CMOS process and consumes 1.2 W of power.     

A low-Voltage 10-bit CMOS DAC in 0.01-mm/sup 2/ die area

A low-voltage 10-bit digital-to-analog converter (DAC) for static/dc operation is fabricated in a standard 0.18-/spl mu/m CMOS process. The DAC is optimized for large integrated circuit systems where possibly dozens of such DAC would be employed for the purpose of digitally controlled analog circuit calibration. The DAC occupies 110 /spl mu/m/spl times/94 /spl mu/m die area. A segmented R-2R architecture is used for the DAC core in order to maximize matching accuracy for a minimal use of die area. A pseudocommon centroid layout is introduced to overcome the layout restrictions of conventional common centroid techniques. A linear current mirror is proposed in order to achieve linear output current with reduced voltage headroom. The measured differential nonlinearity by integral nonlinearity (DNL/INL) is better than 0.7/0.75 LSB and 0.8/2 LSB for 1.8-V and 1.4-V power supplies, respectively. The DAC remains monotonic (|DNL|<1 LSB) as INL reaches 4 LSB down to 1.3-V operation. The DAC consumes 2.2 mA of current at all supply voltage settings.     

Hierarchical symbolic design methodology for large-scale data paths

A symbolic layout methodology for large-scale data paths is proposed. A gate-level symbolic expression, the logic transformation diagram, is adopted as a layout input. A mask layout is automatically generated from the symbolic expression. A hierarchical design method is used in combination with a bit-slice regular structure and a performance-determining irregular structure. A 1-b field of the bit-slice structure is designed symbolically and then compacted, and finally the entire data path is generated. Performance-determining irregular macrocells, such as adders with carry-look-ahead (CLA) circuits, are handcrafted independently and combined with the entire data path at the final step. To achieve high density and high performance, effort is focused on optimizing the layout of the 1-b field. Iteration of the editing and compaction loop can be executed in a short turnaround time (TAT). By the proposed methodology, a data path containing 21 K transistors in a 32-b microprocessor has been successfully produced. Design productivity has been increased tenfold, achieving a layout density equivalent to that of the handcrafted design     

Kink-free SOI analog circuit design with floating-body/NFD MOSFETs

A novel design approach to ensure general kink-free operation of floating-body/nonfully depleted (NFD) SOI analog circuits is described. The approach involves optimization of the bias and aspect ratios of all transistors that determine gain and current in a circuit such that they operate only in their kink-free voltage windows. The approach is demonstrated via a simulation-based design of the current cells of a 10-b floating-body/NFD DAC that shows good linearity and resolution at dc and frequencies up to 1 GHz. In contrast, the floating-body/NFD DAC without proper optimization shows poor and prohibitive performance     

4-bit adder-accumulator at 41-GHz clock frequency in InP DHBT technology

A 41-GHz 4-b adder-accumulator test circuit implemented in InP double heterojunction bipolar transistor (DHBT) technology using 624 transistors is reported. High clock rates are obtained by combining the logic functions into pipelined latches. The adder-accumulator contains a single-level parallel-gated carry circuit that is used as a step toward reduced power consumption. The carry circuit has a maximum clock frequency of 55 GHz. The accumulator architecture employs modular, pipelined 2-b adders and is cascadable to 2 N-bits. The test circuit includes a 4-b digital to analog converter (DAC) that facilitates demonstration of high-speed operation.     

一种带电流源校准的16bit高性能DAC

设计了一种带电流源校准电路的16 bit高速、高分辨率分段电流舵型数模转换器(DAC)。针对电流舵DAC中传统差分开关的缺点,提出了一种优化的四相开关结构。系统分析了输出电流、积分非线性和无杂散动态范围(SFDR)三个重要性能指标对电流舵DAC的电流源单元设计的影响,完成了电流源单元结构和MOS管尺寸的设计。增加了一种优化设计的电流源校准电路以提高DAC的动态性能。基于0.18μm CMOS工艺完成了该DAC的版图设计和工艺加工,其核心部分芯片面积为2.8 mm^2。测试结果表明,在500 MHz采样速率、100 MHz输入信号频率下,测得该DAC的SFDR和三阶互调失真分别约为76和78 dB,动态性能得到明显提升。     

A 12-bit 1-Gword/s GaAs digital-to-analog converter system

The circuitry for a 12-b 1-Gword/s digital-to-analog converter (DAC) IC is described. A DC linearity of /spl plusmn/1/8 LSB has been preserved with this all-depletion GaAs MESFET chip. Dynamic measurements in the frequency domain indicate nonlinearities of less than -62 dBc at a 1-GHz clock rate. The DAC uses a very fast FET analog current switch that exhibits sufficiently low leakage currents for a 12-b linearity. The limited on-chip matching capabilities require the precision DC currents to be generated external to the GaAs chip. A current-switching DAC that partitions the high-speed functions onto a single GaAs chip while the high-precision bit currents are realized off-chip is described. The GaAs chip contains 12 1-b cells, each of which switches an analog bit current into a single sampler circuit that is shared by all the switches. The sampler is used to increase the dynamic linearity in the DAC.     

12bit高稳定性数模转换器设计

设计了一款12 bit高稳定性控制类数模转换器(DAC),该DAC集成了带有稳定启动电路的新型低失调带隙基准源(BGR),改善了基准电路的稳定性以及对温度和工艺的敏感性;DAC采用了改进的两级电阻串结构,通过开关电阻匹配和特殊版图布局,在既不增加电路功耗又不扩大版图面积的前提下,提高了DAC的精度并降低了工艺浓度梯度对整体性能的影响.基于CSMC 0.5 μm 5 V 1P4M工艺对所设计的DAC芯片进行了流片验证.测试结果表明:常温下DAC的微分非线性(DNL)小于0.45 LSB,积分非线性(INL)小于1.5 LSB,并且在-55～125℃内DNL小于1 LSB,INL小于2.5 LSB;5V电源电压供电时功耗仅为3.5 mW,实现了高精度、高稳定性的设计目标.     

基于QN旋转布局的10位500 MS/s分段电流舵DAC

针对分段电流舵数/模转换器（Digital-to-Analog Converter，DAC），通过理论分析和推导，研究电流源阵列系统失配误差和寄生效应对非线性的影响，采用电流源阵列Q^N旋转游走版图布局方案，能够减小电流源系统失配的一次误差，而且版图布线简单，由寄生效应引起的电流源失配较小，利于DAC非线性的优化.基于0.18μm CMOS，采用"6+4"的分段结构，设计了一种10位500MS/s分段电流舵DAC，流片测试结果表明，在输入频率为1.465MHz，采样速率为500MS/s的条件下，无杂散动态范围（Spurious Free Dynamic Range，SFDR）为64.9dB，有效位数（Effective Number of Bits，ENOB）为8.8 bit，微分非线性误差（Differential Non-linearity，DNL）和积分非线性误差（Integral Non-linearity，INL）分别为0.77LSB和1.12LSB.     

A single chip Δ-Σ ADC with a built-in variable gainstage and DAC with a charge integrating subconverter for a 5 V 9600-b/smodem

A 12-b, 19.2-ksamples/s Δ-Σ A/D and D/A converter for a 9600-b/s facsimile modem analog front end is described. In the proposed Δ-Σ ADC, the reference voltage is varied to adjust the signal gain, thus, eliminating the need of a variable gain amplifier. The Δ-Σ DAC uses a 4-b charge integrating subconverter which is insensitive to process variations     

Area-efficient multi-channel active matrix micro-LED driver chip design

This study develops the control and driver for active Micro LED panel with chip-level design. The chip includes constant current circuit, digital-to-analog converter, SPI control interface, and active-matrix display control. The design process uses TSMC0.18um HVG2 CMOS technology, to realize 30 channels for micro LED driver. To reduce I/O pins, the input signals feed to the dynamic shift register in serial, and the results are loaded to the digital-to-analog converter (DAC) in parallel. The DAC module consists of R2R network, unity-gain buffer and sample-and-hold circuits. The DAC outputs with constant current for micro LED driving from voltage-to-current conversion. To reduce the number of DAC component, one DAC can share the common circuit to drive RGB LED of one pixel based on the selected current mirror structure. This chip can greatly reduce resistor and switches about 92% and 96% respectively, compared with the conventional R DAC structure. The measurements result with good linear for the current dimming control, which the test digital signals are generated by Verilog codes to estimate the gray current of this chip.

     

Area-efficient layout design for CMOS output transistors

A novel layout design to effectively reduce the layout area of the thin-oxide NMOS and PMOS devices in CMOS output buffers with ESD consideration is proposed. With respect to the traditional finger-type layout, the large-dimension output NMOS and PMOS devices are realized by multiple octagonal cells. Without using extra ESD-optimization process, the output NMOS and PMOS devices in this octagon-type layout can provide higher driving/sinking current and better ESD robustness within a smaller layout area. The drain-to-bulk parasitic capacitance at the output node is also reduced by this octagon-type layout. Experimental results in a 0.6-μm CMOS process have shown that the output driving (sinking) current of CMOS output buffers in per unit layout area is increased 47.7% (34.3%) by this octagon-type layout. The HBM (MM) ESD robustness of this octagon-type output buffer in per unit layout area is also increased 41.5% (84.6%), as comparing to the traditional finger-type output buffer. This octagon-type layout design makes a substantial contribution to the submicron or deep-submicron CMOS IC's in high-density and high-speed applications     

一种10位电容电阻混合型双极性D/A转换器

在加速度计中,需要数模转换器(DAC)提供一个稳定的偏压来消除重力加速度,要求DAC具有高精度、单调性和小面积等特性。为了解决传统电阻型DAC存在的大面积和传统电容DAC中存在的非单调性等问题,提出了一种电容电阻混合型DAC结构,并设计了一个10位的DAC,用于提供稳定偏压。提出一种新的电容共质心的版图布局,提高了DAC的精度。该DAC在0.5μm CMOS工艺上得以验证实现,微分非线性误差(DNL)最大为0.50LSB,积分非线性误差(INL)最大为0.82LSB,在5V和-5V的双电源供电条件下,芯片功耗为16mW,完全满足了工程需求。