Characterization of the novel polysilicon TFT with a subgatecoupling structure

Proposed and fabricated a novel polysilicon thin film transistor (poly-Si TFT) with a subgate coupling structure that behaves as an offset gated structure in the OFF state while acting as a conventional nonoffset structure in the ON state. The OFF state leakage current of the new TFT is two orders of magnitude lower than that of the conventional nonoffset TFT, while the ON current of the new TFT is one order of magnitude higher than that of the offset TFT and is almost identical to that of the conventional non-offset TFT. The ON/OFF current ratio of the new TFT is greatly improved by two orders of magnitude. No additional photo-masking steps are required to fabricate the subgate of the new TFT and its fabrication process is fully the same as the conventional nonoffset TFTs     

Self-aligned offset gated poly-Si TFTs with a floating sub-gate

We have fabricated a self-aligned offset-gated poly-Si thin film transistor (TFT) by employing a novel photoresist reflow process. The gate structure of the new device is consisted of two unique patterns: A main-gate and a sub-gate. The new fabrication method extends the gate-oxide over the offset region. With the assistance of the sub-gate and reflowed photoresist a self-aligned offset region is successfully obtained due to the offset oxide acting as an implantation mask. The poly-Si TFT with symmetrical offsets is easily fabricated and the new method does not require any additional offset mask step. Compared with the misaligned offset gated poly-Si TFTs, excellent symmetric electrical characteristics are obtained     

A novel polysilicon thin-film transistor with a p-n-p structuredgate electrode

We propose and fabricate a novel polycrystalline silicon thin-film transistor (poly-Si TFT) which exhibits the properties of an offset gated structure in the OFF state, while acting as a nonoffset structure in the ON state. The fabrication process is compatible with the conventional nonoffset poly-Si TFT's process and does not require any additional mask. Experimental results show that the leakage current of the new device is two orders of magnitude lower than that of the nonoffset gated device, while the ON current of the new device is almost identical to the nonoffset gated device. It is observed that the ON/OFF current ratio of the proposed poly-Si TFT is improved remarkably     

Novel offset gated poly-Si TFTs with subgate

We have fabricated a new offset gated poly-Si TFT by employing photoresist reflow, have measured various experimental data of the new device, such as hydrogenation results and high-frequency characteristics, and have analyzed device characteristics as a function of driving frequency. Our devices have a unique gate pattern and the hydrogenation effect is somewhat different from the previous results. Our experimental results suggest that with the same offset length, the device with a wider space between the maingate and the subgate is more advantageous for hydrogenation. Experimental results show that the leakage current of the new device is two orders of magnitude lower than that of the nonoffset gated device, while the ON current of the new device is almost identical to the nonoffset gated device in the typically used frequency range (10-100 kHz)     

Kink-free polycrystalline silicon double-gate elevated-channelthin-film transistors

The authors report the characterization and analysis of a novel double-gate elevated-channel thin-film transistor (ECTFT) fabricated using polycrystalline silicon. The transistor has a thin channel and thick source/drain regions with a double-gate control. Using this structure, the kink effect in the I-V characteristics of a conventional TFT is completely eliminated, and leakage current at zero gate bias is reduced by over 15 times. The elimination of the kink effect and the significant reduction in leakage current are obtained due to the reduction in lateral electric field at the channel/drain junction region. Two-dimensional (2-D) device simulations are used to study the electric field reduction mechanism in the structure. Experimental results on the forward conduction and gate transfer characteristics of the structure are also presented     

A new laser-processed polysilicon TFT architecture

A new top gate polysilicon thin-film transistor (TFT) architecture is introduced which requires only a single laser process step to simultaneously crystallize the channel and activate the source-drain. The dummy-gate TFT (DGTFT) uses a light blocking layer patterned with the gate mask combined with two backside expose steps to allow a self-aligned device structure. N-channel TFTs fabricated using the new process have field effect mobilities greater than 100 cm²/Vs. By controlling the backside exposures it is also possible to form offset or graded doping structures to reduce field enhanced leakage currents     

A novel vertical bottom-gate polysilicon thin film transistor withself-aligned offset

A novel device structure for the vertical bottom polysilicon gate thin film transistor (TFT) with a self-align offset drain is proposed and demonstrated. The new VTFT allows a deep-submicron channel length, which is determined by the thickness of the active polysilicon film, not by the lithographic system resolution. The self-alignment offset drain reduces the leakage current, as a result, it exhibits good device performance     

A new self-aligned offset staggered polysilicon thin-filmtransistor

A new self-aligned offset staggered polysilicon thin-film transistor (poly-Si TFT) has been proposed and demonstrated to have a suppressed leakage current. For the self-aligned offset structure, planarization with thick photoresist and etchback of photoresist are successfully utilized. The offset length can be easily controlled by the thickness of the gate material without photolithographic limitation. In the self-aligned offset polysilicon TFT's, the leakage current decreases with an increasing offset length     

A new poly-Si TFT structure with air cavities at the gate-oxideedges

We propose a new poly-Si TFT structure employing air cavities at the edges of gate oxide in order to reduce the threshold voltage shift after electrical stress and to decrease the large leakage current. Due to the low dielectric constant of air, the air cavity behaves as a thick insulator reducing the vertical electric field near the drain, so that poly-Si region under air cavity acts as an offset. The new poly-Si TFT structure has been successfully fabricated by employing wet etching of the gate oxide followed by atmospheric pressure chemical vapor deposition (APCVD) oxide deposition. Our experimental results show that the leakage current is considerably reduced without decrease of the on-current and the device stability such as threshold voltage shift under high-gate bias is also improved     

Novel Offset-Gated Bottom Gate Poly-Si TFTs With a Combination Structure of Ultrathin Channel and Raised Source/Drain

We propose an offset-gated bottom gate polycrystalline silicon thin-film transistor (TFT), with a combination structure of ultrathin channel and raised source/drain, employing a simple process of the back surface exposure. It is experimentally and simulatively demonstrated that the new device has lower leakage current and better saturation characteristics, as compared with the conventional non offset TFT, due to the lateral electric field near the drain, which is reduced by the proposed structure. Moreover, the proposed TFT exhibits much better ON/OFF current ratio because the high current drive due to the raised source/drain structure is enough to compensate for the ON-state current reduction due to the offset-gate structure.     

Electrical characteristics of new LDD poly-Si TFT structuretolerant to process misalignment

A new lightly doped drain (LDD) poly-Si TFT structure having symmetrical electrical characteristics independent of the process induced misalignment is described in this paper. Based on the experimental results, we have established that there is no difference between the bi-directional I_D-V_G characteristics, and a low leakage current, comparable to a conventional LDD poly-Si TFT, has been maintained for this new poly-Si TFT. The maximum ON/OFF current ratio of about 1×10⁸ is obtained for the LDD length of 1.0 μm. In addition, the kink effect in the output characteristics has been remarkably improved in the new TFTs in comparison to the conventional non-LDD single- or dual-gate TFTs     

The effect of drain offset on current-voltage characteristics insub micron polysilicon thin-film transistors

We have examined the effect of drain offset structures with lengths ranging from 0.0 μm to 1.0 μm on submicron polysilicon TFT devices. The drain offset was found to exhibit resistive behavior that tends to lower the TFT drive current as it reduces the leakage current. For the range of channel lengths studied (1.0 μm to 0.35 μm) the optimum drain offset length was 0.35 μm     

A novel high-performance poly-silicon thin film transistor with aself-aligned thicker sub-gate oxide near the drain/source regions

Poly-Si TFTs with this new structure have been successfully fabricated and the results demonstrate a higher on-off current ratio of 5.9×10⁶ and also shows the off-state leakage current 100 times lower than those of the conventional ones at V_GS=-15 V and V_DS=10 V. Only four photo-masking steps are required and fully compatible with the conventional TFT fabrication processes. This novel structure is a good candidate for the further high-performance large-area device applications     

A new process of fabricating inverted-staggered tri-layer thin-filmtransistors

A new method of fabricating a-Si:H TFT with etching-stop structure has been proposed. Only one plasma-enhanced chemical vapor deposition is required in this new method and a PH₃/H₂ plasma treatment during the deposition has been used to form the TFT contact and thus saved another plasma deposition. With this method, a TFT of 500 Å active layer has been fabricated successfully. The drain current and saturation mobility of this device is 2.4×10^-7 A and 0.1 cm²/V sec, respectively, which is comparable to the conventional fabricating method. The plasma treatment will also form an additional leakage path on the TFT top surface and increase the TFT subthreshold slope. However, a current of less than 1 pA at V_G=-2.4 V can still be obtained. The possible mechanism of the contact formation by the plasma treatment is also discussed     

A novel thin-film transistor with self-aligned field induced drain

In this letter, a novel thin-film transistor with a self-aligned field-induced-drain (SAFID) structure is reported for the first time. The new SAFID TFT features a self-aligned sidewall spacer located on top of the drain offset region to set its effective length, and a bottom gate (or field plate) situated under the drain offset region to electrically induce the field-induced-drain (FID). So, unlike the conventional off-set-gated TFTs with their effective FID length set by two separate photolithographic masking layers, the new SAFID is totally immune to photomasking misalignment errors, while enjoying the low off-state leakage as well as high turn-on characteristics inherent in the FID structure. Polycrystalline silicon TFTs with the new SAFID structure have been successfully fabricated with significant improvement in the on/off current ratio     

High-voltage TFT fabricated in recrystallized polycrystallinesilicon

High-voltage thin-film transistors (TFTs) fabricated using CW-Ar laser annealed polycrystalline silicon have an offset gate structure between the source and gate and between the gate and drain. The breakdown voltage, transconductance, and leakage current in various size TFTs are described. These TFTs exhibited n-channel enhancement characteristics with a low-threshold voltage, and a breakdown voltage above 100 V could be obtained at an offset gate length of 20 μm. Active TFT circuits were fabricated with these high-voltage Si TFTs. These high-voltage TFT circuits can drive thin-film EL (electroluminescent display) at low signal voltage     

A Novel Four-Mask-Step Low-Temperature Polysilicon Thin-Film Transistor With Self-Aligned Raised Source/Drain (SARSD)

In this letter, a novel structure of polycrystalline-silicon thin-film transistors (TFTs) with self-aligned raised source/drain (SARSD) and a thin channel has been developed and investigated. In the proposed structure, a thick SD and a thin active region could be achieved with only four mask steps, which are less than that in conventional raised SD TFTs. The proposed SARSD TFT has a higher on-state current and a lower off-state leakage current. Moreover, the on/off current ratio of the proposed SARSD TFT is also higher than that of a conventional coplanar TFT     

Characteristics of offset-structure polycrystalline-siliconthin-film transistors

In order to reduce anomalous leakage current from n-channel polycrystalline-silicon thin-film transistors (poly-Si TFTs), an offset structure that has an n^- region between channel and n⁺ source-drain electrodes has been proposed. Drain-current measurements of the poly-Si TFT prove that the offset structure is effective in reducing the anomalous leakage current, and that the optimization of the offset length and the doping concentration in the offset region enlarge the ON/OFF current ratio. Implantation of 5×10¹³ cm^-2 phosphorus ions in the offset region makes the ON/OFF current ratio more than one order of magnitude larger than that of conventional structure TFTs     

Characteristics of p-channel polysilicon conductivity modulatedthin-film transistors

A p-channel polysilicon conductivity modulated thin-film transistor (CMTFT) is demonstrated and experimentally characterized. The transistor uses the concept of conductivity modulation in the offset region to obtain a significant reduction in on-state resistance. The conductivity modulation is achieved by injecting minority carriers (electrons) into the offset region through a diode added to the drain. Experimental results show that the conductivity modulation in the p-channel device is as effective as that in the n-channel device. This structure can provide 1.5 to 2 orders of magnitude higher on-state current than that of the conventional offset drain thin-film transistor (TFT) at drain voltage ranging from -15 V to -5 V while still maintaining low leakage current and simplicity in device operation. The p-channel CMTFT can be combined with the n-channel CMTFT to form CMOS high-voltage drivers, which is very suitable for use in fully integrated large-area electronic applications     

A p-channel poly-Si/Si1-xGex/Si sandwichedconductivity modulated thin-film transistor

A p-channel poly-Si/Si_1-xGe_x/Si sandwiched conductivity modulated thin-film transistor (CMTFT) is proposed and demonstrated in this paper for the first time. This structure uses a poly-Si/Si_1-xGe_x/Si sandwiched structure as the active layer to avoid the poor interface between the gate oxide and the poly-Si_1-xGe_x material. Also an offset region placed between the channel and the drain is used to reduce the leakage current. Furthermore, the concept of conductivity modulation in the offset region is used to provide high on-state current. Results show that this structure provides high on-state current as well as low leakage current as compared to that of conventional offset drain TFTs. The on-state current of the structure is 1.3-3 orders of magnitude higher than that of a conventional offset drain TFT at a gate voltage of -24 V and drain voltage ranging from -15 to -5 V while maintaining comparable leakage current