Mo- and Ti-silicided low-resistance shallow junctions formed using the ion implantation through metal technique

Mo-and Ti-silicided junctions were formed using the ITM technique, which consists of ion implantation through metal (ITM) to induce metal-Si interface mixing and subsequent thermal annealing. Double ion implantation, using nondopant ions (Si or Ar) implantation for the metal-Si interface mixing and dopant ion (As or B) implantation for doping, has resulted in ultrashallow ( ≤ 0.1-µm) p⁺-n or n⁺-p junctions with ∼30-Ω sheet resistance for Mo-silicided junctions and ∼5.5-Ω sheet resistance for Ti-silicided junctions. The leakage current levels for the Mo-silicided n⁺-p junctions (0.1-µm junction depth) and the Mo-silicided p⁺-n junction (0.16-µm junction depth) are comparable to that for unsilicided n⁺-p junction with greater junction depth ( ∼0.25 µm).     

Boron ion implantation in silicon through selectively deposited tungsten films

The effect of implanting boron into silicon through thin selective tungsten films and annealing to form silicided p⁺-n junctions is investigated. A rate limited thickness of 0.011-µm tungsten is shown to have the equivalent stopping power of 0.08-µm oxide and be similarly ineffective in eliminating axial boron channeling. Nonetheless, junction diodes as shallow as 0.25µm with sheet resistances of 7 Ω, exhibiting nearly idealI-Vcharacteristics from -40 to 100°C, are fabricated. Analysis of the areal and perimeter leakage currents suggests that defects at the WSi2-SiO2interface are the contributing generation-recombination sites.     

Titanium nitride local interconnect technology for VLSI

This paper reports on how the self-aligned titanium disilicide process, normally used to simultaneously reduce MOS gate and junction sheet resistances to less than 1 Ω/square, has been extended to provide a layer of local interconnect for VLSI CMOS applications. The local interconnect level has been realized by utilization of the titanium nitride (TIN) layer that forms during the gate and junction silicidation process. Normally the TiN layer is discarded, but in this process the 0.1-µm-thick TiN layer is patterned and etched to provide local connections between polysilicon gates and n⁺and p⁺junctions, with a sheet resistance of less than 10 Ω/ square. This is accomplished without area consuming contacts or metal straps, and without any extra deposition steps. In addition to providing a VLSI version of the buried-contact process, the technology permits the widespread use of self-aligned contacts and minimum geometry junctions. These features significantly reduce parasitic capacitance with the result that the signal propagation delay through a 1-µm CMOS inverter is decreased by 20- 25 percent. The TiN local interconnect process has been successfully demonstrated by the fabrication of a pseudo-static CMOS VLSI memory with nearly half a million 1-µm transistors. A full CMOS 16K SRAM has also been fabricated in which the TiN layer performs the gate to n⁺and p⁺junction cross-coupling function. Application of the technology to achieve a high-density full CMOS SRAM cell, that makes a 256K SRAM chip size of less than 80K mils²feasible with 1-µm design rules, is also discussed.     

NMOS Ring oscillators with cobalt-silicided P-diffused shallow junctions formed during the "Poly-plug" contact doping cycle

Composite silicided source-drains are being developed to provide low-resistance shallow junctions for high performance fine-line circuits. The junctions are usually formed either by implantation and drive prior to silicide formation or else by implantation immediately after, followed by a heat cycle. This paper describes a novel approach for the fabrication of CoSi2/n⁺-p junctions (2 . 5 Ω/□ sheet resistance), wherein the junctions are doped by diffusion through the contact windows using the conventional "poly-plug" doping cycle [1], [2]. LPCVD poly-Si is deposited on windows to previously silicided gate and source-drain regions, and exposed to PBr3at an elevated temperature. Since the diffusivity of dopants in silicides is higher than in bulk Si, this step transports the P through the poly-Si via the windows laterally into the silicide, to form uniformly doped junction surrounds. This poly-Si doping scheme for junction fabrication eliminates an ion-implant step, provides an independent means of tailoring channel length, and can potentially result in low-resistance contacts even if the window etch step has punched through the silicide, Electrical characteristics of 1.25-µm gate-length ring oscillators are similar to those of circuits processed with the conventional As implant and drive. TransistorI-V's and subthreshold behavior remain unaffected by the silicide doping process. Junction depth and leakage are sensitive functions of the poly-plug thermal cycle, with a 950°C 30-min drive resulting in 0.3-µm junctions. For a 1-µm design rule circuit layout, 30 to 45 min at 950°C is judged adequate.     

0.4-µm gate-length devices fabricated by contrast-enhanced lithography

This letter describes the fabrication of submicrometer polysilicon-gate MOS devices by an advanced optical process called contrast enhancement. Functional devices having gate lengths as small as 0.4 µm were fabricated with this process. Contrast-enhanced lithography (CEL) allows usable photoresist patterns to be fabricated at smaller dimensions than is possible with conventional resist. The simultaneous replication of mask dimensions for isolated lines at 0.35 µm and above was achieved in this work using a single exposure on an Optimetrix 10:1 DSW system. Contrast enhancement has been applied to the fabrication of n-channel MOS devices having gate lengths from 0.4 to 1.5 µm in steps of 0.1 µm. Long-channel devices were also fabricated. The transconductance of the 0.4-µm devices is 40 mS/mm at Vds= 5 V. Threshold voltages (Vds= 0) are nearly independent of gate length, ranging from 1.21 to 1.31 V over the 7.5- to 0.4-µm range in gate length. The effective mobility for long-channel devices is 430 cm²/V.s.     

Analysis of pattern accuracy in submicrometer electron-beam direct writing

To create submicrometer patterns with high accuracy on thick single-layer negative resist, error factors that degrade pattern accuracy have been investigated. Pattern accuracy was analyzed using a new evaluation method based on the difference between the resist development energy and the exposure energy at points on the edge of each shape. By introducing a new evaluation parameter, we were able to clarify error factors from the exposure conditions, the proximity effect correction method, and the machine exposure fluctuation. The evaluation parameterKisQ/Q_{0}whereQis the exposure dose appropriate for the desired resist thickness and Q0is the interface gel dose. It was found that the resist resolution and the rounding error of the exposure dose were serious error factors, especially in delineation on submicrometer patterns. To achieve 0.5-µm patterns with ±0.1-µm accuracy on 1-µm-thick negative resist, the resist evaluation parameterKmust be less than 2, the rounding error of the exposure dose must be less than 2.5 percent of the dose, and the beam addressing unit (LSB) must be less than 0.025 µm.     

Formation of TiN/TiSi2/p+-Si/n-Si by rapid thermal annealing (RTA) silicon implanted with boron through titanium

A low temperature method of fabricating conductive (3.5 Ω/ sq.) p⁺/n junction diodes possessing excellentI-Vcharacteristics with reverse-bias leakage less than -3 nA.cm^-2at -5 V is described. Single crystal n-type 〈100〉 Si is implanted with 60 keV¹¹B+through 0.028-µm thick sputtered Ti film. Rapid thermal annealing (RTA) in an N2ambient simultaneously forms a 0.36-µm deep p⁺/n junction and a 0.063-µm thick bilayer of TiN and TiSi2with a resistivity of 22 µΩ.cm. The electrical properties of these diodes are not degraded by annealing for 30 min at 500°C, suggesting that the outer layer of TiN is an effective diffusion barrier between TiSi2and Al.     

Characteristics of a 1.2-µm CMOS technology fabricated on an RF-heated zone-melting recrystallized SOI

0.7-5-µm CMOSFET's were fabricated on SOI which was recrystallized using an RF-heated zone-melting recrystallization (RFZMR) method. The leakage currents of n-channel MOSFET's having gate lengths between 5- and 0.7-µm range between 10^-14and 10^-12A/µm and show no dependence on channel length. Those of the p-channel MOSFET's were 10^-14-10^-12A/µm when the gate lengths were longer than 1.2 µm, and increased when the gate lengths were shorter than 1.0 µm. The propagation delay time of the CMOSFET inverter was 0.13 ns per stage at a supply voltage of 3.5 V.     

Computer-controlled scanning electron microscope system for high-resolution microelectronic pattern fabrication

A small, dedicated computer has been interfaced to a scanning electron microscope (SEM) for the purpose of generating, registering, and fabricating microelectronic device and circuit patterns with submicron dimensions. A preliminary registration accuracy of ±0.1 µm over a (950-µm)²pattern field has been demonstrated.     

Ga0.4In0.6As/Al0.55In0.45As pseudomorphic modulation-doped field-effect transistors

High-performance pseudomorphic Ga0.4In0.6As/ Al0.55In0.45As modulation-doped field-effect transistors (MODFET's) grown by MBE on InP have been fabricated and characterized. DC transconductances as high as 271, 227, and 197 mS/mm were obtained at 300K for 1.6-µm and 2.9-µm gate-length enhancement-mode and 2-µm depletion-mode devices, respectively. An average electron velocity as high as 2.36 × 10⁷cm/s has been inferred for the 1.6-µm devices, which is higher than previously reported values for 1-µm gate-length Ga0.47In0.53As/Al0.48In0.52As MODFET's. The higher bandgap Al0.55In0.45As pseudomorphic barrier also offers the advantages of a larger conduction-band discontinuity and a higher Schottky barrier height.     

Two-layer resist structure for electron-beam fabrication of a submicrometer gate length GaAs device

A two-layer resist structure using EBR-9 and PMMA for fabricating a fine metal line with a mushroom-like cross-sectional profile is reported. The structure provides T-shaped resist cavities with undercut profiles using electron-beam exposure. With the optimum developing condition, the bottom opening is as small as 0.1 µm, and the top opening is wide enough not to require an additional exposure in order to obtain a mushroom-like metal lift-off pattern. A Monte Carlo calculation is carried out in order to analyze the profile of the two-layer resist structure, and it is shown that an undercut T-shaped resist profile with a 0.1-µm bottom opening can be obtained using a high-sensitivity resist on a low-sensitivity resist structure. A 0.15-µn mushroom-like lift-off metal profile has been fabricated on a 0.1-µm recessed GaAs substrate by the use of this resist structure.     

Sensitivity measurement of a 10.6-µm parametric upconverter

The sensitivity of a parametric upconverter for the detection of 10.6-µm radiation was measured. 10.6-µm radiation was mixed with the 1.06 µm beam of an Nd :YAG laser in properly oriented single-crystal proustite. The upconverted output at 0.967 µm was then detected by an S-1 photomultiplier tube. NEP of 1.1×10^-9W . s^½was measured.     

A highly latchup-immune 1-µm CMOS technology fabricated with 1-MeV ion implantation and self-aligned TiSi2

A 1-µm n-well CMOS technology with high latchup immunity is designed, realized, and characterized. Important features in this technology include thin epi substrate, retrograde n-well formed by 1-MeV ion implantation, As-P graded junctions, and self-aligned titanium disilicide. The 1-µm CMOS technology has been characterized by examining the deviceI-Vcurves, avalanche-breakdown voltages, subthreshold characteristics, short-channel effect, and sheet resistances. The devices fabricated by using the 1-MeV ion implantation and self-aligned titanium disilicide do not deviate from the conventional devices constructed with the same level of technology. With the As-P double-diffused LDD structure for the n-channel device, the avalanche-breakdown voltage is increased and hot-electron reliability is greatly improved. The titanium disilicide process effectively reduces the sheet resistances of the source-drain and the polysilicon gate to 3 Ω/□ compared with 150 Ω/□ of the unsilicided counterparts. The optimized 1-µm device channel n-well CMOS resulted in a propagation delay time of 150 ps with a power dissipation of 0.3 mW. With the thin epi wafers and the retrograde n-well structure, latchup immunity is found to be greatly improved. Moreover, with the titanium disilicide formation on the source-drain, the latchup holding voltage is found to be extremely high (13 V) with the substrate grounded from the backside of the wafer. If the backside substrate is not grounded, self-aligned disilicide over n⁺and p⁺regions are found necessary to ensure high latchup immunity even in the case of thin epi on heavily doped substrate. The degradation of emitter efficiency due to the TiSi2is believed to be the dominant factor in raising the holding voltage. Detailed experimental results and discussions are presented.     

Efficiency of the a-Si:H solar cell and grain size of SnO2transparent conductive film

The relationship between average grain size on the surface of SnO2transparent conductive film and conversion efficiency of the a-Si:H solar cell was investigated. a-Si:H solar cells were fabricated on SnO2/glass substrates with various grain sizes. The cell structure was glass/p(SiC)-i-n/Al and the effective cell area was 4 × 10^-2cm². The reflectivity from the glass substrate was reduced to about 7 percent with increasing the grain size from 0.1 to 0.8µm, and the short-circuit current was inceased from 12 to 14mA/cm². A 7.9 percent of conversion efficiency was achieved using milky SnO2film of 0.4-µm average grain size at AM-100mW/cm².     

RECIPE—A two-dimensional VLSI process modeling program

REnsselaer Computer integrated Circuits Process Engineering (RECIPE) is a two-dimensional (2-D) integrated circuit process modeling program developed for use in VLSI applications. The program incorporates a 2-D diffusion model which includes the concentration dependence of the diffusion coefficients. An incremental solution method is used to compute the appropriate diffusion coefficients as a function of impurity concentration throughout space. RECIPE also incorporates a 2-D ion-implantation model. While intended as a general-purpose modeling program, RECIPE has been used to study channel-length decrease of short-channel MOSFET's during high-temperature processing. A typical phosphorus-implanted (150 keV, 10¹⁶/cm²) 1-µm gate transistor had no channel after processing for 60 min at 1000°C, while an arsenic-implanted device had an effective channel length of ∼ 0.1 µm after similar processing.     

High-speed polysilicon emitter—base bipolar transistor

High-speed polysilicon emitter and base electrode Si n-p-n bipolar devices were fabricated showing performances of 55-ps ECL gate delay (FI = FO = 1) and cutoff frequency of 15.6 GHz (at VCE= 3 V, LVCEO= 6.8 V). These devices were built on an oxide-isolated substrate produced by planarizing oxide which is deposited after device Si island etching. The final emitter width is 0.5 µm, and a 1.3-µm-thick arsenic-doped LPCVD epitaxial layer of 0.25 Ω.cm is utilized. Emitter-base (E-B) junctions formed by direct implantations of arsenic and boron ions into a substrate were compared with junctions induced by diffusing dopants from implanted polysilicon. In the case of diffused junctions, an emitter junction depth of less than 500 Å along with a 1000-Å base width can be obtained.     

Ballistic transport and properties of submicrometer Silicon MOSFET's from 300 to 4.2 K

The characteristics of submicrometer silicon MOSFET's have been measured from 300 to 4.2 K, and the mobility versus temperature and carrier velocity versus longitudinal field as a function of temperature have been plotted. Effective mobilities in 500-µm-square devices as high as 25 000 cm²/V . s at 4.2 K have been observed. Mobilities of this magnitude represent mean free path lengths that could lead to ballistic transport in submicrometer devices. Effective mobilities in 0.2-µm devices were only 800 cm²/V . s at 4.2 K due to high-field effects. The mobility versus effective channel length for 0.2-, 0.7-, and 1.7-µm devices operating at drain voltages of 0.1 V has been plotted, and it has been observed that the mobility is greatly reduced in short-channel devices. The mobility versus longitudinal field was studied, resulting in the observation that ballistic transport is inhibited by the high fields in devices operating at 0.1 V. Similar high-field effects should limit the effects of ballistic transport in high-mobility semiconductors such as submicrometer GaAs FET's Operating at nominal supply voltages.     

Junction-current-confinement planar light-emitting diodes and optical coupling into large-core diameter fibers using lenses

High-radiance AlGaAs-GaAs double-heterostructure light-emitting diodes utilizing junction current confinement are described. Diode resistance and junction ideality factor are investigated as a function of emission diameters from 10 to 75 µm. Near-field intensity profiles indicate tight current confinement over the full range of emission diameters. Rise-time measurements are consistent with a simple carrier lifetime model for >25-µm emission diameters. An effective radiative-recombination constant, B = 1.5(±0.5) × 10-¹⁰cm³/s is deduced from the rise-time data and model. Peak wavelength and spectral width data are discussed in terms of junction current density and temperature. With decreasing emission diameter, the optical coupling efficiencies into 100- and 200-µm core diam high-numerical-aperture fibers increased from 10 to 25 percent and 25 to 50 percent, respectivley, using spherical glass lenses.     

Boundary conditions in regional Monte Carlo device analysis

A new set of boundary conditions is proposed which allows Monte Carlo (MC) calculations to be carried out accurately in preselected regions of a device structure, thus avoiding impractically long computation time. This technique has been applied to three different silicon device structures: an n-p junction, a 0.3-µm basewidth n⁺-n-n⁺diode, and an n⁺-p-n-n⁺bipolar-transistor structure with a 0.1-µm basewidth. The results indicate difficulties with the MC method when applied to regions where a large retarding field exists. A comparison of the results where both the entire device structure can be analyzed and the "regional" MC calculation can be performed, using the proposed boundary conditions, shows good agreement. The computation time using the regional approach, however, is substantially less.     

Normally-off InGaAs junction field-effect transistor with InGaAs buffer layer

InGaAs junction field-effect transistors (JFET's) with 1-µm gate length were successfully fabricated with an n⁺-InGaAs active layer (8 × 10¹⁶cm^-3) and an undoped InGaAs buffer layer grown on semi-insulating InP:Fe substrate by liquid-phase epitaxy. The device showed good pinch-off behavior with a threshold voltage of 0.25 V, a low drain current of 1 µA at zero gate-source voltage, and a very high transconductance of 553 mS/mm at room temperature. This is one of the highest transconductance values ever reported for a 1-µm gate-length FET.