Hyperabrupt junctions in Au-Si Schottky diodes by ion implantation

The application of ion implantation to the fabrication of Au-Si Schottky diodes with highly nonlinear capacitance/voltage characteristics is described. The capacitance/voltage characteristic and the derived impurity profile are given for a typical diode. The forward current/voltage characteristics are described, and an estimate of Au-Si barrier height is made.     

A simple method for determining the impurity distribution near a p-n junction

It is well known that the form of the dependence upon bias voltage of the incremental space-charge layer capacitance of an asymmetrically-dopedp-njunction depends (in a rather complicated way) upon the concentration profile of the impurity charge on the high-resistivity side. It is shown in this paper that this impurity profile is related, in a very simple way, to the dependence of the incremental space-charge layer elastance upon the total depletion charge in either half of the dipole layer. The incremental-elastance vs. charge relationship has been employed in a simple pulsed-charge automatic measurement system which yields the impurity profile directly, as the slope of anx-yrecording. The system has advantages for rapid evaluation of impurity distributions in the base regions of transistors. These same advantages apply for the high-resistivity sides of asymmetrically doped diodes, under circumstances in which the quick automatic plotting feature is needed, very high accuracy is not required, and the reverse saturation current of the junction is small.     

Breakdown and capacitance properties of hyperabrupt epitaxial Schottky barrier diodes

An analysis of the breakdown and capacitance properties of punch-through hyperabrupt epitaxial Schottky barrier diodes has been carried out. Results are given for the dependence of breakdown voltage of such a device on surface concentration and epitaxial layer thickness. Design curves are given for epitaxial hyperabrupt schottky varactor diodes. The design procedure yields an optimal impurity profile in which just-punch-through occurs at the highest voltage of operation. This gives a maximum dynamic range of operation still keeping the series resistance to a minimum. A corrected boundary condition to determine the profile constants associated with an n/n⁺ (high/low) junction is also given.     

Evaluation of voltage dependent series resistance of epitaxial varactor diodes at microwave frequencies

The series resistance of a high-quality varactor diode is primarily determined by the resistance of the semiconductor material close to the junction. With increasing reverse bias, the width of the space-charge region becomes greater, and the series resistance decreases. Theoretical models of graded and step junctions have been assumed, and calculations have been made of the series resistance as a function of bias. Epitaxial silicon diodes have been measured for series resistance as a function of bias by using the transmission loss method at 6 to 12 Gc/s, with the diode mounted across a reduced-height waveguide. The variation of series resistance with bias agrees well with the theoretical calculations. By measuring of the 3-dB bandwidth of the series resonance of the diode mounted in the reduced-height waveguide, the junction capacitance and the effective series inductance of the package also can be determined. Because the width of the space-charge region must vary with applied voltage in order to obtain the varactor characteristic, the diode cannot have zero-series resistance at zero-volt bias. The minimum possible series resistance is a function of the breakdown voltage and increases with increasing breakdown voltage. Calculations of the maximum possible cutoff frequency as a function of the diode breakdown voltage are presented for both graded and step junction silicon varactors. A plot of series resistance vs. reverse bias can be used to determine the impurity concentration profile in the epitaxial film. The impurity concentration profile can also be determined by measuring the capacitance vs. reverse bias, a technique which has been in use for some time. However the former method appears to be more accurate in that it is independent of junction area.     

Quarter-micrometer SPI (Self-aligned Pocket Implantation) MOSFET'sand its application for low supply voltage operation

A novel SPI (Self-aligned Pocket Implantation) technology has been presented, which improves short channel characteristics without increasing junction capacitance. This technology features a localized pocket implantation using gate electrode and TiSi₂ film as self-aligned masks. An epi substrate is used to decrease the surface impurity concentration in the well while maintaining high latch-up immunity. The SPI and the gate to drain overlapped structure such as LATID (Large-Angle-Tilt Implanted Drain) technology allow use of the ultra low impurity concentration in the channel region, resulting in higher saturation drain current at the same gate over-drive compared to conventional device. The carrier velocity reaches 8×10⁶ cm/sec and subthreshold slope is less than 75 mV/dec, which can be explained by low impurity concentration in the channel and in the substrate. The small gate depletion layer capacitance of SPI MOSFET was estimated by C-V measurement, and it can explain high performance such as small subthreshold slope. On the other hand, the problem and the possibility of low supply voltage operation have been discussed, and it has been proposed that small subthreshold slope is prerequisite for low power device operated at low supply voltage. In addition, the drain junction capacitance of SPI is decreased by 65% for N-MOSFET's, and 69% for P-MOSFET's both compared with conventional devices. This technology yields an unloaded CMOS inverter of 48 psec delay time at the supply voltage of 1.5 V     

Enhancement in electrical properties of Au/n-GaAs Schottky diodes exposed to 60Co gamma rays

The effect of γ-ray exposure on the electrical characteristics of Au/n-GaAs Schottky barrier diodes has been investigated using current–voltage and capacitance–voltage techniques. The results indicate that irradiation with a cumulative dose of 10 Mrad (Si) improves the electrical characteristics of the diode. The parameters like ideality factor, series resistance and reverse leakage current determined from the current–voltage data decreases, whereas the barrier height and rectification ratio increases upon irradiation. The effective barrier height deduced from the capacitance–voltage technique has also increased with irradiation. The irradiated diode shows a higher carrier concentration compared to the virgin diode. The observed overall improvement in the diode quality is attributed to the annealing effect of γ-rays.     

Mechanisms of the degradation of Schottky-barrier photodiodes based on ZnS single crystals

The effect of ultraviolet (UV) illumination on the electrical and spectral characteristics of Schottky-barrier photodiodes based on ZnS single crystals is studied. It is found that irradiation deteriorates their photosensitivity and changes the current–voltage and capacitance–voltage characteristics and the surface profile of the blocking electrode. It is shown that the main reason for a decrease in the photosensitivity of the diodes is the photoinduced drift of mobile donors in the electric field of the barrier. This drift depends on the crystallographic orientation of the surface being irradiated. Another photoinduced process observed in the diodes is photolysis of the ZnS crystal. This process mainly determines the change in the electrical characteristics of the diodes and in the surface profile of the electrode at an insignificant change in the photosensitivity.     

L、S波段俘越二极管性能参数的实验研究

在以击穿电压V_b和结电咨C_j(-60)作为器件低频参数的基础上,研究了器件低频参数与高频性能的关系,增添电容比C_r(=[C_j(-1)]/[C_j(-60)]作为低频参数.实践表明,L、S波段俘越二极管各有相应的C_r最佳范围,凡具有最佳C_r范围的器件有好的俘越振荡性能.本文还介绍了器件C_r与外延材料的杂质浓度N的关系.可据此关系选抒外延材料的杂质浓度N来制造器件,使得80%以上批次的器件部具有好的俘越振荡性能.     

Numerical simulation of the effect of gold doping on the resistance to neutron irradiation of silicon diodes

We have carried out a numerical simulation of the effect of gold doping on the electrical characteristics of long silicon diodes exposed to neutron irradiation. The aim is to investigate the effect of gold on the hardness of the irradiated diodes. The reverse current voltage and capacitance voltage characteristics of doped and undoped diodes are calculated for different irradiation doses. The leakage current and the effective doping density are extracted from these two characteristics respectively. The hardness of the diodes is evaluated from the evolution of the leakage current and the effective doping density with irradiation doses. It was found that diodes doped with gold are less sensitive to irradiation than undoped ones. Thus gold appears to stabilise the electrical properties on irradiation. The conduction mechanism is studied by the evolution of the current with temperature. The evaluated activation energy indicates that as the gold doping or irradiation dose increases, the current switches from the basic diffusion to the generation-recombination process, and that it can even become ohmic for very high gold densities or irradiation doses.     

D.C. measurement of the space charge capacitance and impurity profile beneath the gate of an MOST

An analysis of the MOS Transistor with bias between the source and substrate has shown that when the surface is weakly inverted, the silicon space charge capacitance over a wide range of temperature and bias can be obtained from the change in gate voltage required to maintain a constant channel current. The substrate impurity profile beneath the gate oxide can then be calculated from capacitance-bias measurements.     

Junction capacitance and related characteristics using graded impurity semiconductors

The transition capacitance of a junction of semiconductors with constant impurity density is well-known and varies inversely with the square root of the bias voltage. This paper analyzes the variation of transition capacitance with bias voltage of a junction of semiconductors with graded impurity densities; i. e., densities which are an arbitrary function of position. It is found that the transition capacitance can be simply related to a depletion width and that, in turn, depletion width can be related to the bias voltage. An analysis is also carried out for the impurity grading to produce a specified transition capacitance variation, as for instance, a linear variation of capacitance with bias voltage. It is also possible to determine impurity gradings to satisfy certain special conditions. An example of this type that is considered in some detail is the determination of the impurity grading which will produce avalanche breakdown simultaneously throughout the semiconductor. An important result of the analysis is that the capacitance vs bias voltage relation can be favorably modified by suitable choice of impurity grading (see Fig. 7). The practical realization of the various characteristics considered in this article is contingent upon techniques for fabricating semiconductors with specified impurity gradings.     

Influence of an impurity profile on the determination of interface states

In order to determine the density of interface states from C(V) curves for high test frequencies, a comparison is made with a computed curve for uniform impurity concentration but identical minimum capacitance. The curves calculated for a doping profile (due, say, to acceptor depletion near the surface of a p-type semiconductor) are assumed to represent the measured C(V) curves of MOS diodes. A number of “charges in interface states” (8 × 10¹⁰ cm^?2 in the given example) are simulated by the impurity profile. This shows that it is not sufficient to introduce a mean effective substrate impurity concentration by adapting the minimum capacitance in the inversion region.The same accordingly applies for the C(V) curves for low test frequencies. The error due to “simulated interface states” is reduced somewhat, but it remains the altered relation between the applied voltage and the surface potential.     

Determination of the interface properties of Ni-silicided strained-Si/SiGe heterostructure Schottky diodes using capacitance–voltage technique

Capacitance–voltage (C–V) profiling has been used to study the interface properties and apparent doping profile of NiSi/strained-Si heterostructure Schottky diodes. The interface states have been characterized using the capacitance–voltage (C–V) and capacitance–frequency (C–f) techniques for diodes annealed at 400 and 600 °C. Based on the depletion approximation and interfacial layer with interface states, an equivalent circuit model has been developed to explain the anomalous C–V characteristics observed in case of silicided-Schottky diodes. Self-consistent analytical expressions, developed from the proposed equivalent circuit, have been used to simulate the experimental C–V characteristics using both the MATHCAD and SEMICAD device simulation tool. An excellent agreement has been obtained between the experimental and simulated C–V characteristics, which strongly support the validity of the proposed model.     

Development of mathematical models of semiconductor devices for computer-aided circuit analysis

This paper describes the development and verification of mathematical models which will approximate the electrical characteristics of Zener and/or avalanche diodes and tunnel diodes. Each model consists of a circuit of discrete components with their defining equations. The equations are in a form compatible with the digital computer language which makes the models useful in analysis and design, by computer, of electronic circuits containing these devices. The Zener diode model is basically the familiar Ebers-Moll conventional diode model except that additional current sources have been added to approximate the voltage regulation when breakdown of the junction occurs. The equation for junction capacitance has been modified to model the decrease in capacitance due to avalanche in the junction. A tunnel diode model is presented which approximates the entire static characteristic, including the negative resistance region. Methods for extracting model parameters from a limited number of easily obtainable data points are developed. A method for measuring and describing junction capacitance is also presented.     

Physical equivalent circuit model for planar Schottky varactordiode

A physical equivalent circuit model for the planar GaAs Schottky varactor diode is presented. The model takes into account the distributed resistance and capacitance of the active layer, the sidewall capacitance, and the parasitic resistances and accurately accounts for the high series resistance observed near the pinch-off voltage. The dependence of the maximum series resistance on varactor size, frequency, and doping profile has been theoretically investigated, and the results agree well with experimental data. The proposed model can be easily used for optimization of planar Schottky varactor diodes with regard to broadband monolithic VCO constraints     

On the voltage‐dependent series resistance of a planar Schottky barrier diode

The series resistance of a planar Schottky barrier diode fabricated on p‐type silicon is investigated by analysing the current–voltage characteristics of the device. Different characterisation techniques have been applied to obtain the value of the series resistance of the device. It is found that the existing techniques are either not applicable for the present device or yield unreliable value for the series resistance. A numerical analysis of the I–V data reveals unusual voltage dependence of the series resistance of the device. The anomaly has been resolved by postulating a potential barrier at the ohmic contact and drawing analogy to serially connected high‐ and low‐barrier diodes in a back‐to‐back configuration. It is found that the voltage dependence of the series resistance of the device can be described by certain empirical law, which also applies to device on GaN. The measured voltage behaviour of the ac resistance and capacitance of the device at different frequencies have been found to be consistent with those of a serial combination of diodes considered to verify the postulate made in interpreting the I–V data.     

Design considerations of hyperabrupt varactor diodes

This paper describes the design calculations and fabrication techniques used to produce hyperabrupt varactor diodes. The computation consists of determining, the doping profile, the capacitance as a function of applied voltage, the breakdown voltage, and the series resistance; allowance is made for the nonlinear variation of mobility with doping density. Fabrication of the retrograded region was accomplished by diffusion from a doped-oxide source. Two groups of diodes were fabricated. The first group had a breakdown voltage VBof 95 V at 1 µA, a capacitance ratio of 12 over a voltage range of 1 to 40 V (C_{P1}/C_{P40}=12), and a quality factorQof 60 at an operating level of 3 V and 100 MHz. The corresponding values for the second group were VB=45 V (C_{P1}/C_{P40}=4) andQ=210. The capacitance tracking capability of these diodes was found to be within 2 percent. These measurements showed excellent correlation with calculated results.     

Characteristics of diffused P-N junctions in epitaxial layers

A one-dimensional analysis has been made to determine properties of diffused p-n junctions in epitaxial layers with nonuniform impurity concentration. Impurity diffusion from the surface and from the substrate is assumed to have complementary error function distribution. The transcendental equations obtained by analytical integration of Poisson's equation were evaluated numerically with the IBM 7090/94. Junction depth, impurity gradient and impurity level at the junction are given for a variety of diffusion parameters and impurity concentrations. In addition, graphs are presented, showing the relationship between reverse voltage and depletion layer thickness, capacitance per unit area, and peak electric field for the case of silicon. A comparison between the actual impurity profile and the usual linear approximation using the impurity gradient at the junction gives the range of depletion layer thickness or reverse voltage in which such an approximation is justified. Further, examples are presented of the electric field distribution in the depletion layer for several impurity concentration profiles. Calculated and experimentally determined values of some readily accessible junction characteristics show reasonably good agreement.     

A Monolithically Integrated 12V/5V Switch-Capacitor DC-DC Converter

A monolithically integrated 12V/SV switch capacitor DC-DC converter with structure-simplified main circuit and control circuit is presented. Its topological circuit and basic operating principle are discussed in detail. It is shown that elevated operating frequency, increased capacitance and reduced turn-on voltage of the diodes can make the converter's output characteristics improved. Reducing resistance of the equivalent resistors and other parasitic parameters can make the operation frequency higher. As a feasible efficient method to fabricate monolithically integrated converter with high frequency and high output power, several basic circuits are parallelly combined where the serial-parallel capacitance is optimized for the maximum output power. The device selection and its fabrication method are presented. A feasible integration process and its corresponding layout are designed. All active devices including switching transistors and diodes are integrated together with all passive cells including capacitors and resistor on a single chip based on BiMOS process,as has been verified to be correct and practical by simulation and chip test.     

A simple model for computer simulation of Schottky-barrier diodes

To simulate the electrical characteristics of metal-semiconductor Schottky barrier diodes, a numerical analysis program based on the Shockley's semiconductor equations has been established. The thermionic emissions of electrons and holes from semiconductor to metal as well as the electric field in the interfacial layer are taken as the derivative boundary conditions of the nonlinear equations. The forward and reverse current-voltage characteristics of various metal-silicon and metal-silicide-silicon Schottky barrier diodes can be simulated by properly choosing the zero-field barrier height and the interfacial-layer capacitance. The barrier height variation as a function of applied voltage is related to the space-charge density and the interfacial-layer capacitance. The nonideality of forward characteristics is attributed to the bending of majority carrier imref and the raising of barrier height. The soft behavior of reverse characteristics can be modeled in terms of the interfacial-layer capacitance.