Ku波段GaN单片低噪声放大器的研制

研制了一款Ku波段GaN单片低噪声放大器,该放大器采用了GaN 0.25μm Ku功率工艺,工作电压为10 V。在12~18 GHz频带内,噪声NF≤2.9 d B,增益G≥20 d B,输入驻波比VSWR1≤1.8,输出驻波比VSWR2≤1.5。该芯片在16 GHz下,承受38 d Bm的大功率输入脉冲(周期为1 ms,占空比为10%)10 min,经测试未发现低噪声放大器芯片烧毁的现象。     

Highly Rugged 30 GHz GaN Low-Noise Amplifiers

GaN low-noise amplifiers (LNAs) operating at 27-31 GHz are presented in this letter. The monolithically integrated LNAs were fabricated using the process line of the Ferdinand-Braun-Institut. Noise figures of 3.7 to 3.9 dB were measured. The ruggedness of the LNAs was verified by noise measurements after stressing the LNA for up to 2 h with up to 33 dBm of input power. These conditions are among the most severe stress tests reported in literature. To the best of the authors knowledge, this is the first demonstration of a GaN LNA in this frequency region.     

Low-Noise Cooled GASFET Amplifiers

Measurements of the noise characteristics of a variety of gallium-arsenide field-effect transistors at a frequency of 5 GHz and temperatures of 300 K to 20 K are presented. For one transistor type detailed measurements of dc parameters, small-signal parameters, and all noise parameters (T/sub min/, R/sub opt/, X/sub opt/ g/sub n/) are made over this temperature range. The results are compared with the theory of Pucel, Haus and Statz modified to include the temperature variation. Several low-noise ampifiers are described including one with a noise temperature of 20 K over a 500-MHz bandwidth. A theoretical analysis of the thermal conduction at cryogenic temperatures in a typical packaged transistor is included.     

Desensitized CMOS Low-Noise Amplifiers

The minimum attainable noise figure for scaled- CMOS low-noise amplifiers (LNAs) is limited by impedance mismatches such as the well-known noise/power tradeoff. In this paper, we show that a power-constrained optimization of the device noise resistance parameter, R_n, significantly reduces the impact of mismatches and variations and leads to an almost simultaneous noise and power match. This process, called desensitization, makes the design largely immune to measurement and modeling errors and manufacturing variations, and significantly reduces frequency-dependent noise mismatches in wide-band LNAs. Measured data from devices and desensitized LNAs designed on 180-nm and 90-nm CMOS processes shows that: (1) a device size selected for optimum R_nmiddot is less sensitive to source impedance mismatches and provides a wide-band noise match; and (2) LNAs approach a simultaneous input and noise match, and exhibit significant improvements (ges 2x) in their wide-band noise performance.     

Design and Analysis of Broadband Dual-Gate Balanced Low-Noise Amplifiers

In this paper, we present three MMIC low-noise amplifiers using dual-gate GaAs HEMT devices in a balanced amplifier configuration. The designs target three different frequency bands including 4-9 GHz, 9-20 GHz, and 20-40 GHz. These dual-gate balanced designs demonstrate the excellent qualities of balanced amplifiers in terms of stability and matched characteristics, while demonstrating higher bandwidth than designs with a single-stage common-source device. Additionally, noise performance is excellent, with the 4-9 GHz LNA demonstrating <1.75 dB noise figure (NF), the 9-20 GHz LNA <2.75 dB NF and the 20-40 GHz LNA <2.5 dB NF. Demonstrating high gain and excellent bandwidth, the dual-gate devices seem a logical choice for the balanced amplifier topology.     

Design of Cryogenic SiGe Low-Noise Amplifiers

This paper describes a method for designing cryogenic silicon-germanium (SiGe) transistor low-noise amplifiers and reports record microwave noise temperature, i.e., 2 K, measured at the module connector interface with a 50-Omega generator. A theory for the relevant noise sources in the transistor is derived from first principles to give the minimum possible noise temperature and optimum generator impedance in terms of dc measured current gain and transconductance. These measured dc quantities are then reported for an IBM SiGe BiCMOS-8HP transistor at temperatures from 295 to 15 K. The measured and modeled noise and gain for both a single-and two-transistor cascode amplifier in the 0.2-3-GHz range are then presented. The noise model is then combined with the transistor equivalent-circuit elements in a circuit simulator and the noise in the frequency range up to 20 GHz is compared with that of a typical InP HEMT.     

12-GHz-Band Low-Noise GaAs Monolithic Amplifiers

One- and two-stage 12-GHz-band low-noise GaAs monolithic amplifiers have been developed for use in direct broadcasting satellite (DBS) receivers. The one-stage amplifier provides a less than 2.5-dB noise figure with more than 9.5-dB associated gain in the 11.7-12.7-GHz band. In the same frequency band, the two-stage amplifier has a less tlhan 2.8-dB noise figure with more than 16-dB associated gain. A 0.5-µm gate closely spaced electrode FET with an ion-implanted active layer is employed in the amplifier in order to achieve a low-noise figure without reducing reproducibility. The chip size is 1 mm x 0.9 mm for the one-stage amplifier, and 1.5 mm x 0.9 mm for the two-stage amplifier.     

Development of Integrated Broad-Band CMOS Low-Noise Amplifiers

This paper presents a systematic design methodology for broad-band CMOS low-noise amplifiers (LNAs). The feedback technique is proposed to attain a better design tradeoff between gain and noise. The network synthesis is adopted for the implementation of broad-band matching networks. The sloped interstage matching is used for gain compensation. A fully integrated ultra-wide-band 0.18-mum CMOS LNA is developed following the design methodology. The measured noise figure is lower than 3.8 dB from 3 to 7.5 GHz, resulting in the excellent average noise figure of 3.48 dB. Operated on a 1.8-V supply, the LNA delivers 19.1-dB power gain and dissipates 32 mW of power. The gain-bandwidth product of the UWB LNA reaches 358 GHz, the record number for the 0.18-m CMOS broad-band amplifiers. The total chip size of the CMOS UWB LNA is 1.37 times 1.19 mm².     

Monolithic Integrated Circuits for Low-Noise Centimeter-Wave Amplifiers on an AlGaN/AlN/GaN/SiC Heterostructure

The results of designing low-noise broadband amplifiers on an AlGaN/AlN/GaN HEMT heterostructure are presented. In the investigations, two variants of low-noise amplifiers executed in a two-cascade circuit are considered and fabricated. The parameters of the fabricated monolithic integrated circuits of lownoise amplifiers are given.     

Computer-Aided Design of Broad-Band and Low-Noise Microwave Amplifiers

We have found iterative optimization techniques to be very effective in the design of broad-band low-noise integrated amplifiers. This paper presents an objective function to maximize gain while minimizing ripple and noise figure. An optimization routine using this objective function is applied to the design of an L-band amplifier. The results of several runs using different objectives applied to the same circuit topology are presented to demonstrate both the flexibility of this technique and the tradeoffs involved. One of the designs was fabricated, and the measured and predicted performance agree closely over an octave bandwidth.     

Reconfigurable SiGe Low-Noise Amplifiers With Variable Miller Capacitance

A new input matching method making use of shunt-shunt feedback capacitance is introduced. Based on the new input matching method, reconfigurable SiGe low-noise amplifiers (LNAs) by varying shunt-shunt feedback capacitance are proposed. Two approaches are used to vary the shunt-shunt feedback capacitance. One approach is to switch between two different bias currents while the other is to use a series combination of a switch and a capacitor. Miniaturized fully monolithic reconfigurable SiGe LNAs without emitter degenerative inductors were realized by the above two approaches. The reconfigurable SiGe LNA achieved by switching bias currents only occupies a very small area of 355 mumtimes155 mum, excluding measurement pads. This LNA achieves an input return losses (S₁₁) of -27.6 dB, a voltage gain (A _v) of 19.8 dB, and a noise figure (NF) of 3.18 dB for 2.4-GHz band when biased at a current of 3.8 mA and can be reconfigured to obtain A_v=20.4/20.3 dB, S₁₁=-47.1/-24.6 dB and NF=3.42/3.21 dB for 5.2/5.7-GHz band when bias current is switched to 3 mA. In addition, a 2.4/4.9/5.2/5.7-GHz reconfigurable SiGe LNAs for WLAN applications, whose variable shunt-shunt feedback capacitance is controlled by a switch and a capacitor, was also realized     

Low-Noise and Linear FET Amplifiers for Satellite Communications

FET amplifiers with ambient noise figures as low as 4.8 dB at 12 GHz, 35-dB gain, and intercept points as high as +28 dBm have been developed for use in communications satellites. Predicted mean time to failure is in excess of 10/sup 6/ h.     

硅基双极低噪声放大器的能量注入损伤与机理

针对Si基双极型低噪声放大器(LNA),用脉冲调制150MHz射频信号在其输入端进行了能量注入实验,研究结果表明Si基LNA的噪声系数和增益特性都足注人能最的敏感参数.样品解削和电路仿真显示能量作用使LNA内部晶体管出现基极/发射极金属化损伤,基极金.半接触电阻增大导致了LNA噪声系数增大,而Si基双极器件hFE随时间正向漂移损伤模式使LNA增益随注入能量的增加而增大.研究表明,由于能量作用下损伤效应的复杂性,以往可靠性研究中单纯采用增益的变化来衡量器件与电路的损伤效应的方法是不全面的.     

硅基双极低噪声放大器的能量注入损伤与机理

针对Si基双极型低噪声放大器(LNA),用脉冲调制150MHz射频信号在其输入端进行了能量注入实验,研究结果表明Si基LNA的噪声系数和增益特性都是注入能量的敏感参数. 样品解剖和电路仿真显示能量作用使LNA内部晶体管出现基极/发射极金属化损伤,基极金-半接触电阻增大导致了LNA噪声系数增大,而Si基双极器件hFE随时间正向漂移损伤模式使LNA增益随注入能量的增加而增大. 研究表明,由于能量作用下损伤效应的复杂性,以往可靠性研究中单纯采用增益的变化来衡量器件与电路的损伤效应的方法是不全面的.     

Analysis and Design of Two Low-Power Ultra-Wideband CMOS Low-Noise Amplifiers With Out-Band Rejection

Two 3–5-GHz low-power ultra-wideband (UWB) low-noise amplifiers (LNAs) with out-band rejection function using 0.18- $mu{hbox{m}}$ CMOS technology are presented. Due to the Federal Communications Commission's stringent power-emission limitation at the transmitter, the received signal power in the UWB system is smaller than those of the close narrowband interferers such as the IEEE 802.11 a/b/g wireless local area network, and the 1.8-GHz digital cellular service/global system for mobile communications. Therefore, we proposed a wideband input network with out-band rejection capability to suppress the out-band properties for our first UWB LNA. Moreover, a feedback structure and dual-band notch filter with low-power active inductors will further attenuate the out-band interferers without deteriorating the input matching bandwidth in the second UWB LNA. The 55/48/45 dB maximum rejections at 1.8/2.4/5.2 GHz, a power gain of 15 dB, and 3.5-dB minimum noise figure can be measured while consuming a dc power of only 5 mW.      

Design of Microwave GaAs MESFET's for Broad-Band Low-Noise Amplifiers

As a basis for designing GaAs MESFET's for broad-band low-noise amplifiers, the fundamental relationships between basic device parameters, and two-port noise parameters are investigated in a semiempirical manner. A set of four noise parameters are shown as simple functions of equivalent circuit elements of a GaAs MESFET. Each element is then expressed in a simple analytical form with the geometrical and material parameters of this device. Thus practical expressions for the four noise parameters are developed in terms of the geometrical and material parameters. Among the four noise parameters, the minimum noise figure F/sub min/, and equivalent noise resistance R/sub n/, are considered crucial for broad-band Iow-noise amplifiers. A low R/sub n/ corresponds to less sensitivity to input rnismatch, and can be obtained with a short heavily doped thin active channel. Such a high channel doping-to-thickness (N/a) ratio has a potential of producing high power gain, but is contradictory to obtaining a low F/min/. Therefore, a compromise in choosing N and a is necessary for best overall amplifier performance. Four numerical examples are given to show optimization processes.     

GaAsFET Mount Structure Design for 30-GHz-Band Low-Noise Amplifiers

This paper describes a GaAsFET mount design method for 30-GHz-band low-noise reflection-type amplifiers with the metal wall as a feedback circuit. Two examples of 30-GHz-band low-noise amplifiers are described; one with wide-band response and the other with high-gain response. The wide-band amplifier has 13-dB gain and 8.5-dB noise figure in the frequency range from 27.5 GHz to 29.1 GHz. The high gain amplifier has 15-dB gain and 9-dB noise figure in the frequency range from 27.7 GHz to 28.7 GHz. These results demonstrate the utility of this design approach.     

Low-Noise, Low Power Dissipation GaAs Monolithic Broad-Band Amplifiers

Low-noise, low dc power dissipation GaAs monolithic amplifiers have been developed for use in VHF-UHF mobile radio systems. The developed amplifiers have two-stage constuction, where gate width for the first stage is 1000 µm, and for the second stage is 500 pm. Using this circuit configuration, both noise figure and bandwidth have been improved. To maintain the uniformity for the ion-implanted active layers and to reduce gate-source resistance R/sub S/ and gate-drain resistance R/sub D/, the "closely spaced electrode FET" was adopted. The FET enables low drain voltage operation, resulting in low dc power dissipation. The developed amplifier for the FET threshold voltage VT= --0.6 V provides a 3-dB noise figure, less than 170-mW dc power dissipation, 9-MHz-3.9-GHz bandwidth with 16-dB gain. It can operate under a unipolar power source. When external choke inductors were introduced for the amplifier, 120-mW dc power dissipation has been achieved. It has also been demonstrated that the amplifier for V/sub T/= --0.6V, which is inferior to the amplifier for VT= -2.7V regarding gain-bandwidth product and power efficiency under the same dc power dissipation, however, has an acceptable performance for use in the mobile radio systems.     

Low-Noise Design of Microwave Transistor Amplifiers (Short Papers)

Parameters are derived for circles of constant overall noise figure on the source admittance plane of a preamplifier cascaded with a noisy main amplifier. It is shown that the noise figure and noise measure of an amplifier can be expressed in terms of the scattering parameters of a lossless two-port network connected at the input of the amplifier. Examples are given which demonstrate how this network can be synthesized to meet amplifier noise specifications.     

低电压低功耗CMOS射频低噪声放大器的研究进展

由于无线移动终端重量、体积以及成本等各方面的限制，电路必须满足低电压、低功耗的要求。在CMOS射频低噪声放大器中，如何在满足性能指标要求的同时降低电源电压和功耗，已成为当前研究的热点。文章综述了几种降低CMOS低噪声放大器电源电压和功耗的方法，讨论了一些相关的设计问题。最后，展望了低电压、低功耗CMOS低噪声放大器的未来发展趋势。