1200 V常开型4H-SiC VJFET

用沟槽和离子注入方法在自主外延的4H导通型碳化硅晶圆上研制了垂直沟道结型场效应晶体管(VJFET).在栅电压V<,G>=-10 V时阻断电压达到1 200 V;在V<,G>=2.5 V,V<,D>=2V时的电流密度为395 A/cm<'2>,相应的比导通电阻为5.06 mΩ·cm<'2>.分析发现欧姆接触电阻是导通电阻...     

The accumulation-mode field-effect transistor: a new ultralowon-resistance MOSFET

An ultralow specific on-resistance, vertical channel, power MOSFET structure, based on current conduction via an accumulation layer formed on the surface of a trench (UMOS) gate structure, is described. Two-dimensional numerical simulations and experimental results have been obtained, demonstrating that a specific on-resistance approaching 100 μΩ-cm² can be obtained for a silicon device capable of blocking 25 V     

High-voltage accumulation-layer UMOSFET's in 4H-SiC

A novel silicon carbide UMOSFET structure is reported. This device incorporates two new features: a self-aligned p-type implantation in the bottom of the trench that reduces the electric field in the trench oxide, and an n-type epilayer under the p-base to promote lateral current spreading into the drift region. This UMOS structure is capable of supporting the full blocking voltage of the pn junction while keeping the electric field in the gate oxide below 4 MV/cm. An accumulation channel is formed on the sidewalls of the trench by epigrowth, and the gate oxide is produced by a polysilicon oxidation process, resulting in a uniform oxide thickness over both the sidewalls and bottom of the trench. The fabricated 4H-SiC devices have a blocking voltage of 1400 V (10 μm drift region), a specific on-resistance of 15.7 mΩ-cm ² at room temperature, and a gate oxide field of 3 MV/cm     

A low on-resistance, high-current GaAs power VFET

We have developed a new fabrication process for GaAs VFETs that results in excellent performance in a 10 A prototype designed for switching in low voltage synchronous rectifier applications. The new fabrication process uses a buried carbon-doped GaAs gate structure for the gate electrodes and an epitaxial overgrowth step. We have demonstrated 10 A devices with 3.5 cm of gate width and 1.5 mohm of on-resistance (specific on-resistance of 84 μohm-cm²). The device required a 0.5 μm channel etched between 0.5 μm gates placing stringent requirements on the gate side wall etch profile and epitaxial doping uniformity     

High-performance vertical-power DMOSFETs with selectively silicidedgate and source regions

A power FET (field-effect transistor) structure with selectively silicided gate and source region is described. This structure simultaneously lowers the gate sheet-resistance and the source contact resistance. The gate-source isolation was provided by plasma etching conformally deposited chemical vapor deposition (CVD) oxide using a photoresist mask. This structure has resulted in an order of magnitude improvement in the gate sheet resistance and about 25% improvements in the device's on-resistance (the resistance when conducting in the on-state) compared to previously reported nonsilicided conventional power FETs. Extremely low-resistance Al-TiW-TiSi₂ metallurgy with in situ sputter etching of the silicide surface prior to TiW deposition contributed to the reduction in the on-state resistance. Vertical-power DMOSFETs (double-diffused MOSFET) fabricated using this technology have a specific on-resistance of 0.53 Ω cm² for devices capable of blocking 50 V in the off state     

1.1 kV 4H-SiC power UMOSFETs

Silicon Carbide (4H-SiC), power UMOSFETs were fabricated and characterized from room temperature to 200°C. The devices had a 12-μm thick lightly doped n-type drift layer, and a nominal channel length of 4 μm. When tested under Fluorinert^TM at room temperature, blocking voltages ranged from 1.0 kV to 1.2 kV. Effective channel mobility ranged from 1.5 cm²/V.s at room temperature with a gate bias of 32 V (3.5 MV/cm) up to 7 cm²/V.s at 100°C with an applied gate bias of 26 V (2.9 MV/cm). Specific on-resistance (R_on,sp) was calculated to be as low as 74 mΩ.cm² at 100°C under the same gate bias     

High channel mobility in normally-off 4H-SiC buried channel MOSFETs

We have fabricated buried channel (BC) MOSFETs with a thermally grown gate oxide in 4H-SiC. The gate oxide was prepared by dry oxidation with wet reoxidation. The BC region was formed by nitrogen ion implantation at room temperature followed by annealing at 1500°C. The optimum doping depth of the BC region has been investigated. For a nitrogen concentration of 1×10¹⁷ cm^-3, the optimum depth was found to be 0.2 μm. Under this condition, a channel mobility of 140 cm²/Vs was achieved with a threshold voltage of 0.3 V. This channel mobility is the highest reported so far for a normally-off 4H-SiC MOSFET with a thermally grown gate oxide     

Improved high-voltage lateral RESURF MOSFETs in 4H-SiC

High-voltage lateral RESURF metal oxide semiconductor field effect transistors (MOSFETs) in 4H-SiC have been experimentally demonstrated, that block 900 V with a specific on-resistance of 0.5 Ω-cm² . The RESURF dose in 4H-SiC to maximize the avalanche breakdown voltage is almost an order of magnitude higher than that of silicon; however this high RESURF dose leads to oxide breakdown and reliability concerns in thin (100-200 nm) gate oxide devices due to high electric field (>3-4 MV/cm) in the oxide. Lighter RESURF doses and/or thicker gate oxides are required in SiC lateral MOSFETs to achieve highest breakdown voltage capability     

Experimental Demonstration of Novel High-Voltage Epilayer RESURF GaN MOSFET

We report on the experimental demonstration of a novel n-channel GaN epilayer RESURF GaN MOSFET with good tradeoff between breakdown voltage and specific on-resistance for the first time. Device with 4-mum channel length and 16-mum RESURF length has breakdown voltage up to 730 V with specific on-resistance 34 mOmegamiddotcm² (V_G - V_T = 20 V), best reported to date.     

A novel simplified process for fabricating a very high densityp-channel trench gate power MOSFET

A novel simplified fabrication method of a very high density p-channel trench gate power MOSFET using four mask layers and nitride/TEOS sidewall spacers is realized. The proposed process showed improved on-resistance characteristics of the device with increasing cell density and the cost-effective production capability due to the lesser number of processing steps. By using this process technique, a remarkably increased high density (100 Mcell/inch²) trench gate power MOSFET with a cell pitch of 2.5 μm could be effectively realized. The fabricated device had a low specific on-resistance of 1.1 mΩ-cm² with a breakdown voltage of -36 V     

An 1800 V triple implanted vertical 6H-SiC MOSFET

6H silicon carbide vertical power MOSFETs with a blocking voltage of 1800 V have been fabricated. Applying a novel processing scheme, n ⁺ source regions, p-base regions and p-wells have been fabricated by three different ion implantation steps. Our SiC triple ion implanted MOSFETs have a lateral channel and a planar polysilicon gate electrode. The 1800 V blocking voltage of the devices is due to the avalanche breakdown of the reverse diode. The reverse current density is well below 200 μA/cm² for drain source voltages up to 90% of the breakdown voltage. The MOSFETs are normally off showing a threshold voltage of 2.7 V. The active area of 0.48 mm² delivers a forward drain current of 0.3 A at Y_GS=10 V and V _DS=8 V. The specific on resistance was determined to 82 mΩdcm² at 50 mV drain source voltage and at V_GS =10 V which corresponds to an uppermost acceptable oxide field strength of about 2.7 MV/cm. This specific on resistance is an order of magnitude lower than silicon DMOSFET's of the same blocking capability could offer     

Thin-film quasi-SOI power MOSFET fabricated by reversed siliconwafer direct bonding

A quasi-SOI power MOSFET has been fabricated by reversed silicon wafer direct bonding. In this power MOSFET, the buried oxide under the channel and source regions is removed and the channel region is directly connected to the source body contact electrode to reduce the base resistance of the parasitic npn bipolar transistor. The quasi-SOI power MOSFET can suppress the parasitic bipolar action and shows lower specific on-resistance than that of the conventional SOI power MOSFET. The fabricated chip level quasi-SOI power MOSFET shows the specific on-resistance of 86 mΩ·mm² and on-state breakdown voltage of 30 V     

An implanted-emitter 4H-SiC bipolar transistor with high currentgain

An epi-base, implanted-emitter, npn bipolar transistor which showed a maximum common emitter current gain (β) of ~40, the highest current gain reported for BJT in any polytype of SiC has been experimentally demonstrated in 4H-SiC. The forward drop was ~1 V at forward current density of 50 A/cm². The current gain decreases hence specific on-resistance increases with increasing temperature. The negative temperature coefficient of β makes the device attractive for paralleling and for preventing thermal runaways     

SiC devices: physics and numerical simulation

The important material parameters for 6H silicon carbide (6H-SiC) are extracted from the literature and implemented into the 2-D device simulation programs PISCES and BREAKDOWN and into the 1-D program OSSI Simulations of 6H-SiC p-n junctions show the possibility to operate corresponding devices at temperatures up to 1000 K thanks to their low reverse current densities. Comparison of a 6H-SiC 1200 V p-n^--n⁺ diode with a corresponding silicon (Si) diode shows the higher switching performance of the 6H-SiC diode, while the forward power loss is somewhat higher than in Si due to the higher built-in voltage of the 6H-SiC p-n junction. This disadvantage can be avoided by a 6H-SiC Schottky diode. The on-resistances of Si, 3C-SiC, and 6H-SiC vertical power MOSFET's are compared by analytical calculations. At room temperature, such SiC MOSFET's can operate up to blocking capabilities of 5000 V with an on-resistance below 0.1 Ωcm², while Si MOSFET's are limited to below 500 V. This is checked by calculating the characteristics of a 6H-SiC 1200 V MOSFET with PISCES. In the voltage region below 200 V, Si is superior due to its higher mobility and lower threshold voltage. Electric fields in the order of 4×10⁶ V/cm occur in the gate oxide of the mentioned 6H-SiC MOSFET as well as in a field plate oxide used to passivate its planar junction. To investigate the high frequency performance of SiC devices, a heterobipolartransistor with a 6H-SiC emitter is considered. Base and collector are assumed to be out of 3C-SiC. Frequencies up to 10 GHz with a very high output power are obtained on the basis of analytical considerations     

1800 V NPN bipolar junction transistors in 4H-SiC

The first high voltage npn bipolar junction transistors (BJTs) in 4H-SiC have been demonstrated. The BJTs were able to block 1800 V in common emitter mode and showed a peak current gain of 20 and an on-resistance of 10.8 mΩ·cm² at room temperature (I_C=2.7 A @ V_CE=2 V for a 1 mm×1.4 mm active area), which outperforms all SiC power switching devices reported to date. Temperature-stable current gain was observed for these devices. This is due to the higher percent ionization of the deep level acceptor atoms in the base region at elevated temperatures, which offsets the effects of increased minority carrier lifetime at high temperatures. These transistors show a positive temperature coefficient in the on-resistance characteristics, which will enable easy paralleling of the devices     

Recessed-gate structure approach toward normally off high-Voltage AlGaN/GaN HEMT for power electronics applications

A recessed-gate structure has been studied with a view to realizing normally off operation of high-voltage AlGaN/GaN high-electron mobility transistors (HEMTs) for power electronics applications. The recessed-gate structure is very attractive for realizing normally off high-voltage AlGaN/GaN HEMTs because the gate threshold voltage can be controlled by the etching depth of the recess without significant increase in on-resistance characteristics. With this structure the threshold voltage can be increased with the reduction of two-dimensional electron gas (2DEG) density only under the gate electrode without reduction of 2DEG density in the other channel regions such as the channel between drain and gate. The threshold-voltage increase was experimentally demonstrated. The threshold voltage of fabricated recessed-gate device increased to -0.14 V while the threshold voltage without the recessed-gate structure was about -4 V. The specific on-resistance of the device was maintained as low as 4 m/spl Omega//spl middot/cm/sup 2/ and the breakdown voltage was 435 V. The on-resistance and the breakdown voltage tradeoff characteristics were the same as those of normally on devices. From the viewpoint of device design, the on-resistance for the normally off device was modeled using the relationship between the AlGaN layer thickness under the gate electrode and the 2DEG density. It is found that the MIS gate structure and the recess etching without the offset region between recess edge and gate electrode will further improve the on-resistance. The simulation results show the possibility of the on-resistance below 1 m/spl Omega//spl middot/cm/sup 2/ for normally off AlGaN/GaN HEMTs operating at several hundred volts with threshold voltage up to +1 V.     

High voltage 4H-SiC Schottky barrier diodes

Characteristics of 4H-SiC Schottky barrier diodes with breakdown voltages up to 1000 V are reported for the first time. The diodes showed excellent forward I-V characteristics, with a forward voltage drop of 1.06 V at an on-state current density of 100 A/cm². The specific on-resistance for these diodes was found to be low (2×10 ^-3 Ω-cm² at room temperature) and showed a T ^1.6 variation with temperature. Titanium Schottky barrier height was determined to be 0.99 eV independent of the temperature. The breakdown voltage of the diodes was found to decrease with temperature     

Silicon Carbide Power MOSFET Model and Parameter Extraction Sequence

A compact circuit simulator model is used to describe the performance of a 2-kV, 5-A 4-H silicon carbide (SiC) power DiMOSFET and to perform a detailed comparison with the performance of a widely used 400-V, 5-A Si power MOSFET. The model's channel current expressions are unique in that they include the channel regions at the corners of the square or hexagonal cells that turn on at lower gate voltages and the enhanced linear region transconductance due to diffusion in the nonuniformly doped channel. It is shown that the model accurately describes the static and dynamic performance of both the Si and SiC devices and that the diffusion-enhanced channel conductance is essential to describe the SiC DiMOSFET on-state characteristics. The detailed device comparisons reveal that both the on-state performance and switching performance at 25degC are similar between the 400-V Si and 2-kV SiC MOSFETs, with the exception that the SiC device requires twice the gate drive voltage. The main difference between the devices is that the SiC has a five times higher voltage rating without an increase in the specific on-resistance. At higher temperatures (above 100degC), the Si device has a severe reduction in conduction capability, whereas the SiC on-resistance is only minimally affected     

3100 V, asymmetrical, gate turn-off (GTO) thyristors in 4H-SiC

A 2-mm×2-mm, 4H-SiC, asymmetrical npnp gate turn-off (GTO) thyristor with a blocking voltage of 3100 V and a forward current of 12 A is reported. This is the highest reported power handling capability of 37 kW for a single device in SiC. The 5-epilayer structure utilized a blocking layer that was 50 μm thick, p-type, doped at about 7-9×10¹⁴ cm^-3. The devices were terminated with a single zone junction termination extension (JTE) region formed by ion-implantation of nitrogen at 650°C. The device was able to reliably turn-on and turn-off 20 A (500 A/cm²) of anode current with a turn-on gain (I_K/I_{G, on}) of 20 and a turn-off gain (I_K/I_{G, off}) of 3.3     

Nitrogen Implantation to Improve Electron Channel Mobility in 4H-SiC MOSFET

Normally off 4H-SiC MOSFET devices have been fabricated on a p-type semiconductor and electrically characterized at different temperatures. A gate oxide obtained by nitrogen ion implantation performed before the thermal oxidation of SiC has been implemented in n-channel MOSFET technology. Two samples with a nitrogen concentration at the SiO₂/SiC interface of 5 X 10¹⁸ and 1.5 X 10¹⁹ cm^-3 and one unimplanted sample have been manufactured. The sample with the highest N concentration at the interface presents the highest channel mobility and the lowest threshold voltage. For increasing temperature, in all the samples, the threshold voltage decreases, and the electron channel mobility increases. The latter case attains a maximum value of about 40 cm²/V ldr s at 200degC for the sample with the highest N concentration. These trends are explained by the reduction of interface electron traps in the upper half of the band gap toward the conduction band edge. These results demonstrate that N implantation can be effectively used to improve the electrical performances of an n-type surface channel 4H-SiC MOSFET.