Si bipolar 14 Gb/s 1:4-demultiplexer IC for system applications

A 1:4-demultiplexer IC meeting the essential requirements for lightwave communication systems has been designed based on a 21 GHz f _T 0.4 μm Si bipolar process. The circuit provides features such as bit-rotation control, clock enable control, outputs aligned in time, and phase aligner for clock signals. It operates up to 14 Gb/s (14 GHz) with a phase margin of ⩾250°. The power consumption is 2 W with a -4.5 V supply. 1:16-demultiplexer operation is demonstrated on the basis of 1:4-demultiplexer IC's at 10 Gb/s     

A 12.5 Gb/s Si bipolar IC for PRBS generation and bit errordetection up to 25 Gb/s

This paper describes a Si bipolar IC which features PRBS generation, bit error detection, (de-) scrambling, and trigger derivation up to 12.5 Gb/s. The sequence length is switchable between 2 ¹¹-1 and 2¹⁵-1 b. Two input/output channels are provided which allow PRBS testing up to 25 Gb/s with one external MUX/DMUX. The 3×4 mm², 1377 transistor chip uses 0.4 μm emitter 25-GHz-f_T single-poly self-aligned Si bipolar technology and dissipates 4.6 W from a single -5 V supply     

Silicon bipolar chipset for SONET/SDH 10 Gb/s fiber-opticcommunication links

High-speed multiplexers, demultiplexers, frequency dividers, mixers, and amplifiers are key electronic components in high-speed fiber-optic communications systems such as SONET/SDH. In this paper, we present several important digital and analog integrated circuits (IC) which have been developed for use in SONET/SDH 10 Gb/s optical communication links. The circuits have been fabricated in MOSAIC 5E, an advanced silicon bipolar technology (f_T=26 GHz). The resulting chipset which amounts to a total of 10 IC's consists of multiplexers, demultiplexers, a regenerative frequency divider (2:1), a dual output limiting amplifier, and two different types of mixers for clock extraction. Specifically, the design and performance of these IC's and a hybrid clock recovery module are discussed. The high performance and potential low cost of this research chipset show that advanced silicon bipolar circuit technology can play an important role in future multigigabit fiber-optic communication systems     

Design of a low-power 10 Gb/s Si bipolar 1:16-demultiplexer IC

The design of a low-power Si bipolar 1:16-demultiplexer IC built of 1:4-demultiplexer subcomponents for 10 Gb/s (STM-64) is described. The 1:4-demultiplexers feature an architecture with low component count. Special latches controlled by two clock voltages are used. The 1:16-demultiplexer operates up to 12.5 Gb/s with a power dissipation of only 1.5 W at a single power supply voltage of -3 V     

A Si bipolar phase and frequency detector IC for clock extractionup to 8 Gb/s

A phase and frequency detector IC is presented that operates up to an NRZ bit rate of 8 Gb/s. The IC comprises a phase detector (PD), a quadrature phase detector (QPD), and frequency detector (FD). In the PD and QPD the VCO signal and the quadrature VCO signal are sampled by the NRZ input signal. The two beat notes provided by this operation are subsequently processed in the FD. The superposition of the FD output and the PD output signals are then fed into a passive loop filter (lag/lead filter). The loop filter and the VCO are external components. The measured pull-in range is >±100 MHz at 8 Gb/s. The measured r.m.s. time jitter of the extracted clock is less than 1.9 ps for a pseudorandom bit sequence (PRBS) length of 2²³-1. A 0.9-μm 12-GHz f_T silicon bipolar process was used to fabricate the chip with a total power consumption of 1.4 W     

A 12 Gb/s Si bipolar 4:1-multiplexer IC for SDH systems

The 4:1-multiplexer reported here is based on a 21 GHz f_T 0.4 μm silicon bipolar technology and operates up to 12 Gb/s. For facilitating system applications, the input signals are aligned in phase and retiming of the output signal is provided. A phase control circuit permits the choice of the optimum clock phase for the first and the second multiplexer stages; an internal delay line is not necessary. The 4:1-multiplexer consumes about 1.8 W with a single supply voltage of -4.5 V     

PRBS generation and error detection above 10 Gb/s using amonolithic Si bipolar IC

This paper describes the application of a monolithic Si bipolar IC to serve as a single-chip measurement instrument for pseudo-random binary sequence (PRBS) generation, bit error detection, de-scrambling, and trigger derivation up to 12.5 Gb/s. The package interconnect problem of high I/O count multi-Gb/s IC's is addressed. The paper presents a packaging solution with improved ground contact and odd-mode controlled impedance differential microstrip transmission lines. A method for phase synchronization of multiple PRBS generators is proposed and its feasibility is demonstrated by measurement results     

A CMOS IC for Gb/s Viterbi decoding: system design and VLSIimplementation

At present, the Viterbi algorithm (VA) is widely used in communication systems for decoding and equalization. The achievable speed of conventional Viterbi decoders (VD's) is limited by the inherent nonlinear add-compare-select (ACS) recursion. The aim of this paper is to describe system design and VLSI implementation of a complex system of fabricated ASIC's for high speed Viterbi decoding using the “minimized method” (MM) parallelized VA. We particularly emphasize the interaction between system design, architecture and VLSI implementation as well as system partitioning issues and the resulting requirements for the system design flow. Our design objectives were 1) to achieve the same decoding performance as a conventional VD using the parallelized algorithm, 2) to achieve a speed of more than 1 Gb/s, and 3) to realize a system for this task using a single cascadable ASIC. With a minimum system configuration of four identical ASIC's produced by using 1.0 μ CMOS technology, the design objective of a decoding speed of 1.2 Gb/s is achieved. This means, compared to previous implementations of Viterbi decoders, the speed is increased by an order of magnitude     

Multiplexer/demultiplexer IC technology for 100 Gb/s fiber-optictransmission

We report a new integrated circuit for multiplexing and demultiplexing at rates of 100 Gb/s. In transistor multiplexer/demultiplexer circuits, the operating data rate is limited by transistor bandwidth. The demonstrated circuit, which uses terahertz Schottky diodes, readily attains the necessary bandwidths. The IC, based in the diode nonlinear-transmission line (NLTL) technology, consists of an array of four sample-hold gates driven by NLTL strobe generators. To permit use in multiplexing, the sample-hold gates use a six-diode configuration with 150 GHz output bandwidth. Initial measurements with simple data patterns at 104 Gb/s are demonstrated     

Silicon bipolar laser and line driver IC with symmetrical output pulse shape operating up to 12 Gbit/s

A silicon bipolar laser and line driver IC with an outstanding symmetry of the (single-ended) output pulse shape is presented. The pulse shape can be optimally adjusted via only two external potentiometers, independent of operating speed and output current range. The circuit, fabricated in a 0.8 mu m self aligned double-polysilicon technology, operates up to 12 Gbit/s.<>     

Silicon bipolar IC for PRBS testing generates adjustable bit ratesup to 25 Gbit/s

For the first time, a completely integrated pseudo-random pattern generator providing adjustable bit rates up to at least 25 Gbit/s without additional external multiplexing is presented. The sequence length is 2ⁿ-1. The application of the monolithic Si bipolar IC serves as a single chip measurement instrument for pseudo-random binary sequence (PRBS) generation required for the characterisation and development of high-speed components used in future optical fibre communication systems. Only three external microwave components are needed for operation: a clock generator, a power divider and a phase shifter. The chip is realised in an advanced implanted base silicon bipolar technology     

46 Gb/s DEMUX, 50 Gb/s MUX, and 30 GHz static frequency divider insilicon bipolar technology

High-speed multiplexers, demultiplexers, and static frequency dividers are key electronic components in future optical broadband communication systems. In this paper we present a 50 Gb/s multiplexer, a 46 Gb/s demultiplexer, and a 30 GHz static frequency divider. The IC's were fabricated in a self-aligning double-polysilicon bipolar technology using state-of-the-art production process modules. The achieved results are record speeds not only for silicon, but, except for the static divider, for all semiconductor technologies. The high performance of this chipset shows that circuits in silicon bipolar technology will play an important role in future multigigabit-per-second fiber-optic communication systems, at data rates of 20 Gb/s or even at 40 Gb/s     

Silicon bipolar 1:16-demultiplexer for 10 Gbit/s fibre opticcommunication system

A 1:16-demultiplexer based on silicon bipolar 1:4-demultiplexer ICs, which include all requirements for system applications, has been designed and tested. The authors report the design of the 1:4-demultiplexer, which operates up to 14 Gbit/s, and experimental results for the 1:16-demultiplexer at 10 Gbit/s     

10Gb/s光调制器InGaP/GaAs HBT驱动电路的研制

采用自行研发的4英寸InGaP/GaAs HBT技术,设计和制造了10Gb/s光调制器驱动电路.该驱动电路的输出电压摆幅达到3V_pp,上升时间为34.2ps(20~80%),下降时间为37.8ps(20~80%),输入端的阻抗匹配良好(S11=-12.3dB@10GHz),达到10Gb/s光通信系统(SONET OC-192,SDH STM-64)的要求.整个驱动电路采用-5.2V的单电源供电,总功耗为1.3W,芯片面积为2.01×1.38mm².     

Noise characterization of a neodymium-doped fluoride fiberamplifier and its performance in a 2.4 Gb/s system

An analysis of noise in a neodymium-doped single-mode fluoride fiber amplifier for the 1300-nm telecommunications window has been carried out both theoretically and experimentally. The presence of signal-excited state absorptions, particularly at the shorter wavelength end of the gain transition, has been shown to increase the noise figure and, hence, degrade the overall system performance. However, when the amplifier was used as a power amplifier in a 2.4-Gb/s laboratory system experiment, no degradation at a BER of 10^-9 could be observed     

A 10-Gb/s silicon bipolar IC for PRBS testing

A 10 Gb/s silicon bipolar IC for pseudorandom binary sequence (PRBS) testing was fabricated and tested. The IC features PRBS generation of the sequences of length 2¹⁵-1 and 2²³-1 b up to 10 Gb/s according to CCITT recommendations. Furthermore, the IC is capable of analyzing PRB sequences of the same length and generation polynomials so that a full test of components is possible. In addition, a new PRBS test word synchronization can be provided between two chips for external multiplexing of the sequences up to 40 Gb/s. The IC can be connected to a standard PC, so evaluation of the error test data can be performed in a flexible way. The IC was fabricated with the HP25 process of Hewlett Packard company, the chip size is 32 mm², and it consumes 6.2 W at the nominal supply voltage of -5 V     

2.5 V 43–45 Gb/s CDR Circuit and 55 Gb/s PRBS Generator in SiGe Using a Low-Voltage Logic Family

An alternative design approach for implementing high-speed digital and mixed-signal circuits is proposed. It is based on a family of low-voltage logic gates with reduced transistor stacking compared to series-gated emitter-coupled logic. It includes a latch, an xor gate, and a MUX with mutually compatible interfaces. Topologies and characteristics of the individual gates are discussed. Closed-form propagation delay expressions are introduced and verified with simulations. The proposed design style was used to implement a 43–45 Gb/s CDR circuit with a 600MHz locking range and a 55 Gb/s PRBS generator with a$2^7!-!1$sequence length. The circuits were fabricated in a SiGe BiCMOS technology with$f _T = 120~hboxGHz$. Corresponding measurement results validate the proposed design style and establish it as a viable alternative to emitter-coupled logic in high-speed applications. Both circuits operate from a 2.5 V nominal power supply and consume 650 mW and 550 mW, respectively.     

用0.35μm CMOS工艺进行SDH系统中激光二极管驱动电路芯片设计

首先介绍了光纤传输系统SDH，以及构成SDH收发机的各个功能模块，然后分析了其中的激光二极管驱动器芯片的设计方法。在此基础上设计出了采用标准0.35μm CMOS工艺的工作速率高达2.5Gb/s的驱动器芯片。     

2.5-10Gb/s光发射机驱动电路HEMT IC中器件模型参数

对高速调制器驱动电路HEMTIC中器件参数进行了研究,着重讨论了HEMT器件直流参数、交流参数对外调制驱动电路特性的影响,给出了满足电路性能要求的器件参数范围;对2.5-10Gb/sPHEMTIC光驱动电路进行了计算机仿真,眼图模拟结果表明满足2.5-10Gb/s高速光纤通信系统需要.     

15 Gbit/s silicon bipolar amplifier IC using a novel mountingtechnique

A DC-coupled silicon bipolar amplifier IC, for operation in future multigigabit optical communication systems, has been fabricated using ⩾30 GHz double-polysilicon transistors. Using a novel HF connection technique for reducing the bondwire inductance, we have succeeded in the fabrication of a 14 dB gain amplifier IC, with a flatness better than ±0.5 dB, combined with a -3 dB bandwidth of 12.8 GHz. This is the highest bandwidth ever reported for a bonded amplifier circuit in any semiconductor technology