First-order PMD outage for the hinge model

System outage due to first-order polarization-mode dispersion of links obeying the hinge model is analyzed using outage maps. We find that some fraction of the wavelength-division-multiplexed fiber capacity does not meet any outage specification.     

RZ码和NRZ码的偏振模色散自适应补偿特性比较

建立了自适应偏振模色散补偿系统,利用偏振度作为反馈信号,对40 Gb/s的RZ和NRZ码分别进行了PMD补偿的数值模拟,结果显示,采用DOP作反馈信号、用二段补偿器和三段补偿器对二种码型的PMD补偿均是有效的.但由于高阶PMD的影响对NRZ码的补偿效果要优于RZ码,特别是存在偏振相关色散的影响时,对RZ码的补偿的影响在明显大于NRZ码,这说明,对于RZ码补偿偏振相关色散是必要的.     

A CMOS clock recovery circuit for 2.5-Gb/s NRZ data

This paper describes a phase-locked clock recovery circuit that operates at 2.5 Gb/s in a 0.4-μm digital CMOS technology. To achieve a high speed with low power dissipation, a two-stage ring oscillator is introduced that employs an excess phase technique to operate reliably across a wide range. A sample-and-hold phase detector is also described that combines the advantages of linear and nonlinear phase detectors. The recovered clock exhibits an rms jitter of 10.8 ps for a PRBS sequence of length 2⁷-1 and a phase noise of -80 dBc/Hz at a 5-MHz offset. The core circuit dissipates a total power of 33.5 mW from a 3.3-V supply and occupies an area of 0.8×0.4 mm²     

All-optical enhancement of clock and clock-to-data suppressionratio of NRZ data

A scheme for all-optical enhancement of clock and clock-to-data suppression ratio of nonreturn-to-zero (NRZ) data based on self-phase modulation is proposed and demonstrated. More than 3-dB clock enhancement and 11-dB clock-to-data suppression ratio enhancement has been realized by a semiconductor optical amplifier (SOA) and fiber Bragg grating (FBG) in reflection. Clock enhancement of more than 6 dB is possible using a FBG in transmission. Using this technique, all-optical clock recovery from NRZ data has been demonstrated     

All-optical clock extraction from 40-Gbit/s NRZ data using cascaded long-period fiber grating

All-optical clock extraction from a 40-Gbit/s NRZ input signal is demonstrated using a cascaded long-period fiber grating (CLPG) and a mode-locked fiber ring laser. The CLPG has a Mach–Zehnder configuration with two arms along the core and cladding regions. Using the difference in propagation delay between two arms, the non-return-to-zero (NRZ) signal is converted to the pseudo-return-to-zero (PRZ) signal. To obtain repetitive pulses as a clock signal from the PRZ signal, a ring laser with a semiconductor optical amplifier (SOA) is used. Subsequently, the measured carrier-to-noise ratio (CNR) of the PRZ and clock signals are enhanced up to 30 dB and 31 dB, respectively, compared to that of the original NRZ signal. Also, the clock signal centered at 40 GHz has a low timing jitter of <1.3 ps. It is expected that this method can be applied to high speed fiber-optic systems of >40 Gbit/s due to its small time delay between the core and cladding regions.     

PMD and chirp effects suppression in RF tone-based chromatic dispersion monitoring

We investigate the effects of polarization-mode dispersion (PMD) and chirp on radio-frequency tone-based chromatic dispersion (CD) monitoring method, and show that the PMD and chirp induce significant CD monitoring errors. We propose a CD monitoring technique to suppress these effects. Experiment results show that the CD monitoring errors induced by PMD and chirp fluctuation are greatly suppressed.     

All-optical clock recovery from 2.5 Gbit/s NRZ data using selfpulsating 1.58 mu m laser diode

For the first time, all-optical clock extraction from 2.5 Gbit/s NRZ data is demonstrated using a two contact InGaAsP semiconductor selfpulsating laser diode (SP-LD) for what the authors believe to be the first time. The saturable absorber region of the device was doped with Zn ions to reduce the carrier lifetime such that strong selfpulsations at frequencies up to 4 GHz were obtained. Injection of a 10 mu W optical data signal at a wavelength approximately 15 nm lower than the lasing wavelength was sufficient to synchronise the selfpulsations to the incoming NRZ data stream. Similar effects were seen for RZ formated data. Such all-optical clock extraction techniques will find application in future multigigabit per second optical networks and for OEIC applications.<>     

NMOS IC's for clock and data regeneration in gigabit-per-secondoptical-fiber receivers

The design and performance of two essential analog circuits in optical-fiber receivers is described. A time-interleaved decision circuit is capable of regenerating 35-mV nonreturn-to-zero (NRZ) data inputs to full logic levels at 1.1 Gb/s with 10^-11 bit error rate (BER), and a phase-locked loop (PLL) extracts the clock from a 2 ²³ long pseudorandom sequence at 1.5 Gb/s with 13-ps r.m.s. jitter. The two circuits have been implemented as 1-μm NMOS ICs, and in their core area dissipate 200 and 350 mW, respectively     

All-optical clock recovery of NRZ data at 40 Gbit/s using Fabry-Perot filter and two-section gain-coupled DFB laser

All-optical clock recovery from 40 Gbit/s non-return-to-zero (NRZ) data has been experimentally demonstrated by using a fibre-pigtailed Fabry-Perot filter and a self-pulsing two-section gain-coupled distributed feedback laser. The recovered clock has a measured root-mean-square (RMS) timing jitter of 1.2 ps. Error-free performance has been achieved in back-to-back bit error ratio (BER) tests using the optically recovered clock.     

10 Gbit/s NRZ global transmission using optically amplifiedelectronic regeneration

10 Gbit/s NRZ error-free fibre transmission over distances exceeding 400000 km is demonstrated using an optically amplified regenerator with a 160 km span. Direct modulation of a DFB laser raises the stimulated Brillouin scattering power threshold while maintaining system simplicity and robustness     

PMD补偿技术中影响射频功率反馈信号的因素

推导出了用射频功率作为反馈信息进行偏振模色散(PMD)补偿时,射频功率与光纤线路的差分群延迟(DGD)、偏振模已散补偿器的延迟时间、光功率在光纤中两个偏振主态之间功率分配比,以及补偿器的光快慢轴与光纤线路(或补偿器)快慢轴之间相对角度变化的关系。分析计算了在考虑到补偿器的光快慢轴与光纤线路有相对关系时的输出功率随其他参数变化的关系。     

MultiGbits/s data regeneration and clock recovery IC design

A regenerative data transmission system is briefly outlined. Some important aspects related to the data regeneration and the clock recovery, such as the forms, the spectra, the jitter and the measurements of the data and clock signal, are summarized. The principle and the ic realisation of dr is discussed. Optimal cr circuits are deduced. Its preprocessing part and three categories of the main processing part, i.e., with a passive filter, with a narrowband regenerative frequency divider and with a phase-locked loop, are studied in detail. All circuits discussed are designed for applications in multibitls optical transmission systems, and are mainly based on high-speed Si bipolar technologies.     

Circuit for monitoring BJT RF performance using DC measurements

A test circuit is described for on-wafer monitoring of high-frequency performance of bipolar junction transistors using only dc measurements. The test circuit includes an oscillation-amplitude detector and a high-frequency (/spl sim/3 GHz) oscillator whose minimum bias current for oscillation I/sub osc/ correlates strongly with the transistors' maximum oscillation frequency f/sub max/. Variations in the circuit's I/sub osc/ can be routinely monitored to track changes in f/sub max/ caused by process variations. Monte Carlo simulations showed a correlation coefficient of -0.79 between I/sub osc/ and f/sub max/. Variations in measured f/sub max/ intentionally introduced through layout variations were verified to be strongly correlated with I/sub osc/.     

高速时钟与数据恢复电路技术研究

本文根据数据恢复时,本地时钟与输入数据之间的相位关系及其实现方式的不同,将高速时钟与数据恢复(CDR,Clock and Data Recovery)电路技术分为三类,也即前馈相位跟踪型,反馈相位跟踪型,以及盲过采样型。进而又分别对每一类型进行了细分并分别进行了深入的剖析和比较。最后又给出了不同应用环境下,CDR技术的选择策略,并指出了CDR技术的发展趋势。本文通过对高速CDR技术详尽而又深刻的分析比较,勾勒出了一个高速CDR技术的关系及发展演化图,使读者能够对现存的高速CDR技术及其发展趋势有一个前面而又清晰的认识。     

Method for PMD vector monitoring in picosecond pulse transmissionsystems

A method and a device are proposed that allow measurement of the polarization mode dispersion (PMD) in a transmission line without data traffic interruption. The PMD vector information is extracted from the optical data signal spectrum. The method is experimentally verified by measuring of first-order PMD     

Wavelength selection for gigabits-per-second data transmission using out-of-band RF modulation

Radio frequency modulation of a multicavity laser diode may be used to precisely select lasing optical wavelength for wavelength-division multiplexing (WDM) systems. We demonstrate gigabits-per-second in-band digital data transmission with a low bit-error ratio (BER) and out-of-band radio frequency wavelength selection with -30-dB wavelength selectivity. The same device may also be used to transmit wavelength encoded digital data.     

RF interconnect for multi-gbit/s board-level clock distribution

With clock distribution of over 1 GHz, problems associated with clock skew, power consumption, and timing jitter are becoming critical for determining the processing speed of high-performance digital systems, especially for multi-processor systems. Conventional digital clock distribution interconnection has a severe power consumption problem for GHz clock distribution because of the transmission line losses, as well as exhibiting difficult signal integrity problems due to clock skew, clerk jitter and signal reflection. To overcome conventional digital clock distribution limitations, optical clock distribution techniques, based on guided-wave optics and free-space optics, have been proposed. However, the optical clock distribution is found to be bulky, hard to fabricate, and expensive, even though it has lower power consumption and excellent signal integrity properties. In this paper, a multi-Gbit/s clock distribution scheme to minimize power consumption, skew, and jitter, based on RF interconnect technology, especially for the medium clock frequency region from 200 MHz to 10 GHz, and interconnection line lengths of from 10 cm to 3 m, is proposed. A quantitative comparison is made between the guided optical, the free-space optical, the conventional digital, and the proposed RF interconnections for board-level clock distribution relative to power consumption and speed. The proposed board-level clock distribution with 32-fan-outs has successfully demonstrated less than 22-ps skew and less than 3-ps jitter at 2 GHz. The estimated power consumption of the clock link for the proposed clock distribution has been shown to be about 320 mW. Furthermore, the proposed clock receiver using the RF clock distribution scheme has demonstrated less than 2-ps dead time and 3-ps skew time     

RF and microwave phase shifter using complementary bias techniques

A novel method for the design of an RF phase shifter using a standard foundry process is described. This phase shift achieves very low and near-constant insertion loss. The proposed method uses `complementary' control techniques to keep variable parasitic resistance in a standard transistor to a minimum. Using an only single stage reflection configuration which employs N varactor diodes as a reflection terminator and M varactor diodes, a minimum insertion loss variation can be obtained. The technique is verified by measurement when N=M=1     

Over GHz low-power RF clock distribution for a multiprocessordigital system

Conventional interconnections for digital clock distribution pose a severe power consumption problem for GHz clock distribution due to transmission line losses. Therefore, we have proposed an RF clock distribution (RCD) scheme for high-speed digital applications, in particular a multiprocessor system using global clocking. This paper first reports system power and signal integrity analysis results including skew, jitter, impedance mismatch, and noise for RF clock distribution,especially in the GHz range. Based on this analysis, a novel signal integrity design methodology for RF clock distribution systems is proposed. The clock skew created by process parameter variations are modeled and predicted. The system comprises a RF clock transmitter as a clock generator, an H-tree with junction couplers as a clock distributing network and a RF receiver as a digital clock-recovery module. Flip-chip interconnections for the chip-to-substrate assembly and 0.35 μm TSMC CMOS technology for the RF clock receiver are assumed. EMI analysis for 2 GHz 16-node-board-level RF clock distribution networks is conducted using 3D full-wave EM simulation. Finally, the RCD as a low power and high performance clocking method is demonstrated using HP's Advanced Design System (ADS) simulation, considering microwave frequency interconnection models and process parameter variations. In addition, test vehicles for both 2 GHz 16-node and 5 GHz 64-node board-level RF clock distribution networks were implemented and measured using thin, low-loss, and low permittivity Rogers^Lt; RO3003 high-frequency organic substrate