A model relating wearout to breakdown in thin oxides

A model has been developed relating wearout to breakdown in thin oxides. Wearout has been described in terms of trap generation inside of the oxide during high voltage stressing prior to breakdown. Breakdown occurred locally when the local density of traps exceeded a critical value and the product of the electric field and the higher leakage currents through the traps exceeded a critical energy density. The measurement techniques needed for determining the density of high-voltage stress generated traps have been described along with the method for coupling the wearout measurements to breakdown distributions. The average trap density immediately prior to breakdown was measured to be of the order of low-10¹⁹/cm³ in 10 nm thick oxides fabricated on p-type substrates stressed with negative gate voltages. The model has been used to describe several effects observed during measurements of time-dependent-dielectric-breakdown distributions. The area dependence of breakdown distributions, the differences in the breakdown distributions during constant current and constant voltage stressing, and the multi-modal distributions often observed were simulated using the model. The model contained the provision for incorporation of weak spots in the oxide     

Properties of high-voltage stress generated traps in thin siliconoxide

It has previously been shown that trap generation inside thin oxides during high voltage stressing can be coupled to time-dependent-dielectric-breakdown distributions through the statistics linking wearout to breakdown. Since the stress-generated traps play a crucial role in the wearout/breakdown process, it is important to understand the properties of these traps. The properties of the traps in oxides with thicknesses between 2.5 nm and 22 nm have been studied, with emphasis on oxides in the 8.5-nm to 13-nm thickness range. The Coulombic scattering cross section of the traps responsible for the reduction in the tunneling current, an estimate of the spatial and energy distribution of the traps, and the charging/discharging properties of the traps have been measured. It will be shown that the measured properties of the high-voltage, stress-generated traps can be adequately described by the tunneling of electrons into and out of traps     

Correlation of stress-induced leakage current in thin oxides withtrap generation inside the oxides

Increases in pre-tunneling leakage currents in thin oxides after the oxides are subjected to high voltage stresses are correlated with the number of traps generated inside of the oxides by the high-voltage stresses. The densities of the traps are calculated using the tunneling front model and analyzing the transient currents that flowed through the oxide after removal of the stress voltage pulses. It is found that the trap distributions are relatively uniform throughout the small portion of the oxide sampled by the transient currents. The trap densities increase as the cube root of the fluence of electrons that passes through the oxide during the stress, independent of the stress polarity. The voltage dependence of the low-level pretunneling current is dependent on the sequence in which the stress voltage polarities and the low-level current measurement polarities are applied. The portion of the low-level pre-tunneling current that is not dependent on the polarity sequence is best fitted by a voltage dependence consistent with Schottky emission     

The charging and discharging of high-voltage stress-generated trapsin thin silicon oxide

Excess high-voltage stress-generated low-level leakage currents through 10 nm silicon oxides, previously described as DC currents, are shown to decay to the limit of detection given adequate observation time and, thus, have no discernible component. A physical model is presented which describes the majority of the excess low-level leakage currents in terms of the charging and discharging of traps previously generated by the high voltage stress. Excess low-level leakage currents measured with voltage pulses with polarity opposite to that of the stress voltage are found to contain an additional current component, which is explained by the transient charging and discharging of certain traps inside the oxide. Evidence is presented which suggests that an oxide trap generated by the high-voltage stress can contain either a positive or a negative charge, in addition to being neutral and that the traps are located near both oxide interfaces. All of the trap charging and discharging currents can be explained by the flow of electrons into and out of traps generated by the high voltage stress, without resorting to the flow of holes in the oxide     

Extrapolation of high-voltage stress measurements to low-voltageoperation for thin silicon-oxide films

Breakdown and wearout in MOS capacitors fabricated with 10 nm-thick silicon oxide films on p-type silicon are discussed. They have been stressed at high voltages. The high-voltage-stress-induced changes in the oxide properties are extrapolated to low operating voltages. The stress voltages ranged from -7.5 V to -14.5 V. The fluence during the stress was systematically varied front 2×10^-5 C/cm² to 6 C/cm² by varying the stress time at each voltage. The number of interface traps generated by the stress increased as the stress voltage and fluence increased. However, the interface trap generation rate decreased as the fluence increased. The trap generation rate at low operating voltages was very high, but because the current through the oxide was small, the total number of traps generated was low. The trap generation rate was proportional to the inverse square root of the fluence with a voltage dependence that decreased as the fluence increased. Extrapolation of the high-voltage-stress measurements to 5 V shows that easily detectable changes in the oxide properties would only occur after several years of 5 V operation. Extrapolation of charge-to-breakdown and time-to-breakdown data to 5 V operation indicates that breakdown would occur after hundreds of years of device operation     

衬底热空穴注入下的薄栅氧化层击穿特性

利用衬底热空穴 (SHH)注入技术 ,分别定量研究了热电子和空穴注入对薄栅氧化层击穿的影响 ,讨论了不同应力条件下的阈值电压变化 .阈值电压的漂移表明是正电荷陷入氧化层中 ,而热电子的存在是氧化层击穿的必要条件 .把阳极空穴注入模型和电子陷阱产生模型统一起来 ,提出了薄栅氧化层的击穿是与电子导致的空穴陷阱相关的 .研究结果表明薄栅氧化层击穿的限制因素依赖于注入热电子量和空穴量的平衡 .认为栅氧化层的击穿是一个两步过程 .第一步是注入的热电子打断 Si— O键 ,产生悬挂键充当空穴陷阱中心 ,第二步是空穴被陷阱俘获 ,在氧化层中产生导电通路     

衬底热空穴注入下的薄栅氧化层击穿特性

利用衬底热空穴(SHH)注入技术,分别定量研究了热电子和空穴注入对薄栅氧化层击穿的影响,讨论了不同应力条件下的阈值电压变化.阈值电压的漂移表明是正电荷陷入氧化层中,而热电子的存在是氧化层击穿的必要条件.把阳极空穴注入模型和电子陷阱产生模型统一起来,提出了薄栅氧化层的击穿是与电子导致的空穴陷阱相关的.研究结果表明薄栅氧化层击穿的限制因素依赖于注入热电子量和空穴量的平衡.认为栅氧化层的击穿是一个两步过程.第一步是注入的热电子打断Si一O键,产生悬挂键充当空穴陷阱中心,第二步是空穴被陷阱俘获,在氧化层中产生导电通路,薄栅氧化层的击穿是在注入的热电子和空穴的共同作用下发生的.     

Hole trapping and breakdown in thin SiO2

The field dependence of the hole generation rate, also known as the impact ionization coefficient α, in thin SiO2(< 20 nm) was characterized by measuring the negative flat-band shift due to hole trapping. In thicker oxides,alpha = alpha_{0}e^{-H/E}where H = 78 MV/cm for electric fields ranging from 7 to 14 MV/cm, which covers the field range from the onset of significant Fowler-Nordheim current to instant breakdown. The similar field dependences of α and charge-to-breakdown supports the model that hole generation and trapping leads to oxide wearout. Because of the fact that positive charge generation is observed for oxide voltage well below the SiO2bandgap, we propose that the generated holes arise from transition between band tails in the amorphous SiO2. It is also observed that α decreases rapidly when the applied oxide voltage is very low; thus α is a function of both oxide field and voltage in general. This suggests that ultra-thin oxide with low operating voltages might be a good candidate for high endurance E²PROM devices at very low oxide field.     

Monitoring plasma-process induced damage in thin oxide

Plasma etching and resist ashing processes cause current to flow through the thin oxide and the resultant plasma-induced damage can be simulated and modeled as damage produced by constant current electrical stress. The oxide charging current produced by plasma processing increases with the `antenna' size of the device structure. Oxide charge measurement such as CV or threshold voltage is a more sensitive technique for characterizing plasma-processing induced damage than oxide breakdown. The oxide charging current is collected only through the aluminum surfaces not covered by the photoresist during plasma processes. Although forming gas anneal can passivate the traps generated during plasma etching, subsequent Fowler-Nordheim stressing causes more traps to be generated in these devices than in devices that have not been through plasma etching. Using the measured charging current, the breakdown voltage distribution of oxides after plasma processes can be predicted accurately. Oxide shorts density of a single large test capacitor is found to be higher than that in a multiple of separated small capacitors having the same total oxide area. This would lead to overly pessimistic oxide defect data unless care is taken     

Time dependent dielectric wearout (TDDW) technique for reliabilityof ultrathin gate oxides

The degradation of ultrathin oxides is measured and characterized by the dual voltage time dependent dielectric wearout (TDDW) technique. Compared to the conventional time-dependent dielectric breakdown (TDDB) technique, a distinct breakdown can be determined at the operating voltage I-t curve. A noisy, soft prebreakdown effect occurs for 1.8-2.7 nm ultrathin oxides at earlier stress times. The different stages of wearout of 1.8-2.7 nm oxides are discussed. The wearout of oxide is defined when the gate current reaches a critical current density at the circuit operating voltage. Devices still function after the soft breakdowns occur, but are not functional after the sharp breakdown. However, application of the E model to project the dielectric lifetime shows that this is more than 20 y for thermal oxides in the ultrathin regime down to 1.8 nm     

Two types of neutral electron traps generated in the gate silicon dioxide

Electron trap generation in the gate oxide is a severe problem for the reliability of MOS devices, since it can cause stress-induced leakage current (SILC) and eventually lead to oxide breakdown. Although much effort has recently been made to understand the mechanism for the trap generation, the properties of the generated traps have received relatively less attention. The objective of this paper is to present unambiguous results, showing that two different types of neutral electron traps can be created by the same stress and to compare the properties of these two types of traps. Differences have been found in terms of their generation kinetics, trap filling, detrapping, and refilling after detrapping. The results also indicate that the energy levels of these two types of traps are different.     

Correlation of trap generation to charge-to-breakdown (Qbd): a physical-damage model of dielectric breakdown

Ultrathin gate and tunnel oxides in MOS devices are subjected to high-field stress during device operation, which degrades the oxide and eventually causes dielectric breakdown. Oxide reliability, therefore, is a key concern in technology scaling for ultra-large scale integration (ULSI). Here we provide critical new insight into oxide degradation (and consequently, reliability) by a systematic study of five technologically relevant parameters, namely, stress-current density, oxide thickness, stress temperature, charge-injection polarity (gate versus substrate), and nitridation of pure oxide. For all five parameters, a strong correlation has been observed between oxide degradation and the generation of new traps (distinct from the filling of intrinsic traps). Further, we observe that this correlation is independent of the trap polarity (positive versus negative). Based on this correlation, and based on the fundamental link between electronic properties and atomic structure, a physical-damage model of dielectric breakdown has been proposed. The concept of the physical-damage model is that the oxide suffers dielectric breakdown when physical damage due to broken bonds forms a defect-filled filamentary path in the oxide, that conducts excessive current. A good monitor of this physical damage is trap generation, which we believe is caused by physical bond breaking in the oxide and at the interface. The model has been quantified empirically by the correlation between trap generation and Q_bd     

Degradation and breakdown of thin silicon dioxide films underdynamic electrical stress

Thin oxide MOS capacitors have been subjected to dynamic voltage stresses of different characteristics (shape, amplitude and frequency) in order to analyze the transient response and the degradation of the oxide as a function of the stress parameters. The current transients observed in dynamic voltage stresses have been interpreted in terms of the charging/discharging of interface and bulk traps. As for the oxide degradation, the experimental data has been interpreted in terms of a phenomenological model previously developed for dc stresses. According to this model, the current evolution in voltage stresses is assumed to be related to the oxide wearout. The evolution of the current during bipolar voltage stresses shows the existence of two different regimes, the degradation being much faster at low frequencies than at high frequencies. In both regimes, the frequency dependence is not significant, and the change from one regime to the other takes place at a threshold frequency which depends on the oxide field. These trends are also observed in time-to-breakdown versus frequency data, thus suggesting a strong correlation between degradation and breakdown in dynamic stresses. The experimental results are discussed in terms of microscopic degradation models     

Thickness dependence of stress-induced leakage currents in siliconoxide

The thickness dependence of high-voltage stress-induced leakage currents (SILC's) has been measured in oxides with thicknesses between 5 and 11 nm. The SILC's were shown to be composed of two components: a transient component and a DC component. Both components were due to trap-assisted tunneling processes. The transient component was caused by the tunnel charging and discharging of the stress-generated traps near the two interfaces. The DC component was caused by trap-assisted tunneling completely through the oxide. The thickness, voltage, and trap density dependences of both of these components were measured. The SILC's will affect data retention in electrically erasable programmable read-only memories (EEPROM's) and the DC component was used to estimate to fundamental limitations on oxide thicknesses     

Characterization of charge trapping and high-field endurance for15-nm thermally nitrided oxides

Device-quality gate oxides have been nitrided using both rapid thermal processing and conventional furnace treatment. Charge trapping and high-field endurance including breakdown field and time-dependent dielectric breakdown, are investigated in detail. It is found that proper nitridation can eliminate positive charge accumulation in oxides, increase charge to breakdown, suppress high-field injection-induced interface state generation, and decrease the dependence of the breakdown field on the gate area as a result of the reduced density of microdefects. Experimental results show that although both the density and capture cross-section of the bulk and interface traps increased by nitridation, the combined effects of bulk and interface traps induced by high-field injection can improve the stability of the flatband voltage. For lightly nitrided oxides, the trap generation rate is greatly decreased as compared with the as-grown oxide. Not only are the density and capture cross-section of the traps affected by nitridation, but also the locations of the trapped-charge centroids are changed. The experimental results for postnitridation annealing suggest that these property modifications most likely result from nitridation-induced structural changes rather than hydrogenation alone     

Characterization of various stress-induced oxide traps in MOSFET'sby using a subthreshold transient current technique

An oxide trap characterization technique by measuring a subthreshold current transient is developed. This technique consists of two alternating phases, an oxide charge detrapping phase and a subthreshold current measurement phase. An analytical model relating a subthreshold current transient to oxide charge tunnel detrapping is derived. By taking advantage of a large difference between interface trap and oxide trap time-constants, this transient technique allows the characterization of oxide traps separately in the presence of interface traps. Oxide traps created by three different stress methods, channel Fowler-Nordheim (F-N) stress, hot electron stress and hot hole stress, are characterized. By varying the gate bias in the detrapping phase and the drain bias in the measurement phase, the field dependence of oxide charge detrapping and the spatial distribution of oxide traps in the channel direction can be obtained. Our results show that 1) the subthreshold current transient follows a power-law time-dependence at a small charge detrapping field, 2) while the hot hole stress generated oxide traps have a largest density, their spatial distribution in the channel is narrowest as compared to the other two stresses, and 3) the hot hole stress created oxide charges exhibit a shortest effective detrapping time-constant     

Hole trapping and trap generation in the gate silicon dioxide

Oxide breakdown has been proposed to be a limiting factor for future generation CMOS. The breakdown is caused by defect generation in the oxide. Although electron trap generation has received much attention, there is little information available on the hole trap generation. The relatively high potential barrier for holes at the oxide/Si interface makes it difficult to achieve a high level of hole injection. Most previous work was limited to an injection level Q_inj of 10¹⁴ cm^-2. In this paper, we investigate the hole trapping and trap generation when Q_inj reaches the order of 10¹⁸ cm^-2. When Q_inj <10¹⁵ cm^-2, the trapping is dominated by the as-grown traps. As Q_inj increases further, however, it is found that the generation of new traps controls the trapping. The trap generation does not saturate up to the oxide breakdown. The trapping kinetics for both the as-grown and the generated traps is studied. The relationship between the density of generated traps and the Q_inj is explored. Attention is paid to how the trapping and trap generation depends on the distance from the interface. In contrast to the uniform generation of electron traps across the oxide, we found that the hole trap generation was not uniform and it moved away from the interface as Q_inj increased     

Time-dependent dielectric wearout technique with temperature effect for reliability test of ultrathin (<2.0 nm) single layer and dual layer gate oxides

Ultrathin gate oxide is essential for low supply voltage and high drive current for ULSI devices. The continuous scaling of oxide thickness has been a challenge on reliability characterization with conventional time-dependent dielectric breakdown (TDDB) technique. A new technique, the time-dependent dielectric wearout (TDDW), is proposed as a more practical and effective way to measure oxide reliability and breakdown compared to conventional TDDB methodology. The wearout of oxide is defined as the gate current reaches a critical current density with the circuit operating voltage level. It is shown that although a noisy soft breakdown always exists for ultrathin oxide, with constant-voltage stressing, a big runaway can also be observed for oxides down to 1.8 nm by monitoring the I–V characteristics at a reduced voltage. Devices are found still working after soft breakdowns, but no longer functional after the big runaway. However, by applying E-model to project dielectric lifetime, it shows that the dielectric lifetime is almost infinity for the thermal oxide at 1.8 nm range. It is also demonstrated that the dual voltage TDDW technique is also able to monitor the breakdown mechanism for nitride/oxide (N/O) dual layer dielectrics.     

New insights in the relation between electron trap generation andthe statistical properties of oxide breakdown

In this paper it is demonstrated in a wide stress field range that breakdown in thin oxide layers occurs as soon as a critical density of neutral electron traps in the oxide is reached. It is proven that this corresponds to a critical hole fluence, since a unique relationship between electron trap generation and hole fluence is found independent of stress field and oxide thickness. In this way literature models relating breakdown to hole fluence or to trap generation are linked. A new model for intrinsic breakdown, based on a percolation concept, is proposed. It is shown that this model can explain the experimentally observed statistical features of the breakdown distribution, such as the increasing spread of the Q_BD-distribution for ultrathin oxides. An important consequence of this large spread is the strong area dependence of the Q_BD for ultrathin oxides     

On a universal parameter of intrinsic oxide breakdown based onanalysis of trap-generation characteristics

It is found, even at room temperature, that hole fluence to breakdown Q_p of wet oxides is not a constant value for different oxide fields, but has a strong stress-electric-field dependence. Based on the neutral trap-generation characteristics related to SILC, this oxide-breakdown behavior dependent on the stress-electric field is analyzed. A novel model is proposed in which oxide breakdown is triggered when the current level of steady-state SILC via electron tunneling between traps reaches a critical value. From the spatial distribution of traps, we have concentrated on the critical trap pair whose electron-tunneling probability has the smallest value in the middle of the SiO₂ films. To verify this model, the convoluted trap density which is related to the electron-tunneling probability between the critical trap pair is investigated. As a result, it is found that this convoluted trap density remains constant regardless of stress-electric field and oxide thickness. This means that this convoluted trap density is a universal parameter for oxide breakdown