A new electronically tunable current mode universal filter using MO-CCCII

A new electronically tunable universal current mode biquad filter structure employing three multiple output current controlled conveyors (MOCCCII) and two grounded capacitors is presented. The proposed filter offers the following advantageous features: low input impedance and high output impedance—a desirable property of current mode filters; realization of low pass, band pass, high pass, notch, and all pass; no matching constraint; low sensitivity performance and use of grounded capacitors suitable for integration. The practical design problems due to nonlinearities of MOCCCIIs have also been addressed. The feasibility of the design is confirmed via SPICE simulations.     

New CCII-based versatile structure for realizing PID controller and instrumentation amplifier

In this paper, a novel two-input two-output current-mode (CM) circuit for providing proportional-integral-derivative (PID) controller and instrumentation amplifier (IA) responses, depending on the passive component selection, is presented. The developed circuit uses only grounded capacitors (PID controller selection) and only grounded resistors (IA choice); accordingly, it is convenient for integrated circuit (IC) fabrication. The proposed new configuration can simultaneously realize both gain variable non-inverting and inverting responses without requiring extra additional components. The proposed topology for providing high output impedance currents can be easily cascaded with other CM structures. Finally, some time domain and frequency domain analysis with SPICE simulation program and experimental results are included to show workability and effectiveness of the proposed circuit.     

Minimum component SRCO and VFO using a single DVCCC

Two oscillator topologies each employing a single differential voltage complementary current conveyor (DVCCC) are presented. The first oscillator uses a single active element, five passive components, grounded capacitors, has independent control of frequency and condition of oscillation. It has a current mode output and can be extended to provide a voltage mode output. It combines all the features of the current state-of-art oscillators. The second oscillator uses a single DVCCC, four passive elements, grounded capacitors and provides independent control of frequency. This oscillator not only has all the desired oscillator features, but requires lesser passive components. Theoretical analysis of these oscillators was verified with SPICE simulations.     

On the realization of DO-OTA-C oscillators

The basic aim of this paper is to give design considerations of current-mode high frequency DO-OTA-C oscillator topologies achieving noninteractive control of b and ω_o with a minimum number of components. Starting from DO-OTA-C (grounded capacitor) filter topologies reported in the literature and employing a minimum number of components, novel DO-OTA-C oscillator topologies are generated by converting filters into oscillators. Furthermore, the influence of the OTA nonidealities on oscillator performance is investigated. The performance of the proposed topologies are demonstrated with SPICE simulation program. The oscillator configurations provide frequency control by changing the OTA transconductances with biasing currents without affecting oscillation condition and are very suitable for VLSI design since they are composed only of DO-OTAs and grounded capacitors.     

Power distribution networks for system-on-package: status and challenges

The power consumption of microprocessors is increasing at an alarming rate leading to 2X reduction in the power distribution impedance for every product generation. In the last decade, high I/O ball grid array (BGA) packages have replaced quad flat pack (QFP) packages for lowering the inductance. Similarly, multilayered printed circuit boards loaded with decoupling capacitors are being used to meet the target impedance. With the trend toward system-on-package (SOP) architectures, the power distribution needs can only increase, further reducing the target impedance and increasing the isolation characteristics required. This paper provides an overview on the design of power distribution networks for digital and mixed-signal systems with emphasis on design tools, decoupling, measurements, and emerging technologies.     

Distributed matched bypassing for board-level power distribution networks

Power-distribution networks need to provide impedance response with specified shape/value over a wide frequency band. Bypass capacitors with different values, and capacitors and planes may create resonance peaks, unless the capacitor parameters are selected properly. Distributed matched bypassing (DMB) is suggested to create a smooth impedance profile. DMB requires components with Q/spl Lt/1, which in turn requires user-defined ESR. Different options are shown to set (increase) the ESR of bypass capacitors. The concepts of bypass quality factor (BQF) and bypass resistor (BR) are introduced.     

An efficient approach for power delivery network design with closed-form expressions for parasitic interconnect inductances

Investigation of a dc power delivery network, consisting of a multilayer PCB using area fills for power and return, involves the distributed behavior of the power/ground planes and the parasitics associated with the lumped components mounted on it. Full-wave methods are often employed to study the power integrity problem. While full-wave methods can be accurate, they are time and memory consuming. The cavity model of a rectangular structure has previously been employed to efficiently analyze the simultaneous switching noise (SSN) in the power distribution network. However, a large number of modes in the cavity model are needed to accurately simulate the impedance associated with the vias, leading to computational inefficiency. A fast approach is detailed herein to accelerate calculation of the summation associated with the higher-order modes. Closed-form expressions for the parasitics associated with the interconnects of the decoupling capacitors are also introduced. Combining the fast calculation of the cavity models of regularly shaped planar circuits, a segmentation method, and closed-form expressions for the parasitics, an efficient approach is proposed herein to analyze an arbitrary shaped power distribution network. While it may take many hours for a full-wave method to do a single simulation, the proposed method can generally perform the simulation with good accuracy in several minutes. Another advantage of the proposed method is that a SPICE equivalent circuit of the power distribution network can be derived. This allows both frequency and transient responses to be done with SPICE simulation.     

Software-based analysis of radio frequency plasma display panel forefficient design and impedance matching

A full software analysis technique for the radio frequency (RF) plasma display panel (PDP) has been developed. The RF PDP test panel has been analyzed by the segmentation/three-dimensional (3-D) parameter extraction/SPICE simulation scheme, which was originally developed for the analysis of RF complimentary metal oxide semiconductor (CMOS) chips. Our technique is shown to be accurate in predicting the input impedance of the RF port and the calculated input impedance is used to perform impedance matching of the system. The technique is also extendable to a much larger size RF-PDP and has the possibility of being applied to the design and analysis of various interesting RF systems and components     

音响分频器使用的有机薄膜电容器

音响分频器中使用的有机薄膜电容器 ,其阻抗和损耗频率特性的优劣直接影响分频器的阻抗及功率特性 ,从而影响音响的质量。在选用电容器时 ,应注意 :1选用无感式卷绕的金属化有机薄膜电容器 ,使 LESL趋于零 ;2选用边缘加厚的金属化有机薄膜电容器 ,降低极板电阻、接触电阻和接触损耗 ,改善电容器的阻抗和损耗频率特性 ,满足分频器的阻抗匹配和功率匹配的要求 ;3首选粗短结构的电容器 ;4选用圆形结构电容器 ,避免连续性自愈发生。正确选择优质电容器 ,满足良好的听觉效果。     

基于改进目标阻抗的电源分配网络设计方法

针对目前电源分配网络设计中传统目标阻抗法带来的过度设计问题,提出了一种基于改进目标阻抗的电源分配网络设计方法。与传统目标阻抗不同的是,该方法提出的目标阻抗为电阻和电感的若干组组合,它在频域上表现为一条阻抗值随频率上升的曲线。在实际操作中,在满足该目标阻抗的情况下,选择使用电容器个数最少的一组组合当作最优目标阻抗。用Matlab实现了该方法的PDN设计工具,实验表明,该方法与传统目标阻抗法相比,对于高频段PDN网络设计限制更少,去耦电容器使用个数更少,具有较强的实用性。     

Efficient Distributed On-Chip Decoupling Capacitors for Nanoscale ICs

A distributed on-chip decoupling capacitor network is proposed in this paper. A system of distributed on-chip decoupling capacitors is shown to provide an efficient solution for providing the required on-chip decoupling capacitance under existing technology constraints. In a system of distributed on-chip decoupling capacitors, each capacitor is sized based on the parasitic impedance of the power distribution grid. Various tradeoffs in a system of distributed on-chip decoupling capacitors are also discussed. Related simulation results for typical values of on-chip parasitic resistance are also presented. The worst case error is 0.003% as compared to SPICE.      

An electronically tunable current-mode quadrature oscillator using PCAs

This article presents a new realisation of active RC sinusoidal oscillator with electronically tunable condition and frequency of oscillation (FO). As compared to the class of three resistors, two capacitors (3R-2C)-based canonic oscillators, the circuit proposed here uses only two resistors and two capacitors as the passive components and still provides non-interactive tuning laws for the condition of oscillation and the FO. The proposed circuit employs new bipolar programmable current amplifier as the active building block and is capable of simultaneously providing two explicit quadrature current outputs. SPICE simulation results have been included to verify the workability of the circuit as an oscillator and the tuning range of the FO.     

Modeling of power distribution systems for high-performancemicroprocessors

This paper presents approximate techniques for building models and simulating the response of power distribution systems for high-performance microprocessors. Several distributed equivalent SPICE circuit models were built by extracting the appropriate resistance, inductance, capacitance (RLC) component values using a combination of two-dimensional (2-D) and three-dimensional (3-D) quasi-static field solvers. They were used to assess how well such effects as system transfer impedance and transient characteristics can be predicted. The models include the chip, its controlled collapsed chip connection (C4) connections to the package, the power distribution structure in the package, connector and motherboard. It is found that the response of the entire power system can be treated as a second order system, by which the main features of the performance of the power delivery network are assessed. Samples of transient and frequency domain data for typical microprocessors are given and the effects of some design options are discussed, as are the tradeoffs in model complexity versus the gain of useful design information     

Modeling the effects of nonlinear materials in ceramic chipcapacitors for use in digital and analog applications

This paper describes a physics-based numerical approach to building circuit models for electronic components that are made of nonlinear dielectrics. The resulting models are intended for use in time-domain circuit simulators to assess the effects of material nonlinearity on the electrical performance of such components as discrete de-coupling and filter capacitors that are used in digital and analog circuits. A 3-D electrostatic field solver is modified to take into account the nonlinear field dependence of the dielectric material and is employed to calculate the Q-V curve for any capacitive structure. Subsequently, a time integration method (similar to that used in SPICE) is utilized to devise an appropriate time-stepping algorithm for the current-charge relationship of a nonlinear capacitor that can be used to simulate its time-domain electrical characteristics. Sample results are provided to illustrate the methodology and the effects of the material nonlinearity on the performance of the capacitor     

A new 5th-order differential type class-AB log-domain elliptic lowpass filter for video frequency applications

This paper proposes a new current-mode 5th-order differential type class-AB log-domain elliptic lowpass filter for video frequency applications. The design is based on the state-space synthesis method. The proposed filter has 5.75 MHz cut-off frequency with maximum 0.177 dB passband ripple and attenuation greater than 40 dB at 7.88 MHz. Only BJTs and grounded capacitors were used, and operated with single power supply of 2.5 V. Since the parameters of proposed filter are tunable, it is easy to control of cut-off frequency. This adjustment is accomplished by changing external currents. SPICE simulations are given to confirm the theoretical analysis. For this purpose, the filter is simulated by using both idealized BJT models and AT&T CBIC-U2 type transistors.     

Modeling, analysis and design of resonant free power distribution network for modern microprocessor systems

This paper presents design-oriented analysis of the power distribution network (PDN) for high performance microprocessor systems to realize the resonant free, close to flat output impedance magnitude over a wide frequency range. Based on the frequency domain analysis, closed form design equations and parametric curves relating the system parameters are derived. A systematic method of estimating the optimum parameters of the decoupling capacitors used in a single or multistage PDN is described to realize the output impedance of specified magnitude for the noise-free, and critically damped voltage at the microprocessor core. The design examples and simulation results are discussed to demonstrate the application of the design equations and parametric curves.     

High output impedance current-mode universal biquadratic filters with five inputs using multi-output CCIIs

Three current-mode universal biquadratic filters each with five input terminals and one output terminal are presented. The first proposed circuit uses three multi-output second-generation current conveyors, two grounded capacitors and three resistors. This circuit offers the following advantageous features: orthogonal controllability of resonance angular frequency and quality factor, high output impedance, the versatility to synthesize all standard filter types without component matching condition and using grounded capacitors. The second proposed circuit uses three multi-output second-generation current conveyors, two grounded capacitors and two resistors. This circuit offers the following advantageous features: using minimum passive components, high output impedance, the versatility to synthesize all standard filter types without component matching condition and using grounded capacitors. The third proposed circuit uses three multi-output second-generation current conveyors, two grounded capacitors and three grounded resistors. This circuit offers the following advantageous features: the versatility to synthesize all standard filter types, high output impedance and using only grounded passive components. Each of the proposed circuits can get five kinds of filter functions by using only one current input signal.     

Current-mode continuous-time filters using complementary current mirror pairs

A design of current-mode continuous-time filters for low voltage and high frequency applications using complementary bipolar current mirror pairs is presented. The proposed current-mode filters consist of simple bipolar current mirrors and capacitors and are quite suitable for monolithic integration. Since the filters are based on the integrator type of realization, the proposed method can be used for a wide range of applications. The frequency of the filters can easily be changed by the DC controlling current. A fifth-order Butterworth and a third-order leapfrog filter with tunable cutoff frequencies from 20 MHz to 100 MHz are designed as examples and simulated by SPICE using standard bipolar parameters.     

Novel voltage/current-mode quadrature oscillator using current differencing transconductance amplifier

This letter proposes a new realization of voltage/current-mode (CM) quadrature oscillator (QO) using Current Differencing Transconductance Amplifier (CDTA) as the active element. The proposed circuit employs canonic number of components, namely two CDTAs, one resistor and two grounded capacitors. The oscillator is capable of providing two explicit quadrature current outputs and two quadrature voltage outputs. Moreover, the circuit enjoys the advantage of independent control of condition of oscillation (CO) and frequency of oscillation (FO). The non-ideal analysis and sensitivity study of the circuit has been carried out and the circuit exhibits a good sensitivity performance. B2SPICE simulation results are included that validate the working of the circuit.     

A Novel High CMRR High Input Impedance Differential Voltage-Mode KHN-Biquad Employing DO-DDCCs

In this work, a novel circuit configuration for realizing a differential voltage-mode Kerwin-Huelsman-Newcomb (KHN) biquad filter with high common-mode rejection ratio (CMRR) is presented. The proposed circuit is based on using the dual output differential difference current conveyor (DO-DDCC). The circuit uses three DO-DDCCs, two capacitors and five resistors. All the passive elements are grounded, which is important in integrated circuit implementation point of view. The differential voltage input signal is applied to high input impedance terminals, which is important in the voltage-mode operations. SPICE simulation results are included to verify the theory.