ZVT-PWM反激变换电路研究与设计

对恒频零电压转换（ＺＶＴ－ＰＷＭ）反激变换器进行了研究与设计。采用ＨＥＸＳＥＮＳＥ ５端结构的ＭＯＳＦＥＴ,研制成１２Ｖ／６Ａ ２５０ｋＨｚ ＤＣ／ＤＣ变换器,并给出了实验结果。     

系统电压畸变时STATCOM的运动性能研究

基于ＳＴＡＴＣＯＭ的标幺值数学模型,研究了系统电压畸变条件下ＳＴＡＴＣＯＭ的电压电流运行特性,讨论了ＳＴＡＴＣＯＭ谐波电压电流与装置主电路参数的关系,给出了ＬＣ谐波条件,理论分析结果得到了ＰＳＣＡＤ／ＥＭＴＤＣ数字仿真以及１０ｋｖａｒ ＳＴＡＴＣＯＭ动模装置实验的双重验证。     

用于三相桥式电路的600V驱动集成电路

介绍了一种６００Ｖ单片式智能驱动集成电路，它可连接ＴＴＬ，ＣＭＯＳ逻辑电路与三相桥式电路之间，用以驱动ＭＯＳ栅极器件。本文给出了该驱动电路在步进电机，高频镇流器中的应用电路。     

MOS控制晶闸管（MCT）的设计

讨论了ＭＣＴ的结构设计及耐压设计。通过对结构参数的最佳化选择，制造出开关电流９Ａ，耐压９００Ｖ的ＭＣＴ芯片。ｎ沟ＭＯＳ阈值电压为２Ｖ，ｐ沟ＭＯＳ阈值电压为－５Ｖ。当门极加－７Ｖ电压时，其关断电流密度为２２０Ａ／ｃｍ＾２。     

零电压谐振开关电源在机载设备中的应用

介绍了一种半桥工作方式的零电压准谐振开关ＤＣ－ＤＣ变换器；描述了该变换器的原理和特点；给出了应用零电压谐振开关技术和集成控制块ＭＣ３３０６６的５Ｖ／２０ＡＤＣ－ＤＣ变换器电路和试验结果。     

基于E-dot探头的冲击电压测量系统

介绍了基于Ｅ－ｄｏｔ探头的冲击电压测量系统的原理和特点,研制了一套用于测量真空中绝缘子上冲击电压的Ｅ－ｄｏｔ冲击电压测量系统,同时利用ＰＳＰＩＣＥ电路分析软件对所研制的冲击电压测量系统进行了分析和优化。通过利用美国ＰＥＲＳＯＮ公司的ＶＤ－３０５Ａ 型分压器对该系统进行校验后的结果表明,该系统完全可以用于冲击电压的测量。     

EO227脱排油烟机自动控制电路

ＥＯ２２７脱排油烟机自动控制电路张景水ＥＯ２２７是为脱排油烟机全自动工作而专门设计制造的ＣＭＯＳ集成电路。该电路有电源电压范围宽，静态功耗低，外接元件少，简单可靠等优点。加电工作时，即处于自动状态，有油烟或煤气时，即自动打开排风机，并发出报答信号；抽...     

DVD 与计算机

ＤＶＤ与计算机ＣＤ－ＲＯＭ光驱和光盘已成为计算机的标准配置之一,但现在,ＤＶＤ－ＲＯＭ光驱和光盘则将取代它们。不过真正实现还需要一定的时间。ＤＶＤ－ＲＯＭ同ＣＤ－ＲＯＭ相比,其最大优势在于存储容量更大。ＤＶＤ－ＲＯＭ的数据存储容量为４．７ＧＢ,约为Ｃ...     

CMOS集成电路功能测试方法及实现

文中根据ＣＭＯＳ集成电路的特点,阐述了利用ＰＣ机进行ＣＭＯＳ集成电路功能测试,逻辑仿真及其系统实现方法,文中介绍的方法,可对各种通用,专用ＣＭＯＳ数字集成电路芯片及其应用电路,进行电路功能测试和逻辑仿真。     

WINDOWS95操作系统下的串并行仪器接口开发

本文介绍了在ＷＩＮＤＯＷＳ９５操作条件下,如何开发中并行仪器接口,包括ＧＰ－ＩＢ并行接口和ＲＳ－２３２Ｃ串行接口,以实现微机与测量仪器的连接,从而建立虚拟仪器,并以ＶＩＳＵＡＬ ＢＡＳＩＣ平台为例,列举了利用ＭＳＣＯＭＭ控件实现串行仪器接口的部分程序。     

基于数字电位器的可编程稳压器设计

数字电位器亦称数控可编程电阻器或数控电位器。它是采用CMOS工艺制成的数字-模拟混合信号处理集成电路,是一种颇具发展前景的新型电子器件。详细阐述了基于数字电位器的可编程线性稳压器、开关式稳压器的电路设计原理、设计要点及使用注意事项。     

Complete delay modeling of sub‐threshold CMOS logic gates for low‐power application

In this paper, the propagation delay of a complementary metal‐oxide semiconductor (CMOS) inverter circuit in sub‐threshold regime has been analyzed thoroughly with respect to variable loads, rise and fall time of input, device dimensions and temperature, without neglecting the significant drain induced barrier lowering (DIBL) and body bias effects. In particular, sub‐threshold slope factor and current strength have been modeled with respect to temperature, which would be efficacious for the analysis of sub‐threshold circuit as temperature plays an important role in propagation delay. Transistor stacking has also been modeled considering variation in threshold voltage, sub‐threshold slope factor and DIBL coefficient owing mainly to fluctuation in doping levels. The CMOS inverter delay model together with transistor stacking model has been incorporated in the analysis of propagation delays of NAND and NOR gates. Extensive simulations have been performed under 45 and 22 nm CMOS technology using simulation program with integrated circuit emphasis (SPICE) to ensure the correctness of the analysis. Simulation shows that this model is applicable for the analysis of digital sub‐threshold circuit in sub‐90 nm technology. Copyright © 2015 John Wiley & Sons, Ltd.     

A flexible current‐mode classifier circuit and its applications

In this paper a new CMOS classifier circuit is presented, simulated, and compared with other recently introduced circuits. The proposed CMOS circuit operates in current‐mode and can classify several types of data. The architecture is designed using two threshold circuits and a subtraction circuit. Among many possible applications of the classifier circuit, template‐based pattern classification, namely template matching and character recognition with corruption, and in another direction its use as a quantizer are given. Using 0.35‐ µm AMS technology parameters, SPICE simulations as well as hard realization results for the classifier and application circuits are included; detailed Monte Carlo analyses to assess parameter mismatch effects are also performed. Copyright © 2010 John Wiley & Sons, Ltd.     

High-Power Integrated Stimulator Output Stages With Floating Discharge Over a Wide Voltage Range for Nerve Stimulation

Two integrated nerve stimulator circuits are described. Both generate passively charge-balanced biphasic stimulating pulses of 1 to 16 mA with 10-$mu $s to 1-ms widths from 6- to 24-V supplies for implanted book electrodes. In both circuits, the electrodes are floating during the passive discharge anywhere within the range of the power rails, which may be up to 24 V. The first circuit is used for stimulation only. It uses a floating depletion transistor to enable continuous discharge of the electrodes, except when stimulating, without using power. The second circuit also allows neural signals to be recorded from the same tripole. It uses a modified floating complementary metal–oxide semiconductor (CMOS) discharge switch capable of operating over a range beyond the gate-to-source voltage limits of its transistors. It remains off for long periods using no power while recording. A 0.6-$mu $m silicon-on-insulator CMOS technology has been used. The measured performance of the circuits has been verified using multiple tripoles in saline.      

Statistical forecasting algorithm on circuit level gain transformation due to negative bias temperature instability for the microwave frequency spectrum

Negative Bias Temperature Instability (NBTI) is a critical reliability issue for CMOS technology, as this directly impacts the CMOS circuit performance parameters causing system failure. Moreover, NBTI behavior for radio frequency (RF) signals needs more understanding. On the device level, there has been much research on the relation between NBTI and RF. Many of those works contradict each other on the question of RF dependency with NBTI. Hence, the behavior of NBTI must be analyzed at the circuit level using a prediction technique. In this article, we analyzed the circuit level impact of NBTI for microwave frequency and developed a gain transformation technique for RF circuits in the microwave frequency range. To do this, we employed a 65 nm conventional ring oscillator as an RF block and carried out an aging simulation on it. A compatibility analysis was performed on low and high bandwidth microwave signals. The implemented statistical technique can determine the actual operable frequency range, so that the RF circuit can perform with minimal NBTI effect.     

Adaptive equalizer in CMOS

A mixed-signal short/long-haul adaptive equalizer suitable for high-speed T1/E1/J1 applications in CMOS is presented. The manufactured circuit recovers distorted incoming signals attenuated from 0 to 44dB (max.), occupies an area of 1.2 x 1.8 mm in a CMOS 0.35 /spl mu/ process, and typically requires 120 mW of power at 3.3V. The unshielded twisted pair (UTP) cable models are stored in a local random access memory (RAM) and can be easily reprogrammed. This circuit is the first commerical, single-channel, 3.3V-power supply, short/long-haul T1/E1/J1 device.     

Parametric yield optimization of CMOS analogue circuits by quadratic statistical circuit performance models

A major bottleneck in the design and parametric yield optimization of CMOS integrated circuits lies in the high cost of the circuit simulations. One method that significantly reduces the simulation cost is to approximate the circuit performances by fitted quadratic models and then use these computationally inexpensive models to optimize the parametric yield. In this paper quadratic statistical circuit performance models are applied to maximize the parametric yield of CMOS analogue circuits. It is found that quadratic polynomials may not always model the circuit performances well. However, with engineering knowledge applied to identify and reduce the causes of the errors, accurate performance models and yield maximization can be achieved with a reasonably small number of circuit simulations, as illustrated through examples. Distinctions between the present method and previous applications of quadratic modelling to statistical circuit design are made.     

Analysis and optimization of a novel biasing for constant‐gain CMOS open‐loop amplifiers

A replica biasing circuit is presented which allows open‐loop gain in CMOS amplifiers to be accurately set. The proposed solution is a new biasing which takes advantage of a triode‐biased transistor instead of the ΔV_GS approach which is the traditional one. The circuit can be applied to both RF and IF amplifiers which are based on resistive loads in order to achieve high‐frequency and/or low‐noise performance. A detailed analysis of second‐order effects is then given which emphasizes the effects due to mobility degradation, channel‐length modulation and threshold voltage mismatches. Simulated results show a good sensitivity to process variations. Copyright © 2001 John Wiley & Sons, Ltd.     

A novel,low‐complexity,high‐speed envelope detector and its applications

A compact and effective transmission envelope detector (TED), which can detect whether the absolute amplitude of an input differential signal is larger than a threshold or not, is proposed. The TED has been demonstrated to be applicable for received signal strength indicator circuit in wireless communication receivers or power management systems, and mode‐control circuit in bidirectional optical transceivers. Implemented in a 0.18 µm CMOS technology, the TED has a response time of 210 ps at 5 Gbps, occupies an active area of 0.05 mm², and consumes 1 mA from 1.8 V supply. Copyright © 2011 John Wiley & Sons, Ltd.     

Low-Power Circuits for the Bidirectional Wireless Monitoring System of the Orthopedic Implants

This paper proposes an architecture of the wireless monitoring system for the real-time monitoring of the orthopedic implants, which monitors the implant duty cycle, detects abnormal asymmetry, high amounts of force, and other conditions of the orthopedic implants. Data for diagnosis are communicated wirelessly by the radio-frequency (RF) signal between the embedded chip and the remote circuit. In different working modes, the system can be powered by the RF signal or stiff lead zirconate–titanate (PZT) ceramics which are able to convert mechanical energy inside the orthopedic implant into electrical energy. The power circuits with a variable ratio switched-capacitor (SC) dc–dc converter have been taped out with 0.35-$mu$m complementary metal–oxide semiconductor (CMOS) technology. The test results show that the SC converter can transfer the input voltage that ranges from 5 V to 14 V from the PZT ceramics into the voltage ranging from 2 V to 2.5 V which will be dealt with by a low drop-out circuit in the future work. The total efficiency of the SC converter is from 28% to 42% at full-time working mode. The analog-to-digital converter (ADC) circuits have been fabricated in a 0.18-$mu$m 1P6M CMOS process. The test results show that the ADC chip consumes only 12.5 $mu$W in working mode and 150 nW in the sleep mode. The circuits, including RF circuits, ADC, and the microcontrol unit, have been implemented in a 0.18-$mu$ m CMOS process. Future work includes some clinical experiments test in the application where PZT elements are used for power generation in total knee-replacement implants.